JPH1125679A - Sense amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sense amplifier having low power consumption and high reliability. SOLUTION: A sense amplifier 50 is provided with a sense amplifier section 51 outputting data by a potential difference generated in signal lines BL, BLB conforming to data stored in a memory cell; a detecting circuit 52 outputting a data read-out detecting signal (O) of a high level indicating that data is read out based on potential difference of signal lines BL and BLB generated at the time of reading out data; a data latch circuit 55 latching data outputted from the sense amplifier 51 based on the data read-out detecting signal (O) of a high level; and a NAND circuit 65 outputting an activation control signal making the sense amplifier section 51 a non-activation state based on the data read-out detecting signal (O) of a high level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier for reading data used in a semiconductor memory device such as a ROM or a RAM.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional current mirror type sense amplifier. In this sense amplifier, gates of N-channel transistors 13 and 14 are connected to signal lines BL and BLB to which an output signal from a memory cell (not shown) is supplied. The transistors 13 and 14 are grounded via an N-channel transistor 15 to which a signal (SE: activation control signal) is input to the gate. The drain of the transistor 13 is connected to the gate and the drain of the P-channel transistor 11, and the drain of the transistor 14 is connected to the drain of the P-channel transistor 12, respectively. The sources of the transistors 11 and 12 are respectively connected to the power supply voltage Vcc. In this sense amplifier, the connection point between the transistor 12 and the transistor 14 becomes the output OUT.

In this sense amplifier, when data "1" stored in a memory cell (not shown) is read, signal lines BL and BLB are precharged and signal line B is read.
After L and BLB go high, an output signal from the memory cell is applied to signal lines BL and BLB.
Then, the signal line BL is maintained at the high level,
The signal line BLB falls toward the low level,
A high-level signal indicating data "1" is output from the output OUT. On the other hand, when reading data "0", the signal lines BL and BLB are precharged, and after the signal lines BL and BLB become high level,
An output signal from the memory cell is applied to signal lines BL and BLB.
Given to. Then, the signal line BLB is maintained at the high level, the signal line BL falls toward the low level, and a low-level signal indicating data “0” is output from the output OUT.

In the sense amplifier, data is read from the memory cell as described above, and the signal line BL or the signal line BLB is maintained at a high level from the start to the end of the data read. As a result, the current continues to flow from the power supply voltage Vcc via the transistors 11, 13, 15 or the transistors 12, 14, 15, and there is a problem that power consumption increases.

A technique for preventing current from continuing to flow from the start of data reading to the end thereof to reduce power consumption has been proposed in Japanese Patent Publication No. 7-43938. FIG. 5 is a circuit diagram schematically showing an internal configuration of a sense amplifier using this technique. In this sense amplifier, a P-channel transistor 16 and a P-channel transistor 16 are connected between the sources of the transistors 11 and 12 and the power supply voltage Vcc.
17 are interposed so that each source is connected to the power supply voltage Vcc. These transistors 16,
Reference numeral 17 indicates that each gate is cross-connected to the signal line BL and the signal line BLB via inverters 18 and 19.

In this sense amplifier, when data "1" of a memory cell (not shown) is read, signal lines BL and B are read.
LB is precharged and the signal lines BL, BLB
Becomes high level, an output signal from the memory cell is applied to the signal lines BL and BLB. The signal line BL is maintained at the high level, the signal line BLB falls toward the low level, and a high-level signal indicating the data “1” of the memory cell is output from the output OUT. When the signal line BLB falls to the low level, the transistor 16 to which the voltage level of the signal line BLB is applied via the inverter 19 is turned on.
The state becomes the FF state. On the other hand, when data "0" of a memory cell (not shown) is read, signal lines BL and BLB
Is performed, and after the signal lines BL and BLB become high level, an output signal is supplied from the memory cell to the signal lines BL and BLB. Signal line BL
B is maintained at the high level, the signal line BL falls toward the low level, and a high-level signal indicating the data “0” of the memory cell is output from the output OUT. When the signal line BL falls to a low level, the voltage level of the signal line BL is changed to the level of the inverter 1.
The transistor 17 provided via the switch 8 is turned off. Therefore, in this sense amplifier, the data in the memory cell is read, and one of the signal lines BL and BLB falls to a low level, whereby the transistor 16 or the transistor 17 is turned off, and the current from the power supply voltage Vcc is reduced. It is prevented from continuing to flow. Therefore, power consumption in the sense amplifier is reduced.

Japanese Patent Application Laid-Open No. Hei 8-279296 proposes another technique for preventing a current from continuing to flow from the start to the end of data reading to reduce power consumption. FIG. 6 is a circuit diagram showing a schematic configuration of a sense amplifier using this technique. The sense amplifier unit 20 includes a P-channel transistor 25 whose source is connected to the power supply voltage Vcc between the transistors 11 and 12 and the power supply Vcc, instead of the transistor 15 of the sense amplifier shown in FIGS. It was dressed. An activation control signal is applied to the gate of the transistor 25, and the transistor 25 is turned on / off to set the sense amplifier section 20 in an active state / inactive state. The NAND circuit 31 having two input terminals receives a signal (SIN: for example, a clock signal) and an inverter 32
The activation control signal is generated by a feedback signal from the data latch circuit 21 described later, which is provided via the data latch circuit 21. The data latch circuit 21 includes elements 27 to 30, inputs a signal from an output OUT, and outputs the signal from an output SOUT. This signal is the output SOU
Output from T and as a feedback signal,
This is supplied to the NAND circuit 31 and a NAND circuit 34 having two input terminals. The NAND circuit 34 generates a latch control signal based on the feedback signal and the signal (SIN), and outputs the latch control signal to the data latch circuit 21. The data latch circuit 21 latches a signal from the output OUT based on a latch control signal. An N-channel transistor 36 is interposed between the output OUT between the sense amplifier section 20 and the data latch circuit 21 and the ground. An activation control signal is supplied to the gate of the transistor 36. When a high-level activation control signal is supplied, the transistor 36 is turned off.
N, a low level signal is given to the data latch circuit 21.

A case where data "1" is read from a memory cell (not shown) in the sense amplifier having the above configuration shown in FIG. 6 will be described. First, before reading data, the signal lines BL and BLB are precharged and set to a high level. When the signal (SIN) rises to a high level, a low-level activation control signal is given to the sense amplifier unit 20. When a low-level activation control signal is supplied, the transistor 25 is turned on,
The sense amplifier unit 20 is activated.

An output signal from a memory cell is applied to the precharged signal lines BL and BLB, and the signal line BL is maintained at a high level.
B falls toward a low level. Then, a high-level signal indicating data “1” is output from the output OUT of the sense amplifier unit 20. This high level signal
The output from the data latch circuit 21 and the feedback signal of the inverter 32 and the NAND circuit 3
4 given. NAND through the inverter 32
When the high-level feedback signal is supplied to the circuit 31, the NAND circuit 31 outputs a high-level activation control signal to the sense amplifier unit 20. This high-level activation control signal causes the transistor 25
The state becomes the FF state, and the sense amplifier section 20 becomes inactive. In this case, the NAND circuit 34 outputs a low-level latch control signal to the data latch circuit 21, and the data latch circuit 21 latches a high-level signal provided from the sense amplifier unit 20. Therefore, in the sense amplifier shown in FIG. 6, when data reading is started, the data latch circuit 21 latches the signal output from the sense amplifier unit 20, outputs the signal, and turns off the transistor 25. By setting the sense amplifier section 20 to the inactive state in this manner, power consumption is reduced.

[0010]

However, in the sense amplifier shown in FIG. 5, the high level voltage level on the signal line BL or the signal line BLB is equal to the power supply voltage Vc.
If the circuit configuration is less than c, the transistor 16
Alternatively, there is a problem in that the transistor 17 is not completely turned off, current continues to flow, and current consumption cannot be reduced.

In the prior art shown in FIG. 6, before data is read, the signal lines BL and BLB are precharged and the transistors 13 and 14 are turned on by setting the signal lines BL and BLB to a high level. I do. Thereafter, when the sense amplifier unit 20 is activated, noise (signal) is generated by a through current flowing in the sense amplifier unit 20.
Is generated, and the noise is output to the data latch circuit 21. Then, a latch control signal is given to the data latch circuit 21 by the noise, and the data latch circuit 21 may latch the noise. In this state, if an output signal is applied from the memory cell to the signal lines BL and BLB, the latched noise is output as data read from the memory cell, causing a problem.

An object of the present invention is to provide a highly reliable sense amplifier with low power consumption in view of the above problems.

[0013]

SUMMARY OF THE INVENTION A sense amplifier according to the present invention comprises: a set of signal lines to which an output signal from a memory cell is applied; and data stored in the memory cell according to an output of the set of signal lines. A sense amplifier that outputs a read detection signal indicating that data has been read from the memory cell based on the output of the one set of signal lines; and Activation control means for switching the sense amplifier section from an active state to an inactive state, and data latch means for holding an output of the sense amplifier section based on the read detection signal.

According to the above configuration, the detecting means does not output the read detection signal until it detects that the data stored in the memory cell has been read based on the outputs of the pair of signal lines. . That is, the read detection signal is output only after the data stored in the memory cell is read. Therefore, the data latch unit latches the output of the sense amplifier unit when the read detection signal is applied, so that noise is generated from the sense amplifier unit at the precharge stage before the output signal from the memory cell is applied. Even if it does, the noise will not be latched. For this reason, since the data latch means does not latch and output the noise as data read from the memory cell, it is possible to prevent a problem from occurring and improve reliability. Further, when the read detection signal is output, the activation control means switches the sense amplifier section from the activated state to the inactivated state. Therefore, it is possible to reliably prevent the current from continuing to flow in the sense amplifier unit without being affected by the circuit configuration unlike the related art, and to reduce the current consumption.

[0015] The detecting means may include voltage setting means for setting an output from the signal line to a full swing level.

Here, the output from the signal line may not be fully swung due to the circuit configuration, and if not, the ON / O of a transistor or the like constituting the detecting means is not turned on.
The FF operation becomes insufficient, and the current continues to flow in the detection means.

By providing the voltage setting means, the output from the signal line is set to the full swing level.
It is possible to prevent a current from continuing to flow in the detection means, and to reduce current consumption.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a sense amplifier according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an internal configuration of a sense amplifier 50 according to an embodiment of the present invention. In the sense amplifier unit 51 constituted by a current mirror circuit, an N-channel transistor 1 is connected to signal lines BL and BLB to which an output signal from a memory cell (not shown) is supplied.
3, 14 gates are connected respectively. And
The sources of the transistors 13 and 14 are grounded via an N-channel transistor 15 whose gate receives an inversion activation control signal (ISE) described later. The drain of the transistor 13 is connected to the gate and drain of the P-channel transistor 11 on the load side, and the drain of the transistor 14 is connected to the P-channel transistor 1 on the load side.
2 drain. The transistors 11, 1
2 have their sources connected to the power supply voltage Vcc.
In the sense amplifier section 51, a signal indicating data read from a memory cell (not shown) is output from a connection point between the drain of the transistor 12 and the drain of the transistor 14.

The signal lines BL and BLB are also connected to a detecting circuit 52 which is a detecting means for detecting that data has been read from the memory cell. The detection circuit 52 detects an output from the signal lines BL and BLB and outputs a data read detection signal (O) indicating that data has been read from the memory cell. The detection circuit 52
Are voltage setting circuits 59a and 59b and XOR circuit 62
And. The voltage setting circuits 59a and 59b are provided on each of the signal lines BL and BLB, respectively, and based on the output from each of the signal lines BL and BLB, the signal (no2),
(No1) are output. The XOR circuit 62 includes:
Signals (no2) and (no1) output from the voltage setting circuits 59a and 59b are input, and a data read detection signal (O) is output based on these signals.

The voltage setting circuits 59a and 59b include NAND circuits 60a and 60b having two input terminals and p-channel transistors 61a and 61b.
In the NAND circuits 60a and 60b, outputs from the signal lines BL and BLB are respectively input to one input terminal, a signal (ICE: chip enable signal) is input to the other input terminal, and a signal (no2) is output from an output terminal. ),
(No1) is output. This signal (no2), (no
1) is output to the XOR circuit 62 and also to the gates of the transistors 61a and 61b. The sources of the transistors 61a and 61b are connected to the power supply voltage V
cc, and the drains are connected to the signal lines BL and B.
Connected to LB. Then, the NAND circuit 60a,
When the signals (no2) and (no1) output from the signal line 60b are at a low level, that is, when the outputs from the signal lines BL and BLB are at a high level, this transistor 6
1a and 61b are turned ON. Then, the signal lines BL, B
The voltage level of the output from LB is set to power supply voltage Vcc. Therefore, even when the signal lines BL and BLB do not swing fully, the voltage setting circuits 59a and 59b can
The outputs from the signal lines BL and BLB are set to the full swing level. Therefore, the NAND circuits 60a and 60b
ON / OFF of the transistors formed therein can be reliably performed, and the current consumption in the NAND circuits 60a and 60b can be reduced.

The XOR circuit 62 outputs a data read detection signal (O) based on the signals (no2) and (no1) from the NAND circuits 60a and 60b. This X
The OR circuit 62 includes elements 80 to 84 as shown in FIG. 2. When both of the signals (no2) and (no1) are at a high level or a low level, a low-level data read detection signal ( O) and outputs the signal (no)
2) When (no1) has different signal levels, a high level data read detection signal (O) is output.
As described above, the XOR circuit 62 receives the full swing level signal (no) from the voltage setting circuits 59a and 59b.
2) and (no1), the XOR circuit 6
2 can be reliably turned on / off, and current consumption can be reduced.

The data latch circuit 55 includes elements 70 to 75
A signal output from the sense amplifier unit 51 is input via the NOR circuit 67 and the signal is output. Further, the data latch circuit 55 inputs the above-described data read detection signal (O) as a latch signal,
When a high-level data read detection signal (O) indicating that data has been detected is applied, the signal provided from NOR circuit 67 is latched and output.

One input terminal of a NAND circuit 65 having two input terminals as activation control means is connected to the detection circuit 5.
The data read detection signal (O) output from 2 is supplied via an inverter 64, and the other input terminal is supplied with a signal (CK: for example, a clock signal) for controlling data read. The NAND circuit 65 outputs an activation control signal for controlling the activated state or the inactivated state of the sense amplifier unit 51. This activation control signal is supplied to an inversion activation control signal (IS
E) is given to the sense amplifier unit 51. Therefore,
The NAND circuit 65 outputs a low-level activation control signal for activating the sense amplifier unit 51 when the high-level signal (CK) indicating data reading is applied, and additionally, the detection circuit 52 High-level data read detection signal (O) indicating that data has been read from
, A high-level activation control signal for inactivating the sense amplifier unit 51 is output.

The activation control signal output from the NAND circuit 65 is a NOR circuit 6 having two input terminals.
7 is also provided to one input terminal. This NOR circuit 67
Then, the signal output from the sense amplifier unit 51 is supplied to the other input terminal. Then, this NOR circuit 67
When a low-level activation control signal for activating the sense amplifier unit 51 is supplied to one input terminal, a signal supplied from the sense amplifier unit 51 is output to the data latch circuit 55. On the other hand, the NOR circuit 67 outputs a low-level signal to the data latch circuit 55 when a high-level activation control signal for deactivating the sense amplifier unit 51 is applied to one input terminal. by this,
A signal of a constant level can always be given to the data latch circuit 55, and the input of the data latch circuit 55 does not become unstable.

Further, the inversion activation control signal (ISE)
Is applied to the gate of a P-channel transistor 68 whose source is connected to the power supply voltage Vcc and whose drain is connected to the output side of the sense amplifier unit 51. This transistor 68
Is turned on when a low-level inversion activation control signal (ISE) for deactivating the sense amplifier unit 51 is applied, and instead of the signal output from the sense amplifier unit 51, the NOR circuit 67 (High level) signal. As a result, even when a signal is not supplied from the sense amplifier unit 51 to the NOR circuit 67, the NO
A constant level signal can be given to the R circuit 67.

FIG. 3 is a time chart for explaining a data read operation in sense amplifier 50. The operation of reading data from a memory cell in sense amplifier 50 having the above configuration will be described below.

(Precharge Operation) When a data read operation from a memory cell is started, first, signal lines BL,
BLB is precharged, and the signal lines BL, BL
B are both at a high level. Accordingly, the detection circuit 52 outputs a low-level data read detection signal (O) which does not indicate the data read state. As shown in FIG. 3A, when a signal (CK) for controlling data reading rises from a low level to a high level, a low-level activation control signal is output from the NAND circuit 65 as the activation control means. The high-level inversion activation control signal (ISE) is output to the sense amplifier 51 as shown in FIG.
Is entered. Transistor 15 of sense amplifier section 51
Is turned on, and the sense amplifier unit 51 is activated. At this time, as shown in FIG. 3 (i), the detection circuit 52 can detect the data reading, as shown in FIG.
A high-level signal (ICE) is input.

(Read operation of data "1") As described above, when the precharge operation of the signal lines BL and BLB is completed and an output signal is supplied from the memory cell to the signal lines BL and BLB, the signal line BL Is maintained at the high level, and the signal line BLB falls from the high level to the low level as shown in FIG.
Then, the sense amplifier unit 51 outputs a high-level signal indicating data “1”. This high level signal
The signal is output to the data latch circuit 55 as a low level signal via the NOR circuit 67. Data latch circuit 55
Outputs a high-level signal obtained by inverting the low-level signal from the NOR circuit 67, that is, data "1", as shown in FIG.

When the signal line BLB falls from the high level to the low level as shown in FIG. 3C, the signal (no) output from the voltage setting circuit 59b of the detection circuit 52
1) rises from a low level to a high level as shown in FIG. Then, as shown in FIG.
The XOR circuit 62 of the detection circuit 52 outputs a high-level data read detection signal (O).

The high level data read detection signal (O) is inverted by the inverter 64 and input to the NAND circuit 65. Then, the NAND circuit 65 outputs an activation control signal that has risen to a high level. As shown in FIG. 3B, the low-level inversion activation control signal (ISE) is supplied to the sense amplifier unit 51 via an inverter 66. Of the transistor 15. Therefore, the transistor 15 is turned off, and the sense amplifier 51 is deactivated.

When a high level data read detection signal (O) is applied from the detection circuit 52 to the data latch circuit 55, the data latch circuit 55 latches the output signal indicating data "1". Continue to output this signal.

(Read operation of data "0") As described above, when the precharge operation of the signal lines BL and BLB is completed and an output signal is supplied from the memory cell to the signal lines BL and BLB, the signal line BLB Is maintained at the high level, and the signal line BL falls from the high level to the low level as shown in FIG.
Then, the sense amplifier unit 51 outputs a low-level signal indicating data “0”. This low level signal is
The signal is output to the data latch circuit 55 as a high-level signal via the NOR circuit 67. Data latch circuit 55
Outputs a low-level signal obtained by inverting the high-level signal from the NOR circuit 67, that is, data "0", as shown by the dotted line in FIG.

When the signal line BL falls from the high level to the low level as shown in FIG. 3E, the signal (no) output from the voltage setting circuit 59a of the detection circuit 52 is output.
2) rises from a low level to a high level as shown in FIG. Then, as shown in FIG.
The XOR circuit 62 of the detection circuit 52 outputs a high-level data read detection signal (O).

As a result, as described above, a low-level inversion activation control signal (ISE) is applied to the transistor 15 of the sense amplifier unit 51, and the sense amplifier unit 5
1 is inactive. The data latch circuit 55
Latches the signal indicating the output data “0”,
Continue to output this signal.

As described above, the detection circuit 52 detects that the voltage level of one of the signal lines BL and BLB supplied with the output signal from the memory cell has fallen from the high level to the low level. A high level data read detection signal (O) indicating that data has been read from the memory cell is output. That is, the detection circuit 52 does not output a high-level data read detection signal (O) until data is read from the memory cell. When the high-level data read detection signal (O) is applied, the data latch circuit 55 latches the signal output at that time. Therefore, the data latch circuit 55 can latch only the data read from the memory cell. For this reason, the data latch circuit 55 does not output the noise output from the sense amplifier unit 51 during the precharge operation as data read from the memory cell, so that it is possible to prevent the occurrence of a defect and improve reliability. Can be improved.

Further, based on a data read detection signal (O) provided from detection circuit 52, an inversion activation control signal (ISE) is applied to sense amplifier unit 51, and sense amplifier unit 51 is set in an inactive state. Become. Therefore, the current does not continue to flow in the sense amplifier unit 51 from the start to the end of the data reading, so that the current consumption can be reduced.

Further, even when the signal lines BL and BLB have a circuit configuration in which the signal lines BL and BLB do not fully swing, the sense amplifier 51 is deactivated as described above, so that it is ensured that a current continues to flow in the sense amplifier 51. Can be prevented. The detection circuit 52 is connected to each of the signal lines BL and BLB.
Since the voltage setting circuits 59a and 59b for setting the voltage level of the output from the memory cell to the full swing level are provided, current does not continuously flow from the start to the end of data reading. Therefore, current consumption can be reduced more efficiently.

In the sense amplifier of the present embodiment,
In order to reduce current consumption in the detection circuit 52 more efficiently, the voltage setting circuits 59a, 59b
Is provided. However, the detection circuit 52
Does not include the voltage setting circuits 59a and 59b, and directly outputs signals from the signal lines BL and BLB to the XOR circuit 62.
May be provided.

[0040]

According to the above-described invention, after data is output from a memory cell, the sense amplifier is inactivated, and during the period from the start to the end of data reading,
Since the current does not continue to flow in the sense amplifier unit and the detection unit, current consumption can be reduced. Further, the data latch unit holds the output from the sense amplifier unit in response to the read detection signal given from the detection unit, so that the data latch unit reliably outputs data from the memory cell, thereby preventing the occurrence of a problem and Can be improved in reliability.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an internal configuration of a sense amplifier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of an XOR circuit of the detection circuit shown in FIG.

FIG. 3 is a time chart for explaining a data read operation in a sense amplifier.

FIG. 4 is a circuit diagram showing a conventional current mirror type sense amplifier.

FIG. 5 is a circuit diagram schematically showing an internal configuration of a conventional sense amplifier with reduced current consumption.

FIG. 6 is a circuit diagram schematically showing an internal configuration of another conventional sense amplifier in which current consumption is reduced.

[Explanation of symbols]

 Reference Signs List 51 Sense amplifier section 52 Detection circuit 55 Data latch circuit 59a, 59b Voltage setting circuit 65 NAND circuit ISE Inversion activation control signal O Data read detection signal

Claims (2)

[Claims] 1. A sense amplifier comprising: a set of signal lines to which an output signal from a memory cell is applied; and a sense amplifier unit that outputs data stored in the memory cell according to an output of the set of signal lines. Detecting means for outputting a read detection signal indicating that data has been read from the memory cell based on the output of the pair of signal lines; and inactivating the sense amplifier unit from an activated state based on the read detection signal. A sense amplifier comprising: activation control means for switching to an activated state; and data latch means for holding an output of the sense amplifier section based on the read detection signal. 2. The sense amplifier according to claim 1, wherein said detection means includes voltage setting means for setting an output from said signal line to a full swing level.