JPH1125604A - Magnetic disk device and semiconductor device using the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To regulate continuity of 0 or 1 in recording codes by performing set partition in an n-bit unit into output groups of 1st and 2nd signal converting circuits. SOLUTION: Since output signal groups of two RS inspection code arithmetic circuits 3-2 and 3-4 are not restricted in continuous numbers, these output signals are not digitally recordable, and are inputted to an 8-9 converter circuit 3-5. In this circuit, an output of 9 bits is given to an input of 8 bits, and an output bit string is not continued to be >=4 pieces of 0 or 1 by this conversion. When this output signal group is encoded for set partition, the continuous number of pieces of o or 1 is <=9 pieces as same as information data. Furthermore, an output D of the 8-9 converter circuit 3-5 and an output B of a 16-17 converter circuit 3-1 are synthesized by a synthesizer circuit 3-6, and its output signal E is processed in 3-bit unit by a recording encoder circuit 3-7, and then the conversion takes place in reference to a recording code just prior to every 3 bits. This output signal is of a magnetic recording enable signal group, and is amplified by a recording amplifier circuit 4 to be recorded by a recording head.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic disk drive using a signal processing circuit for recording digital data at a high density and a semiconductor device used for the same.

[0002]

2. Description of the Related Art Recently, the center of mass storage devices is RA.
Moving to ID (Redundant Arrays of Inexpensive Disk) systems, the performance of high-end small magnetic disks has been directly affecting system performance. Therefore, there is a strong demand for high-density and high-speed small magnetic disks of 3.5 inches or less. In addition, a GUI (Graphical User
Large-scale software that takes human interfaces into consideration is inevitable, and large-capacity small magnetic disks are desired. For that purpose, high-density recording is required, and high-density recording of several Gbit / in ² is targeted.

[0003] One of the signal processing techniques supporting high-density recording is a reproduction signal processing technique. Because of the high-density recording (accurately, the interval between recording bits has been narrowed), the interference between signals for each bit has increased.In the conventional peak detection method, the signal required to reproduce and identify the original recording signal The specification value of the noise-to-noise ratio becomes high, and a heavy load is imposed on the magnetic disk. For this reason, PR4ML (Partial Response class 4) that employs partial response equalization that takes into account intersymbol interference and employs maximum likelihood decoding that can detect the most likely signal sequence from the reproduced signal to remove the effects of noise. with Maxi
mum Likelihood decoding) method was considered. Signal processing LSIs using it have been developed and are being implemented in products.

When using a recording / reproducing system on the premise of greater intersymbol interference, it is necessary to change the partial response equalization method from PR4 to EPR4 (Extended PR4). ML (Maximum Likelihood decodin
g), that is, the maximum likelihood decoding circuit is changed from 2 states to 8 states. This number of states may be considered as the number of candidates for finding the most probable signal, indicating that EPR4 is more robust at dealing with noise. An application example of the EPR4ML circuit to a magnetic disk is disclosed in Patent Publication No. 1995-2499
98.

In high-density recording with a high track density, the signal-to-noise ratio of the recording / reproducing system is reduced, so that a code error is likely to occur due to noise. It is said that a trellis code in which a recording code is devised is effective against this problem. In other words, since the ML circuit is digital processing, it is considered that LSI implementation is relatively easy, and by assuming the use of complicated ML processing, by giving the recording code itself characteristics suitable for ML processing, low signal It tries to deal with the noise-to-noise ratio.
This study was initiated by a communication theory researcher in the mid-1980s. After that, in order to make it a practical recording and coding technology, compatibility with the reproduction equalization method and limiting the number of consecutive identical codes were considered. Investigations were undertaken, such as measures for error propagation and removal of DC components. For example, Japanese Patent Application Laid-Open No.
A construction method and a decoding method of a trellis code called an MSN (Matched Spectral Null) code characterized by free are disclosed. Among them, the code rate is 1/2, bi-phase
It is shown that the MSN code is applicable to EPR4 equalization.

[0006] In 1995, similarly, a magazine related to magnetism (IEEE transactions on magn) of the Institute of Electrical and Electronics Engineers.
etics) Volume 31, Issue 2, pages 1208-1213 contain PR4
On the premise of equalization, there have been reports on LSI prototypes of MSN codes with a code rate of 8/10.

As another signal processing technique for supporting high-density recording, there is an error correction code. The conventional role of the error correction code in the magnetic disk is to mainly deal with the one caused by the deterioration of the medium characteristics depending on the recording location of the recording medium (disk). In many cases, the characteristic degradation has a length of several tens of bits or more in terms of the number of bits, which causes a temporary decrease in the reproduction output, and a code error that extends over several tens of bits, a so-called burst error. I do. Therefore, in a serial signal sequence to be recorded, an interleaved error correction code is configured for each of a plurality of bytes (1 byte is usually composed of 8 bits). This interleave configuration allows successive burst errors to be corrected by different error correction code configurations.
For example, interleaving every three bytes (3way In)
When an error correction code configuration (ECCj) j = 1, 2, 3 is assumed to have 8 bytes for one byte and a burst error of 17 bits or less once, for example, 1 bit for ECC1 8 in ECC2
If the ECC3 is responsible for 8 bits and each error correction code configuration can cope with a 1-byte error, 1
Burst errors of 7 bits or less can be completely handled. Further, assuming that the number of bits of a code error becomes longer, it is necessary to increase the number of error correction check codes so that each error correction code configuration can cope with a longer number of bytes. At present, a Reed-Solomon code capable of performing byte-based error correction is often used as an error correction code.

The outline of the so-called equalization technique, the detection (or sometimes called identification) processing technique relating to a reproduced signal related to Viterbi detection, and the error correction code technique for coping with a code error remaining in the detection result have been described. .
Currently, these technologies are often discussed separately,
Few technologies are mentioned. The reason is that the former technique is a technique for dealing with a bit error due to noise superimposed mainly in a recording / reproducing system, and the latter is, as described above,
This is probably because it is recognized as a technique for dealing with burst errors.

However, if high-density recording advances, it is difficult to separate the two causes, and a slight deterioration in the characteristics of the recording medium will cause burst-like code errors due to random noise superimposed. Accordingly, in high-density recording, the efficiency of the error correction code, that is, the number of check codes is made as small as possible so that as many code errors as possible can be dealt with.
It is necessary to consider the recording code, the reproduction equalization, and the error correction code configuration in an integrated manner.

One proposal that embodies this integrated concept is a technique related to a recording code called a set partition code on the premise of EPR4 equalization described in Japanese Patent Application No. Hei 8-58754. This code is to allocate a 3-bit recording code to the 3-bit information data while also considering the immediately preceding recording code. The allocated (set partition) recording code is recorded on a recording medium, reproduced, and after performing EPR equalization on the reproduced signal, Viterbi detection is performed. After that, the set partition is inversely converted to return to the original information bits. At this time, even if noise is superimposed on the reproduced signal and a code error occurs at an arbitrary position in the detection signal sequence, when the detection signal is returned to the original 3-bit information data, the leading bit of each 3-bit information data is First assigned to be wrong. Of course, when a larger noise occurs, a code error occurs in the order of the second and third bits of the information data. When adopting such set partition encoding,
Only the first information bit (that is, the first bit of each 3-bit data) is regarded as one information bit group, and an error correction code is first formed for the information bit group. In addition, the second,
An error correction code is also formed in the third information bit group, but the redundancy thereof is set to be sequentially smaller. That is, there is disclosed a technique capable of efficiently coping with a code error as compared with a case where an error correction code is configured on average for all information bits.

[0011]

A code based on a bi-phase code which is an example of a conventional trellis code conforming to EPR4 equalization has a low code rate and is not suitable for high density. Also, the 8/10 trellis code having a higher code rate than the bi-phase code is not a method suitable for EPR4 equalization. Furthermore, a set partition code based on EPR4 equalization has a high code rate, is suitable for EPR equalization, and is excellent in fusibility with an error correction code. However, if the information bits to be recorded are simply recorded by set partition recording encoding, while the information bits are continuous, the set-partitioned recording code is also continuous with 0s. There are no restrictions. At this time, reproduction timing information at the time of reproduction cannot be obtained, and subsequent reproduction processing becomes unstable. Therefore, a first object of the present invention is to provide a recording code configuration that restricts the continuation of 0 or 1 in a recording code while using set partition recording encoding. Further, the error correction of the conventional set partition code is configured by changing the redundancy in three stages, and the circuit configuration is complicated. Therefore, a second object of the present invention is to provide a simple error correction code configuration capable of efficiently coping with a code error generated in high density recording, and on the basis of which, 3.5 "or less, which prioritizes high density recording. And a signal processing method suitable for a small magnetic disk.

[0012]

In order to solve the problems of the present invention, at least input data of digital information is converted into another digital data string, and the number of consecutive zeros in the converted digital string is regulated. 1 digital signal conversion circuit, a first error correction encoding circuit for all bits in the digital sequence after the conversion,
In the output signal sequence of the error correction coding circuit
3 bits or more) Each bit is one sub-block,
A second part of the error correction code for the signal block of interest from the head bit of the sub-block to the m-th bit (where m is a positive integer satisfying m <n).
Error correction coding circuit, a second digital signal conversion circuit for converting a check code sequence of the two error correction codes into a recording code suitable for digital recording, a first digital signal conversion circuit and a second digital signal conversion circuit. A set partition recording encoding circuit that converts the output sequence of the digital signal conversion circuit into a set partition recording code in units of n bits is used.

The reproducing circuit corresponding to the recording circuit includes at least an equalizing circuit for compensating a frequency characteristic of a head disk recording system so as to have a frequency characteristic necessary for detecting a digital signal, and a Viterbi detection or the like. A maximum likelihood detection circuit, a circuit for outputting an equalized output expected value corresponding to an output signal of the detection circuit, a set partition decoding circuit, and first and second digital signal conversion circuits corresponding to the first and second digital signal conversion circuits. A second inversion circuit, the first and second
The first and second error correction operation circuits corresponding to the error correction coding circuit of FIG.

(Examples) The present invention will be described in detail with reference to examples. FIG. 1 is a signal processing system diagram of a recording system according to the present invention. Data to be recorded is input from the computer 1 to the recording processing circuit 3 via the interface circuit 2. An output signal of the recording processing circuit 3 is recorded on a magnetic disk 5 by a magnetic head via a recording amplification circuit 4. The feature technology of the present invention is included in the recording processing circuit 3. FIG. 2 shows a signal form of each part in the recording processing circuit 3. The output signal (A) of the interface circuit 2 shows the signal form of one sector consisting of 512 words, with eight bits of information data as one data word. However, for the sake of simplicity, various identification signal data attached before the beginning of the sector data and signals attached after the end of the data are omitted. A unit called a sector is the minimum unit of data handling between the magnetic disk device and the interface or the computer. The signal (A) is converted by the 16-17 conversion circuit 3-1 into 17-bit data in units of two data words (16 bits).

When the output signal of the recording processing circuit 3 is represented by binary values of 1 and 0, recording is performed so that 1 corresponds to a certain magnetization state + M on the magnetic disk and 0 corresponds to -M.
In this case, if a long continuous signal of 1 or 0 is recorded, the reproduction timing clock signal corresponding to each bit cannot be extracted from the reproduction signal. Therefore, the number of consecutive 1s and 0s must be less than a certain limit number. Since the signal (A) from the computer is a signal without such restriction, the above restriction is given by converting 16 bits of data into 17 bits. Data string (B) is 16-17
This is an output signal of the conversion circuit 3-1. Various conversion rules have been proposed. According to a certain conversion rule, the number of consecutive 1s and 0s can be limited to 4 or less. When set partition recording encoding is performed on this digital signal sequence, the number of consecutive 1s or 0s becomes long. However, as described below, the maximum number of consecutives can be limited to 9 and magnetic recording becomes possible.

The total number of bits in the data string (B) is (8 × 512) / 16 × 17 = 4352. Since 8 × 512 = 4096 in the signal (A),
Compared to this, there are more. However, in FIG. 2, assuming that the transfer speed is increased by 17/16, (A) and (B)
The length of the signal is shown the same.

The RS check code calculation circuit 3-2 calculates a check code using a Reed-Solomon error correction code (hereinafter abbreviated as RS code) using the signal (B) as an information code. However, although the signal (B) is data in units of 17 bits, it is neglected, divided into 8-bit units from the beginning of the signal sequence, treated as an 8-bit information code, and a check code based on an RS code is calculated. That is, the Galois field GF (2
⁸ ), the RS code (Rsj) j = 1, 2, 3 is constructed. At this time, the maximum number of RS codes having 8 bits as one unit is 2 ⁸ -1, that is, up to 255. For this reason, as shown in the signal (C), an interleaving operation is performed for every three information codes, and the RS check code of 4 bytes (1 byte is 8 bits) is synthesized by the combining circuit 3-3 in one interleaved sequence. insert. The same processing is performed for another interleave sequence. For this reason,
The RS check code operation circuit 3-2 includes three RS code operation circuits (not shown). As a result, the synthesis circuit 3-3
In the output signal (C), a sequence of RS1, a sequence of RS2, and a sequence of RS3 are separately inserted as RS check codes. The figure simply shows 2 bytes. Since the total number of bits 4352 of the data string (B) is interleaved by 3 in 8-bit units, an RS check code of 4 bytes is formed for every 4352/8/3 = 181 bytes. As a result, the total number of bits of data (C) is 4352 + 3 × 8 × 4 = 44
48.

The method of constructing the RS check code described above is not new, but has been disclosed conventionally. The present invention further provides an error correction code configuration suitable for a set partition recording code suitable for EPR4 and a method for recording the error correction code itself, in addition to the conventional configuration.

First, as shown in FIG. 3, it is assumed that the output signal (C) is composed of sub-blocks every three bits, where n = 3. Then, assuming that m = 2, only the first bit and the second bit (color-coded in FIG. 3) of each sub-block are extracted, and the eight bits are treated as one information word sequence S-E1, and the sub-block is processed. Of the RS code for use. Further, in order to perform three-system interleave processing, the next 8 bits are handled as an S-E2 sequence, and the next 8 bits are handled as an S-E3 sequence. That is,
(RSsj) j = 1, as the sub-block RS code
2 and 3 are configured. Since the total number of bits of the data (C) is given by 4448 as described above, if this is divided into sub-blocks, 4448/3 = 1483, the leading bit and the second bit are collected by 8 bits, and 3 interleaved (1483 × 2) / 8/3 = 124.
In the embodiment, a 7-byte RS check code is configured for 124 bytes.

Two RS check code operation circuits 3-2 and 3
Since the number of consecutive codes is not limited, the digital signal cannot be recorded as it is. Therefore, these output signals are input to the 8-9 conversion circuit 3-5. The 8-9 conversion circuit provides 9 bits of output for 8 bits of input. Due to this conversion, four or more 0s or 1s do not continue at any place in the output bit string. When this output signal sequence is set-partition-encoded, the number of consecutive 0s or 1s is 9 or less as in the case of the information data, as described below.

Now, the number of output bits of the circuit 3-2 is 3x8x.
4 = 96 becomes 96/8 × 9 = 108 bits after the 8-9 conversion, and the number of output bits of the circuit 3-4 is 3 × 8 × 7.
= 168 means 168/8 × 9 = 189 bits. These check bits are input to the synthesis circuit 3-6, and 16-1
The output (E) is synthesized with the output of the 7 conversion circuit (B).

Of the signal (E), the signal indicated by D is the output signal of the circuit 3-5, that is, the two R signals after the 8-9 conversion.
S check code (RSj) t j = 1,2,3 and (RSs
j) tj = 1, 2, 3; t indicates that the conversion was 8-9.

The total number of bits of the signal (E) is 4352 + 10
8 + 189 = 4649. The set partition (hereinafter abbreviated as SP) recording encoding circuit 3-7 performs processing on the input signal (E) in units of 3 bits, and refers to 3 bits as a new recording code to the immediately preceding recording code. While converting. One example of the conversion table is as described in the already-filed application (application number Heisei 8-58754). It is transcribed and shown in FIG. The input signal of the SP recording / encoding circuit 3-7 has two systems, one is a data sequence subjected to 16-17 conversion, and the other is a check code sequence subjected to 8-9 conversion. In both cases, the number of consecutive codes is limited to four. However, as shown in FIG. 5, the worst recording code sequence when SP recording encoding is performed has a long continuous number of nine. In FIG. 5, the input data yyy is changed from the state Sk.
If the state is changed to the state S0, the state of the state S0 means that the recording code is 000 from FIG. The worst case is when the input data becomes further 000 in the state S0, the recording code is 000, and again the state is S.
It becomes 0. Since the input data is limited to 0, the input data does not become 000 again. The input data for lengthening the 0 continuation of the recording code is 100. In the first state Sk, the reason why k = 4 is not considered is that the input data is 000 when the next state is set to S0 at k = 4. This is because 000 is prohibited due to the restriction of 0 continuation, and 0 continuation in the recording code is interrupted. FIG. 5 shows the EPR equalized output in the worst recording code sequence. As can be seen from the figure, since the EPR has an equalization characteristic that allows intersymbol interference, the continuation of 0 output in the equalized output is 6, and the lack of reproduction timing information does not pose a serious problem in practical use. From the above, the output signal of the circuit 3-7 is a signal sequence that can be magnetically recorded, is amplified by the recording amplifier circuit 4, and is recorded as a magnetization pattern on the magnetic disk via the magnetic recording head.

The method of recording one 512-byte sector signal and its accompanying error correction check code has been described above.

Next, the reproduction process will be described with reference to FIG.
In order to make it easy to understand which signal form of each part corresponds to which point on the recording side, a dash is added to the signal on the recording side in FIG.
This indicates that the corresponding signal is on the reproduction side. Also,
A novel part of the present invention is a set partition decoding circuit 8 surrounded by a dotted line.

The signal recorded on the magnetic disk is read out by the magnetic head, amplified by the reproducing amplifier 6 and converted into a signal having a predetermined amplitude, and is called an extended partial response equalization (hereinafter referred to as EPR). The compensator 7-1 compensates for the deterioration of the frequency characteristics in the recording / reproducing system 5 using the magnetic disk and the magnetic head. Note that EPR is D (1−D) where D is a bit delay operator.
(1 + D) is an equalization method indicated by ² . Equalizer 7-1
The output is a signal sequence G in which noise is superimposed on the expected output value of EPR equalization. From the signal sequence G, the most likely recorded encoded sequence (F ') is calculated by the Viterbi detector 7-2. E
The combination of PR equalization and Viterbi detection is called EPRML (circuit 7). The output signal (F ') of EPRML is shown in FIG.
Is a reproduced signal corresponding to the signal (F) in FIG. This signal is input to the set partition decoding circuit 8.
In the decoding circuit 8, first, the first set partition decoding, that is, provisional decoding is performed by the set partition decoding circuit 8
According to -1, a process corresponding to the inverse transform of the set partition encoding is performed. The error check code portion of the output signal (E ') of the decoding circuit 8-1 is added to the 8 bits on the recording side.
The inverse conversion of the -9 conversion is performed by the 9-8 conversion circuit 8-2. As a result, RSs1'RSs2 'and RSs3' for the first bit and the second bit in the sub-block
Since a check code is obtained, error correction of the first bit and the second bit of the sub-block is performed by this. First,
The syndrome value in the error correction code relating to the first bit and the second bit in the sub-block is calculated by the syndrome calculation circuit 8-3. Since one interleave sequence constitutes 7 bytes of check bytes,
Seven syndrome values are calculated, and up to three (one is one)
Bytes) can be corrected. That is, the positions and the magnitudes of the three errors can be obtained at the maximum. It should be noted that there is almost no probability that more than three errors occur and that the seven syndromes cannot be detected. But,
Since it is important to consider the oversight in terms of securing the reliability of the magnetic disk device, as described below, error correction using an error correction code of (RSj) j = 1, 2, 3 Detection is used.

The error correction circuit 8-4 can identify an erroneous location and correct the error of the first bit and the second bit at that location. That is, with respect to the state S ′ for each three bits of the recording code in FIG.
It can be determined that the inter-symbol distance in the PR output is one of the largest combinations such as S0 and S1, S2 and S3, and the like. Therefore, if the Viterbi detection is performed again in an erroneous place and again with reference to the G signal which is the output signal of the EPR4 equalization circuit and in consideration of the definite condition, a correct third bit is obtained. In the embodiment of the present invention, G
Instead of directly reusing the signal, the Viterbi detection circuit 7
-2 output signal from the EPR expected output sequence (signal E in FIG. 5)
Q. ) EQ ′ was created by the EPR expected value output circuit 8-5, and was used instead of the G signal. Using the result of the first Viterbi detection, a Viterbi detection circuit 8-6 obtains a signal sequence that meets the above-described determination condition. Since it is not a signal sequence including noise like the signal G, the number of operation bits may be small. Due to the fixed condition, the corrected first bit b
0 and the decoded output E ″ (b0, b1) of the second bit b1 are output from the correction circuit 8-4. As a result, the Viterbi detection circuit 8-6 outputs the signal sequence (F ″) with the improved error rate. Output. The output signal is again subjected to set partition decoding by the decoding circuits 8-7 to obtain a signal sequence (E ").

The portion corresponding to the RS check code in the signal sequence (E ″) is converted by the 9-8 conversion circuit 9 into the original RS1,
Return to RS2 and RS3 check codes. As a result, a signal sequence (C ′) on the reproduction side corresponding to the signal sequence (C) is obtained. Irrespective of the first-stage error correction processing of the present invention based on Viterbi detection again using set partition encoding and error correction processing, a missed error or a burst error that cannot be corrected by the first-stage error correction The error correction circuit 10 performs the second-stage error correction process using the RS1, RS2, and RS3 check codes in each interleave sequence. Since the number of check codes is 4 bytes, it is checked (detected) whether there is an error of 2 bytes or more, and 1-byte error correction is possible. The corrected data (B ') returns to the original input data (A') by a 17/16 conversion circuit which is an inverse conversion of the 16/17 conversion, and is output to the computer via the interface circuit 12. In the correction circuit 10,
If an error of 2 bytes or more is detected, rereading must be reported to the computer side, so the correction circuit 10 outputs a rereading control signal RT.

The circuit configuration related to set partition encoding and decoding has been mainly described above. Further, encoding and decoding will be described in more detail by using a specific example of a recording code, and improvement in characteristics of the present invention will be described. First, the process of encoding and decoding the set partition when there is no noise in the reproduction process will be described with reference to FIG. For example, 16-17
The converted data is 00000,001, as shown in FIG.
000,001,111. The initial state required for performing the set partition encoding is S0. When the initial state is S0 and the input data 3 bits are 000, the recording code cc assigned from FIG.
Becomes 000, and the state S0 remains unchanged. Since the next three input bits are 001, cc = 110, and the state S '= S6. In the same manner, a recording code cc by SP encoding is obtained, and a recording encoded sequence F is formed. Assuming that the recording coded sequence F is digitally recorded and there is no noise in the disk head system, the EPR
Output sequence after equalization (G signal in FIG. 6)
Can obtain the expected output in FIG. 4 as it is. Although noise is superimposed on the output G of the actual device, a signal sequence F 'corresponding to the most probable recording code is calculated by Viterbi detection. In the example of FIG. 7, since there is no noise, the original recording code sequence is obtained, and the original data B can be obtained by performing set partition decoding.

Although the present invention utilizes set partition encoding, the encoding is based on EPRML.
The noise suppression effect of EPRML can be used as it is.
According to FIG. 8, E in the set partition recording code
The effect of PRML will be described. It is assumed that an equalized output different from the original value is provided as the EPR equalized output G ′ on which noise is superimposed as shown in FIG. Since it is different from the original value 0 by two, the square of the distance (hereinafter referred to as (distance) ² ) as (0−2) ² is called an equalized output sequence separated by four. S0 to S6 in FIG. 8 show eight states of the EPR Viterbi detector. In Viterbi detection, the most probable state path is determined after a certain period of time by selecting the path with the highest probability from the two transitions (paths) in each state. In FIG. 8, three paths (a) and (b) near the noise superimposed and near the equalized output sequence
(C), the noise disappears, and thereafter, the convergence occurs. At this time, since two transition paths, that is, the series (a) and (b) first intersect in the state S6, their probabilities are compared. In each path, the case where the expected EPR output value with respect to the signal output differs from the actual EPR equalized output is indicated by a dotted line. It differs once in the path of the sequence (b), but three times in the path of the sequence (a). Therefore, at this point, the sequence (b) is selected. Furthermore, since the sequence (c) intersects with the state S4 at the next time, the likelihood is compared again. Also at this time, the path of the sequence (b) which is considered more likely is selected. In this way, it can be seen that the original sequence is correctly detected by performing Viterbi detection on the equalized output sequence G ′ whose (distance) ² is 4 away from the original sequence due to noise. In EPRML, since the (minimum distance) ² of two equalized output sequences is 16, even if the equalized output is incorrect due to noise from the original equalized output, the (distance) ² is half of (minimum distance) ² , that is, If it is smaller than 8, by detecting Viterbi as described above,
All are correctly detected as original signal sequences. Of course, if the superimposed noise is large and the (distance) ² is incorrectly output as an equalized output separated by 8 or more, the EPRML may not correctly detect the output.

Therefore, noise that may be erroneous in EPRML is dealt with by configuring an error correction code. The conventional concept of error correction will be described first. In a signal sequence, for example, in the embodiment of the present invention, 181 bytes = 181 × 8 bits in one interleave sequence. In the EPR equalized output, if an output sequence whose (distance) ² is 8 or more away from the original value occurs due to a certain large noise, as described above, it is mistaken for another output sequence. Error occurs. In a magnetic disk drive, not only is a 1-bit error or at most a few-bit error generated due to superimposition of random noise such as amplifier noise, but also signal deterioration due to the influence of medium characteristics slightly fluctuating depending on a place. Accompany 1
Since it is important to assume a burst error of up to 3 bytes (8 bits to 24 bits), a Reed-Solomon code capable of correcting bytes is usually used as the error correction code. Therefore, it is naturally necessary to construct an error correction code capable of correcting one byte even for one bit error. Further, assuming that another 1 bit is erroneous due to another noise, it is necessary to configure an error correction code capable of 2-byte correction. This is the conventional idea. In other words, it is suggested that the conventional configuration does not always provide efficient error correction for bit errors. Conventionally, the order of recording coding such as error correction coding and 16-17 conversion is to perform error correction coding before performing 16-17 conversion. On the other hand, the present invention, after 16-17 conversion,
It constitutes an error correction code. The conventional method is characterized in that recording and encoding can be performed only once. However, in the conventional method, the digital signal sequence is converted to 17
When 17-16 conversion is performed by dividing each bit, the error remains in the signal sequence before conversion without being corrected, and a few bits of errors remain including the 17-bit separation. Often occurs. In this case, an error occurs in both of the two 16-bits separating the boundary, and the error is enlarged. That is, a one-byte error becomes a two-byte error. Furthermore, when the conversion table is configured so that the entire 17 bits of one section are directly converted into two 8 bits, a one-byte error is expanded to a four-byte error. This means that even if a check code of an RS code of as many as 11 bytes is formed in one interleave sequence in the conventional method,
This means that the number of bytes of the check code that is substantially effective is half or 1/4 of that, so care must be taken when using a high code rate recording code such as 16-17 conversion. On the other hand, on the reproducing side of the present invention, since the 17-16 conversion is performed after the error correction operation is completed, the error does not expand. Therefore, when a recording code of a high code rate is used, or even when a recording code of a low code rate is adopted, a predetermined bit error rate ( ^10-6 to ^10-8 ) can be obtained only by Viterbi detection because of high-density recording. If it cannot be ensured, it is better to perform error correction coding after recording coding as in the present invention.

Next, a description will be given of a fusion technique of set partition recording encoding and error correction encoding used in the present invention. In the EPR-compliant set partition encoding, the 181 × 8 bit string is divided into 3 bits, and converted into another 3 bits according to the conversion table shown in FIG. 4 and recorded. In the embodiment, since an error correction code for all bits is configured together with the set partition coding,
Since set partition encoding is performed including that, the number of target bits is more than 181 bytes. The recorded set partition coded signal sequence is output after EPR equalization, noise is superimposed on the signal sequence, and (distance) ² is 8 from the original value.
When a distant output sequence occurs, an error occurs due to Viterbi detection as in the related art. However, when the set partition is decoded based on the detection signal sequence, the probability that an error occurs in the first bit or the second bit in every three bits of the decoded sequence is extremely high. This is because, when the output sequence after the equalization in the conversion table of the set partition coding in FIG. 4 is seen due to the difference of the leading bits of the three bits of the input data, (distance) ² is the minimum combination of four.
For example, when the state of the immediately preceding recording code CC is S0, the equalized output is 000 and 002 for the input data 000 and 100, and the equalized output is 24 for the 001 and 101 as well.
0 and 242. This means that if noise is superimposed on the equalized output and Viterbi detection is erroneous, an equalized output with a short distance, that is, a short distance, will be erroneously output. Conversely, if the third bit is erroneously As can be seen from FIG. 5, since 000 in the equalization output means that incorrect 240, the third when speaking in code distance (distance) ² 20 not leave Bits do not stop. Therefore, in most cases, the third bit error does not occur. This will be explained by rough estimation. Assuming that a predetermined output is 0 or 2 and noise having a normal distribution is superimposed on the predetermined output, and the signal output (peak to peak) to noise (square root of the root mean square) is 10: 1, the probability that the output 0 is erroneous to 2 Is about ^10-6 . On the other hand, 0 is the probability is 10 ^{over 40} below err of 4, it can be seen that may be largely ignored. For example, the signal output 10: Even if a 1.5, the probability that output 0 is erroneous in a 2 whereas in the range of about 10 ^-3, the probability of mistaking 0 of 4 are still 10 ^-25 or less, most It doesn't matter. Therefore, most bit errors can be dealt with simply by configuring the error correction code only for the first bit and the second bit. In the set partition coding, three output bits are assigned to three input bits, so that there is no deterioration in redundancy. Therefore, of the three bits, 2
When an error correction code is composed only of bits, almost the same correction capability as that of the conventional configuration can be obtained due to the redundancy of 2/3 as compared with the conventional configuration. As shown in FIG. 4, the set partition encoding is performed by using the immediately preceding recording code cc.
Is different depending on the conversion table. Therefore, when the first bit and the second bit after decoding are changed by the correction processing, the state of the corresponding three bits is converted, and Viterbi detection is performed again based on the newly determined state, and the third bit is changed. Must be detected.

Hereinafter, a specific example of the decoding process in the set partition encoding will be described to show its effectiveness. FIG.
7 shows an example in which, in the EPR4 output sequence G, an equalized output whose (distance) ² is 8 or more away from the original equalized output G in FIG. 7 and is detected as another output sequence, (Distance) ² is 16 away. However, the output value G ′
Is displayed ignoring the value after the decimal point due to noise,
This is the same value as the output EQ ′ of the EPR expected value output circuit 8-5. The output of the Viterbi detection circuit 7-2, that is, the first Viterbi detection result F 'is calculated from the equalized output G' series.
Incorrect locations compared with the correct results in FIG. 7 are indicated by *. At the same time, the status of the set partition associated therewith is shown. When the inverse set partition is decoded from the result of F ′, the provisional decoding result E ′ is obtained.
Is obtained. Also in this case, an error part is marked with * in comparison with the correct result in FIG. As can be seen from FIG. 9, E ′
The error in the sequence is only the first bit of the sub-block as described above. This is because, in the equalized output G ′, the equalized output corresponding to each sub-block is only 4 (distance) ² away from the correct value, so that the error in the first bit that is most error-prone after decoding is obtained. Since an error correction code is configured for the first bit and the second bit,
The error of the temporary decoding result E 'is corrected, and the correction result E "in which the first bit and the second bit of the sub-block are determined.
(B0, b1) is obtained. In the second simple Viterbi detection circuit 8-6, the EPR expected value output EQ ′, that is, the EPR4 output G ′ and the correction result E ″ (b0, b
If 1) is used, the final detection result E ″ is obtained for each sub-block. Specifically, in FIG. 9, in the case of the second sub-block, the equalization output 240 is given in the state S0, The correction results b0 = 1 and b1 = 0.State S0
Since b0 = 1 and b1 = 0, the expected value of the equalized output is 002 or 242 with reference to the conversion table of FIG. Looking for certainty, the expected value close to 240 is 24
2, the detection result F ″ is 111, and the state S7
Changes to The detection results can be sequentially obtained in sub-block units. As a result, a correct detection result F "is given, and a correct decoding result E" is obtained.

FIG. 10 shows an example where noise is concentrated in the EPR4 equalized output. That is, in the equalized output 220, an error occurs in which the (distance) ² is 4 in each of the second bit and the third bit from the original value 242. At this time, as can be seen from the provisional decoding result E ', not only the first bit of the sub-block but also the second bit is incorrect. However, as in the case of FIG. 9, by performing error correction on the sub-block, a correct detection result F ″ is given, and a correct decoding result E ″ is obtained. In the above, the effectiveness of the present invention has been described with reference to specific examples of the reproduction signal in the embodiment of the present invention.

Next, the effectiveness of the present invention will be described with reference to FIG. A of FIG.
P is a repetition of FIG. 3 and shows an error correction code configuration for a sub-block according to the present invention. Since the use of EPR4-compatible set partition recording coding is assumed, an 8-bit interleave format in which four 3-bit sub-blocks are collected and the first bit and the second bit of each sub-block are information bits in 12-bit interleaved format Constitutes one byte. On the other hand, the conventional error-correcting code configuration AC forms one byte with continuous eight bits, and has an interleaving configuration of every eight bits. Both are three systems of interleaving. Now, it is assumed that a 5-bit error has occurred due to deterioration of the medium characteristics as indicated by DEF in the figure. An error may be applied to each of the two error correcting sequences interleaved depending on the position of the deterioration. In the configuration of the present invention, two errors occur at a probability of 1/3, whereas in the related art, two errors are handled at a probability of 1/2.
Therefore, even if the number of check codes of error codes is the same,
The effect is 1.5 times different. Similarly, for long burst errors, the length before being considered an error of the same interleave system is also 1.5 times more advantageous.

Although the EPR4 expected value output circuit 8-5 is used as the input signal of the Viterbi detection circuit 8-6 in the embodiment, the present invention can be applied to the case where the EPR4 equalized output G is used again via the delay circuit. Needless to say, this can be implemented. Also,
Although the present embodiment has been described based on EPR4 equalization, the concept of the present invention can be applied to other partial response systems. For example, for a recording pulse 1, 110
The present invention can be configured based on set partition encoding suitable for a partial response corresponding to a -1-1 response. FIG. 12 shows the PR (1, 1,
2 shows a part of a set partition encoding table corresponding to (0, -1, -1). The configuration of the table is the same as that of FIG. 4, and the recording code CC in the initial state S0 is described. Recording codes for other states can also be configured based on the same concept as in FIG. To reduce complexity, only the initial state S0 is described.

FIG. 6 shows a preferred LSI configuration for implementing the present invention.
As shown in the figure, the operation circuit of the Reed-Solomon code is configured in the same LSI together with the EPR4 equalization circuit 7-1 and the Viterbi detection circuit 7-2. However, conventionally, EP
In many cases, the RML circuit and the error correction code have different LSI configurations. Therefore, it is necessary to consider the following case. At this time, the error correction code LSI is shown in FIG.
Circuits 8, 9, 10, and 11 will be included. Especially,
The provision of the EPR4 expected value output circuit 8-5 in order to perform Viterbi detection again in this error correction code LSI has the following advantages as described above.
(1) The number of delay circuits can be reduced as compared with a case where the EPR4 equalized output G is reused by using a delay circuit. (2)
To send or calculate a signal containing noise such as a G signal, the number of bits is large. On the other hand, it is better to calculate the expected output value without noise based on the first Viterbi detection result. This is an arithmetic operation with a small number. It should be noted that the EPR4 expected value output circuit 8-5 is connected to the EPRM
Needless to say, it can be included in the LSI on the L side.

The present invention can be understood from the above description.
Since the error correction code is used twice, it is assumed that the redundancy of the error correction code is large. Therefore, for example, the reliability of the recording / reproducing characteristics of the head disk system is high,
It is assumed that the assumed bit error rate is as low as about ^10-8 or ^10-9, and the redundancy of the error correction code is about 3.5%, specifically, 6 bytes to 171 bytes in the conventional error correction code configuration. It is meaningless to design a new magnetic disk drive to which the present invention is applied when a degree of error correction check code is used. Rather, redundancy is less than 5%, for example, as attempts to use error correction check code 11 bytes to 171 bytes in the conventional configuration, when assuming a bit error rate of 10 ^-4 or 10 ^-6 as low is assumed The application of the present invention is suitable for a magnetic disk drive. Therefore, the present invention is effective for a small-sized magnetic disk device of 3.5 "or less, in which high-density recording is particularly required in the future.

[0039]

Since the present invention is equivalent to increasing the error correction capability by about 1.5 times as compared with the conventional configuration, if the present invention is applied to a small magnetic disk drive, the required signal to noise of the head disk system is required. The ratio can be reduced by approximately 2 dB. Alternatively, with the same signal-to-noise ratio specification, an effect equivalent to a 1.6-fold increase in areal density can be expected.

Alternatively, since the error correction code is configured with 1.5 times less redundancy than the conventional configuration, the power consumption of the LSI related to the error correction code can be reduced.

[Brief description of the drawings]

FIG. 1 is a signal processing system diagram of a recording system according to an embodiment of the present invention.

FIG. 2 is a signal form diagram of each unit in FIG. 1;

FIG. 3 is a diagram showing a configuration of a sub-block and an error correction code configuration thereof in the embodiment.

FIG. 4 is a diagram showing a conversion table for set partition recording encoding applied to EPR4.

FIG. 5 is a diagram showing a worst recording encoded sequence of the set partition recording encoding of FIG. 4;

FIG. 6 is a reproduction signal system diagram of an embodiment relating to a reproduction system corresponding to FIG. 1;

FIG. 7 is an exemplary view for explaining a process of signal processing in the embodiment.

FIG. 8 is a diagram showing that EPRML is effective in the embodiment.

FIG. 9 is an exemplary view for explaining that a signal affected by noise is correctly decoded by the signal processing according to the embodiment;

FIG. 10 is an exemplary view for explaining that a signal affected by noise is correctly decoded by the signal processing according to the embodiment;

FIG. 11 is a view for explaining differences and effects of an error correction code configuration between the embodiment and the conventional example.

FIG. 12 is a diagram showing a part of a set partition encoding table corresponding to PR (1, 1, 0, −1, −1).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Computer, 2 ... Interface circuit, 3 ... Recording encoder, 4 ... Recording amplifier, 5 ... Recording / reproducing system, 6 ... Reproduction amplifier, 7 ... EPRML circuit, 8 ... Set partition decoding circuit, 10 ... Error correction Circuit, 11 ... 17-16 conversion circuit.

Claims (9)

[Claims] In a magnetic disk drive for magnetically recording and reproducing digital information, a first digital signal conversion circuit for converting input data of digital information into another digital data sequence as a recording signal processing circuit, A first error correction encoding circuit for all bits in the digital sequence, and in an output signal sequence of the first error correction encoding circuit, every n (n is 3 bits or more) bits is defined as one sub-block; A second error correction coding circuit forming an error correction code for a signal block of interest from the first bit to the m-th bit (where m is a positive integer satisfying m <n); A second digital signal conversion circuit for converting the check code sequence of the correction code into a recording code suitable for digital recording, and a first digital signal conversion circuit; To circuit and the output series of the second digital signal conversion circuit, a magnetic disk apparatus characterized by having a recording encoding circuit for performing a set partitioning in n-bit units. 2. The magnetic disk drive according to claim 1, wherein said first digital signal conversion circuit regulates the number of consecutive zeros in the converted digital sequence. 3. The magnetic disk drive according to claim 1, wherein said first digital signal conversion circuit converts 16 bits of input data into 17 bits. 4. The magnetic disk drive according to claim 1, wherein said first and second error correction coding circuits form an error correction code capable of correcting an error in byte units. 5. The magnetic disk drive according to claim 1, wherein a set partition recording / encoding circuit based on EPR equalization in units of 3 bits is used. 6. An equalizer circuit for compensating the frequency characteristics of a head disk recording system to have a frequency characteristic necessary for detecting a digital signal, a maximum likelihood detection circuit such as Viterbi detection, and two types of reproduction means. An equalized output expected value corresponding to an output signal of the detection circuit using two types of inverse conversion circuits corresponding to a digital signal conversion circuit and two types of error correction operation circuits corresponding to two types of error correction encoding circuits. 2. The magnetic disk drive according to claim 1, further comprising: a circuit for outputting a signal. 7. A first circuit for converting input data of digital information into another digital data sequence as a recording signal processing circuit.
, A first error correction coding circuit for all bits in the converted digital string, and n (n is 3 bits or more) in the output signal sequence of the first error correction coding circuit. Each bit is regarded as one sub-block, and from the first bit of the sub-block to the m-th bit (where m is a positive integer satisfying m <n)
A second error correction coding circuit that forms an error correction code for the signal block of interest, a second digital signal conversion circuit that converts a check code sequence of the two error correction codes into a recording code suitable for digital recording, A recording encoding circuit for performing a set partition on an output series of the first digital signal conversion circuit and the second digital signal conversion circuit in n-bit units. 8. An element device of a magnetic disk drive for magnetically recording and reproducing digital information, wherein a reproduction signal processing circuit compensates for frequency characteristics of a head disk recording system so as to have frequency characteristics necessary for detecting digital signals. A semiconductor device comprising: an equalization circuit; a maximum likelihood detection circuit such as Viterbi detection; and a circuit that outputs an expected equalized output value corresponding to an output signal of the detection circuit. 9. The semiconductor device according to claim 8, further comprising an error correction code operation circuit in one device.