JPH11252060A - Decision method and device for phase between logical data and synchronous clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily determine the propriety of relative phase relations between logical data and synchronous clock signals. SOLUTION: A decision circuit 3 can detect a deficient hold time by comparing the data level states of logical data (c) set at the rising time of a synchronous clock signal (a) and those of logical data (c) set at the rising time of a delay clock (b) respectively. Meanwhile, a decision circuit 3 can detect a deficient set-up time by comparing the data level states of both data (c) and delay data (d) set at the rise times of signals (a) respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a synchronous clock signal phase for each logical data when it is specified that each logical data is to be transmitted with a synchronous clock signal near the center of the data. The present invention relates to a method and a device for determining the phase between logical data and a synchronous clock, which are used to determine the quality of the data.

[0002]

2. Description of the Related Art Generally, when each logical data is transmitted periodically or aperiodically with a synchronous clock signal in the vicinity of the data center (so-called data eye), the pulse width of each logical data is transmitted. Is sufficiently larger than the required minimum pulse width (= setup time + hold time), that is, the pulse width is set in a state where a margin is secured, and the data is actually transmitted. Also,
As for the relative phase relationship of the synchronous clock signal to each of the logical data, the synchronous clock signal is usually set to be located near the center of the logical data. As a result, even if there is a slight variation in the relative phase relationship of the synchronous clock signal with respect to each of the logical data, the variation can be tolerated.

[0003]

However, if the relative phase relationship of the synchronous clock signal with respect to each of the logical data is unacceptably large due to some factor, the synchronous clock signal may cause an unacceptable change. The reliable punching of logical data can no longer be guaranteed at all. This is because, based on the time of the rising or falling edge of the synchronous clock signal, a sufficient setup time is not secured for the logic data before the time reference, or a sufficient hold time is provided after the time reference. This is because they are not secured.

An object of the present invention is to provide a logic data phase determination method and apparatus capable of easily determining whether the relative phase relationship of a synchronous clock signal with respect to each logical data is good or not.

[0005]

SUMMARY OF THE INVENTION The object of the present invention is to provide a synchronous clock signal having a data level state of logical data at a rising time or a falling time and a rising time of a synchronous clock signal of logical data delayed by a setup time, or If the data level state at the falling point is not the same as the data level state, or the rising point of the synchronous clock signal, or the rising edge of the synchronous clock signal delayed by the hold time from the data level state of the logical data at the falling point This is achieved by determining that the phase between the logical data and the synchronous clock is defective when the data level state of the logical data at the time point or the falling time point is not in the same data level state.

[0006] Further, as a device configuration, a first delay circuit for delaying logic data by a set-up time, a data level state of the logic data at a rising time or a falling time of a synchronous clock signal, and the like are included as components. The first
Of the logical data delayed by the setup time by the delay circuit of the synchronous clock signal at the rise time or the fall time of the synchronous clock signal. A first phase determination circuit that determines that the phase is defective, a second delay circuit that delays the synchronous clock signal by a time such as a hole,
The data level state of the logical data at the rising or falling point of the synchronous clock signal and the data of the logical data at the rising or falling point of the synchronous clock signal delayed by the hold time by the second delay circuit This is attained by including at least a second phase determination circuit that determines that the phase between the logical data and the synchronous clock is defective when the levels are not in the same data level state after comparison with the level state.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. First, prior to the specific description of the present invention, the setup time and the hold time will be slightly supplementarily described as follows.

That is, as shown in FIG. 2, in this example, it is assumed that logical data is punched out at the rising edge of the synchronous clock signal. However, in order to reliably punch out the logical data, Before the rising time, the logical data must exist as the data level state for at least the setup time Ts, and after the rising time, the logical data exists as the data level state for at least the hold time Th. That's what you have to do. In other words, the logic data shown in FIG. 2 has its pulse width set to a necessary minimum. However, when the logical data is set to have the necessary minimum pulse width, the relative phase relationship of the synchronous clock signal with respect to the logical data must be uniquely determined. It is clear that no variation can be tolerated as the inter-clock phase. Therefore, in general, each of the logic data is set so that the pulse width thereof is set to a state where a sufficient margin is secured, and the phase variation within the margin is allowed. However, even if the circuit and transmission are designed in advance in such a manner, the phase between the logical data and the synchronous clock often fluctuates greatly from the initial setting state due to a temporal factor or the like, and the logical data is changed by the synchronous clock signal. Although there is a possibility that a situation may occur in which the punching is not reliably performed, the present invention is to determine whether there is a large change in the phase between the logical data and the synchronous clock while the logical data is being transmitted.

Now, the present invention will be described in detail. FIG. 1 shows the configuration of an example of the logical data / synchronous clock phase determining apparatus according to the present invention. Normal,
Assuming that each of the logical data c is transmitted periodically or aperiodically in a state accompanied by a synchronous clock signal a near the center of the data, the synchronous clock signal a While being delayed by the hold time Th in the delay circuit 1 and input to the determination circuit 3 as a delay clock b,
The data is counted by the counting circuit 5. Each of the logic data c is input to each of the determination circuits 3 and 4, while being delayed by the setup time Ts by the delay circuit 1 and then input to the determination circuit 4 as delay data d.

FIG. 3 also shows the input / output waveforms of the main part in the logical data / synchronous clock phase judging device. The operation of the device will be described with reference to these main input / output waveforms. The explanation is as follows. That is, each of the determination circuits 3 and 4 detects and holds the data level state of the logical data c at the time of rising (even at the time of falling) of the synchronous clock signal a (see point B). Thing). In addition to the above, the determination circuit 3 detects and holds the data level state of the logical data c at the rising time (even at the falling time) of the delay clock b (see point C). The detected and held data level state is compared with the data level state of the logical data c at the time of the rise of the synchronous clock signal a, so that the data level states match (the hold time T
h is sufficient) and mismatch (when the hold time Th is insufficient) is determined. If they do not match, the determination circuit 3 outputs a hold time shortage detection signal e and counts by the counting circuit 6 as a cause of the phase failure between the logical data and the synchronous clock.

On the other hand, the decision circuit 4 also detects and detects the data level state of the delay data d at the rising time (even at the falling time) of the synchronous clock signal a.
Although the data level state is held (see point A), the detected and held data level state is compared with the data level state of the logical data c at the time of the rising edge of the synchronous clock signal a. It is determined that the level states match (when the setup time Ts is sufficient) and do not match (when the setup time Ts is insufficient). If they do not match, the judgment circuit 4 outputs the setup time shortage detection signal f and counts by the counting circuit 7 as the cause of the phase failure between the logical data and the synchronous clock.

In particular, in the above example, when the logical data c is transmitted very rarely and only aperiodically, the total value of the logical data c is obtained from the count values from the counters 5 to 7. Insufficient hold time for the number of transmissions The number of logical data,
Insufficient setup time The number of logical data is easily known.

[0013]

As described above, according to the first aspect, there is provided a logical data phase determination method capable of easily determining whether or not the relative phase relationship of a synchronous clock signal with respect to each logical data is good. In the case of item 2, a logical data phase determination device is provided which can easily determine whether the relative phase relationship of the synchronous clock signal to each logical data is good or bad.

[Brief description of the drawings]

FIG. 1 is a diagram showing the configuration of an example of a logical data / synchronous clock phase determining apparatus according to the present invention;

FIG. 2 is a diagram for explaining a setup time and a hold time in logical data;

FIG. 3 is a diagram for explaining the operation of the logical data / synchronous clock phase determination device shown in FIG. 1;

[Explanation of symbols]

1, 2, delay circuit, 3, 4, judgment circuit, 5-7, counting circuit

Claims (2)

[Claims] When the logical data is to be transmitted with a synchronous clock signal near the center of the logical data, it is determined whether the phase of the synchronous clock signal for each logical data is good or not. The method of determining the phase between the logical data and the synchronous clock, the rising point of the synchronous clock signal, or the data level state of the logical data at the falling point and the rising point of the synchronous clock signal of the logical data delayed by the setup time, Or, when the data level state at the falling point is not the same as the data level state, or at the rising point of the synchronous clock signal, or the data level state of the logical data at the falling point and the synchronous clock signal delayed by the hold time The data level state of the logical data at the time of rising or falling becomes the same data level state. A logic data / synchronous clock phase determination method in which the phase between the logic data / synchronous clocks is determined to be defective. 2. A method for determining whether a phase of a synchronous clock signal for each logical data is good when it is specified that each logical data is to be transmitted near a central portion of the data with a synchronous clock signal. A first delay circuit for delaying the logic data by a set-up time, a data level state of the logic data at a rising time or a falling time of the synchronization clock signal, and If the logical level of the logical data delayed by the first delay circuit by the setup time is compared with the data level at the rising or falling point of the synchronous clock signal, the logical data and the synchronous data are not synchronized. A first phase determination circuit that determines that the inter-clock phase is defective, and a second delay circuit that delays the synchronous clock signal by the hold time And the data level state of the logic data at the rising or falling point of the synchronous clock signal and the logic at the rising or falling point of the synchronous clock signal delayed by the hold time by the second delay circuit. A second phase determination circuit which determines that the phase between the logical data and the synchronous clock is defective if the data is not in the same data level state after comparing the data with the data level state; apparatus.