JPH11251635A - Semiconductor element and its manufacture - Google Patents

Semiconductor element and its manufacture

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Publication number
JPH11251635A
JPH11251635A JP4757698A JP4757698A JPH11251635A JP H11251635 A JPH11251635 A JP H11251635A JP 4757698 A JP4757698 A JP 4757698A JP 4757698 A JP4757698 A JP 4757698A JP H11251635 A JPH11251635 A JP H11251635A
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JP
Japan
Prior art keywords
layer
type
sic
electrode
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4757698A
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Japanese (ja)
Other versions
JP3813347B2 (en
Inventor
Yasuhiko Matsushita
保彦 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Tottori Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
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Application filed by Tokyo Sanyo Electric Co Ltd, Tottori Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP4757698A priority Critical patent/JP3813347B2/en
Publication of JPH11251635A publication Critical patent/JPH11251635A/en
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Abstract

PROBLEM TO BE SOLVED: To avoid the development of lattice defect due to the thermal cracking of the second layer during the growing step of the third layer, by a method wherein the third layer made of a GaN base compound semiconductor capable of being grown at lower temperature than SiC is grown on upper part of the second layer (active layer). SOLUTION: A semiconductor element composed of the first clad layer 2 made of p type SiC, an active layer 3 made of In(1-x) Gax N (0<=X<1), the second clad layer 4 made of n type Al'(1-y) Gay N (0<=Y<=1) successively laminated on a SiC substrate 1 is provided with an n type electrode in thickness exceeding 2 μm on the second clad layer 4. In such a constitution, the development of lattice defect due to the thermal cracking of the active layer 3 in the growing step of the clad layer 4 can be avoided by growing an n type clad layer 4 capable of low temperature growing on the upper part of the active layer 3. Besides, the n type electrode fills the role of a shock absorbing layer, so that the layers lower than the n type electrode may be turned into the thin films hardly having the crack due to the difference in lattice constants.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子とその製
造方法に関する。
The present invention relates to a semiconductor device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】GaN系、SiC系の材料は、青色発光
に適した材料として注目され、現在様々な技術が提案さ
れている。
2. Description of the Related Art GaN-based and SiC-based materials are attracting attention as materials suitable for blue light emission, and various techniques are currently proposed.

【0003】例えば特開平8−64910号公報では、
図4(A)に示すように、n型SiC基板10上にn型
SiCクラッド層11、InGaN活性層12、p型S
iCクラッド層13が順に積層され、このp型SiCク
ラッド層13上部中央にAl電極14が、n型SiC基
板10下部中央にNi電極15が形成された青色発光が
可能な半導体素子(以下、従来構造A)が提案されてい
る。
[0003] For example, in JP-A-8-64910,
As shown in FIG. 4A, an n-type SiC cladding layer 11, an InGaN active layer 12, a p-type S
An iC cladding layer 13 is sequentially stacked, an Al electrode 14 is formed in the upper center of the p-type SiC cladding layer 13, and a Ni electrode 15 is formed in the lower center of the n-type SiC substrate 10. Structure A) has been proposed.

【0004】また、同公報には、その従来技術として、
図4(B)に示すように、サファイヤ基板20上に、A
lGaNバッファ層21、n型GaN層22、n型Al
GaNクラッド層23、InGaN活性層24、p型A
lGaNクラッド層25、p型GaN層26、p型透明
電極27が順に積層され、更にこのp型透明電極27の
上にp型電極28が、n型GaN層22の一部にn型電
極29が形成された青色発光が可能な半導体素子(以
下、従来構造B)も開示されている。
[0004] Further, the same publication discloses, as its prior art,
As shown in FIG. 4B, on the sapphire substrate 20, A
lGaN buffer layer 21, n-type GaN layer 22, n-type Al
GaN cladding layer 23, InGaN active layer 24, p-type A
An lGaN cladding layer 25, a p-type GaN layer 26, and a p-type transparent electrode 27 are sequentially stacked. Further, a p-type electrode 28 is provided on the p-type transparent electrode 27, and an n-type electrode 29 is provided on a part of the n-type GaN layer 22. A semiconductor element capable of emitting blue light (hereinafter, referred to as a conventional structure B) formed with a blue light is also disclosed.

【0005】[0005]

【発明が解決しようとする課題】従来構造Aにおいて
は、低温成長(約800℃)のInGaN活性層12の
上部に高温成長(1400〜1500℃)のp型SiC
クラッド層13を成長させるため、p型SiCクラッド
層13の成長中にInGaN活性層12中のNが離脱し
て格子欠陥を生じやすく、良好な結晶が得られない、素
子特性が低下するなどの課題がある。
In the conventional structure A, a p-type SiC grown at a high temperature (1400 to 1500 ° C.) is formed on the InGaN active layer 12 grown at a low temperature (about 800 ° C.).
Since the cladding layer 13 is grown, N in the InGaN active layer 12 is easily released during the growth of the p-type SiC cladding layer 13 and lattice defects are likely to occur, so that good crystals cannot be obtained, and device characteristics are deteriorated. There are issues.

【0006】また、従来構造Bにおいては、p型GaN
層26及びp型AlGaNクラッド層25を形成する
際、アクセプタ添加層を成長後にアニール処理、電子線
照射処理などの後処理が必要であるため、製造工程が複
雑化するという課題がある。そしてまた、このような後
処理によってp型層は得られるが、その比抵抗値が数オ
ーム・cmと高く、十分低抵抗なp型層が得られないた
め、電流の広がりを図るための透明電極27を別途設け
る必要があり、製造工程が複雑化するという課題があ
る。この透明電極27は一般に、遮光性の金属材料を光
を透過できる程度に薄く成膜して形成する必要があるの
で、透明電極27を作成するための工程に高い制御性が
必要になるという課題がある。
In the conventional structure B, p-type GaN
When the layer 26 and the p-type AlGaN cladding layer 25 are formed, post-processing such as annealing and electron beam irradiation is required after growing the acceptor-added layer, and thus there is a problem that the manufacturing process is complicated. Although a p-type layer can be obtained by such a post-treatment, the specific resistance is as high as several ohm-cm, and a sufficiently low-resistance p-type layer cannot be obtained. It is necessary to provide the electrode 27 separately, and there is a problem that the manufacturing process is complicated. Generally, it is necessary to form the transparent electrode 27 by forming a light-shielding metal material so as to be thin enough to transmit light, so that a high controllability is required in a process for forming the transparent electrode 27. There is.

【0007】[0007]

【課題を解決するための手段】本発明は前記課題に鑑み
てなされたもので、基本的な特徴は、p型SiCからな
る第1の層、In(1-X)GaXN(0≦X<1)からなる
第2の層、n型GaN系化合物半導体からなる第3の層
を順に積層し、前記第3の層の上に厚みが2μ以上のn
型電極を備えて構成したことにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and has a basic feature that a first layer made of p-type SiC, In (1-X) Ga X N (0 ≦ X <1) and a third layer made of an n-type GaN-based compound semiconductor are sequentially stacked, and an n layer having a thickness of 2 μ or more is formed on the third layer.
That is, it is configured to include a mold electrode.

【0008】これにより、成膜工程において、In
(1-X)GaXN(0≦X<1)からなる第2の層の上部
に、SiC層(成長温度:1400〜1500℃)に比
べて低温成長可能なn型GaN系の第3層(成長温度:
1100℃)を成長させるため、In(1-X)GaXNから
なる第2の層の熱分解による格子欠陥の発生を防止する
ことができる。
Thus, in the film forming process, In
An n-type GaN-based third layer capable of growing at a lower temperature than the SiC layer (growth temperature: 1400 to 1500 ° C.) is formed on the second layer made of (1-X) Ga X N (0 ≦ X <1). Layer (growth temperature:
To grow the 1100 ° C.), it is possible to prevent occurrence of lattice defects due to thermal decomposition of the second layer of In (1-X) Ga X N.

【0009】加えて、第3の層の上に厚みが2μm以上
のn型電極を備えるので、このn型電極がワイヤーボン
ド時に加わる衝撃を効果的に吸収する衝撃吸収層として
機能し、n型電極の下の層を、格子定数差に起因するク
ラックの発生が生じにくい薄膜に維持することができ
る。また、n型電極の下のn型GaN系化合物半導体層
の厚みを増加させて衝撃吸収層として機能させる場合
は、その成膜に長時間要するが、n型電極の場合は、そ
の成膜を短時間で行うことができ、製造時間の短縮を図
ることができる。
In addition, since the n-type electrode having a thickness of 2 μm or more is provided on the third layer, the n-type electrode functions as a shock absorbing layer for effectively absorbing the shock applied at the time of wire bonding. The layer below the electrode can be maintained as a thin film in which cracks due to a difference in lattice constant do not easily occur. Further, when the thickness of the n-type GaN-based compound semiconductor layer under the n-type electrode is increased to function as a shock absorbing layer, the film formation takes a long time. This can be performed in a short time, and the manufacturing time can be reduced.

【0010】[0010]

【発明の実施の形態】以下本発明の実施例を、図1に示
す青色発光に適した半導体素子を例にとって説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to a semiconductor device suitable for blue light emission shown in FIG.

【0011】この半導体素子は、p型SiC単結晶基板
1上にp型SiC単結晶からなるp型クラッド層2、I
(1-X)GaXN(0≦X<1)からなる単層の活性層
3、n型Al(1-Y)GaYN(0≦Y≦1)単結晶からな
るn型クラッド層4を順に積層した構造となっている。
In this semiconductor device, a p-type clad layer 2 made of a p-type SiC single crystal and a p-type
Single-layer active layer 3 made of n (1-X) Ga X N (0 ≦ X <1), n - type clad made of single crystal of n-type Al (1-Y) Ga Y N (0 ≦ Y ≦ 1) It has a structure in which the layers 4 are sequentially laminated.

【0012】n型クラッド層4上には、TiとAlの積
層体からなるn型電極5が形成され、基板1裏面にはS
iとAlとAuの積層体からなるp型電極6が形成され
ている。
An n-type electrode 5 made of a laminate of Ti and Al is formed on the n-type cladding layer 4, and an S-type electrode 5 is formed on the back surface of the substrate 1.
A p-type electrode 6 made of a laminate of i, Al and Au is formed.

【0013】n型電極の厚みは一般に0.5μm前後に
設定されているが、従来、n型電極がこのような厚みで
あっても、n型電極と活性層の間には、比較的厚膜の層
が介在するので、それがワイヤーボンド時に活性層に加
わる衝撃を吸収する衝撃吸収層として機能することがで
きた。ここで、衝撃吸収層として機能する膜厚は、例え
ば上記n型AlGaNクラッド層4の場合、0.5μm
以上必要となる。ところが、n型AlGaNクラッド層
4を衝撃吸収層として機能するに必要な0.5μm以上
の膜厚に成膜すると、その下の層との格子定数差に起因
する応力が累積されてクラックが発生し易くなり、素子
特性の低下要因となるという問題が生じる。また、n型
AlGaNクラッド層4等の半導体層を衝撃吸収層とし
て厚膜に成膜する場合、成膜に要する時間が長くなって
製造効率が低下するという問題も生じる。
Although the thickness of the n-type electrode is generally set to about 0.5 μm, conventionally, even if the n-type electrode has such a thickness, a relatively large thickness is provided between the n-type electrode and the active layer. Since the film layer was interposed, it could function as a shock absorbing layer for absorbing the shock applied to the active layer during wire bonding. Here, for example, the thickness of the n-type AlGaN cladding layer 4 is 0.5 μm
This is necessary. However, if the n-type AlGaN cladding layer 4 is formed to a thickness of 0.5 μm or more necessary to function as a shock absorbing layer, cracks are generated due to accumulation of stress due to a difference in lattice constant with the layer below the layer. This causes a problem that the device characteristics are easily deteriorated. In addition, when a semiconductor layer such as the n-type AlGaN cladding layer 4 is formed into a thick film as a shock absorbing layer, there is a problem that the time required for the film formation becomes long and the manufacturing efficiency is reduced.

【0014】そこで、前記n型電極5は、図2に示す実
験結果に基づいて、その厚みを2μm以上に設定し、ワ
イヤーボンド時に活性層に加わる衝撃を吸収する衝撃吸
収層としてそれ自体で機能することができるように、厚
膜構造としている。
Therefore, the n-type electrode 5 has a thickness of 2 μm or more based on the experimental results shown in FIG. 2, and functions as a shock absorbing layer for absorbing the shock applied to the active layer during wire bonding. It has a thick film structure so that it can be used.

【0015】すなわち、活性層とn型電極の間に介在す
る(クラッド層4に代表される)GaN系化合物半導体
層の厚みのみが、0.1μm、0.2μmと相違する以
外は同一の2種類の素子について、そのn型電極の厚み
を0.5μmから0.5μm刻みに3.0μmまで変化
させたものに、ボールボンディング法によるワイヤーボ
ンドを同一条件で行った後、1000時間の連続通電実
験を行い、発光輝度が当初から70%以上低下した素子
数の割合を求めた結果、図2に示すような特性が得られ
た。この特性から明らかなように、2種類の素子につい
て、いずれもn型電極の厚みが2.0μmを越えるあた
りから素子特性の改善が図られ、2.5μmを越えると
素子特性の大幅な改善が図られていることが分かる。そ
こで、n型電極の厚みは2.0μm以上に設定するのが
好ましく、2.5μm以上に設定するのがより好まし
い。
That is, except that only the thickness of the GaN-based compound semiconductor layer (typified by the cladding layer 4) interposed between the active layer and the n-type electrode is 0.1 μm and 0.2 μm, For each type of element, the thickness of the n-type electrode was changed from 0.5 μm to 3.0 μm in steps of 0.5 μm, and after wire bonding by the ball bonding method was performed under the same conditions, continuous energization was performed for 1000 hours. An experiment was performed to determine the ratio of the number of elements whose emission luminance was reduced by 70% or more from the beginning. As a result, characteristics as shown in FIG. 2 were obtained. As is clear from these characteristics, for both of the two types of devices, the device characteristics are improved when the thickness of the n-type electrode exceeds 2.0 μm, and when the thickness exceeds 2.5 μm, the device characteristics are significantly improved. It can be seen that it is planned. Therefore, the thickness of the n-type electrode is preferably set to 2.0 μm or more, and more preferably to 2.5 μm or more.

【0016】図3に前記各層を構成する各種材料の物性
定数を示す。本実施例で使用するSiC材料には、6H
−SiC,4H−SiC,2H−SiCなど、各種多形
が存在し、それぞれで物性定数が異なる。またIn
(1-X)GaXN,Al(1-Y)GaYNの3元混晶材料の物性
定数は、それぞれの2元材料の間の値になる。また、本
実施例のダブルヘテロ構造では、活性層3のバンドギャ
ップエネルギより、p型クラッド層2及びn型クラッド
層4のバンドギャップエネルギを高くする必要がある。
FIG. 3 shows the physical property constants of various materials constituting each layer. The SiC material used in this embodiment includes 6H
There are various polymorphs such as -SiC, 4H-SiC, and 2H-SiC, each having a different physical property constant. Also In
The physical property constants of the ternary mixed crystal material of (1-X) Ga X N, Al (1-Y) Ga Y N are values between the respective binary materials. Further, in the double hetero structure of this embodiment, the band gap energy of the p-type cladding layer 2 and the n-type cladding layer 4 needs to be higher than that of the active layer 3.

【0017】この実施例の半導体素子において、例えば
青色発光させる場合には、活性層3のGa比率を0.6
〜0.8程度とし、かつ膜厚を500オングストローム
前後とすることが好適である。また、このような活性層
3において、効率よく発光を行わせるためには、活性層
3と各クラッド層2,4間のバンドギャップ差を大とす
ることが好ましい。従って、p型クラッド層2は1.0
μm程度の厚みの2H−SiCで構成し、一方、n型ク
ラッド層4はGa比率が0.8〜0.9程度で、かつ、
膜厚0.1〜0.2μm程度のn型Al(1-Y)GaY
(0≦Y≦1)で構成することが好ましい。
In the semiconductor device of this embodiment, for example, when emitting blue light, the Ga ratio of the active layer 3 is set to 0.6.
It is preferable that the thickness is about 0.8 and the film thickness is about 500 angstroms. In order to efficiently emit light in such an active layer 3, it is preferable to increase the band gap difference between the active layer 3 and each of the cladding layers 2 and 4. Therefore, the p-type cladding layer 2 has a thickness of 1.0
On the other hand, the n-type cladding layer 4 has a Ga ratio of about 0.8 to 0.9 and a thickness of about 2 μm.
N - type Al (1-Y) Ga Y N having a thickness of about 0.1 to 0.2 μm
(0 ≦ Y ≦ 1).

【0018】次に上記半導体素子の製造方法を以下に説
明する。
Next, a method of manufacturing the above semiconductor device will be described below.

【0019】まず第1の工程として、p型SiC単結晶
基板1上にp型SiC単結晶からなるp型クラッド層2
をCVD(化学気相成長)法を用いて成長させる。具体
的には、SiH4を流量0.5CC/分、C38 を流
量0.3CC/分の割合で注入し、基板温度を1500
℃に加熱する。また、Alをドープする為にド−パント
ガスとしてTMA[トリメチルアルミニウム:(C
33Al]を流量0.06CC/分の割合で注入す
る。また、本実施例ではp形SiC基板1の成長面とし
て(0001)面を用いているが、結晶の低指数面から
10°以下に傾いた、所謂オフアングル面を用いても良
い。
First, as a first step, a p-type clad layer 2 made of a p-type SiC single crystal is formed on a p-type SiC single crystal substrate 1.
Is grown using a CVD (Chemical Vapor Deposition) method. Specifically, SiH 4 is injected at a flow rate of 0.5 CC / min and C 3 H 8 is injected at a flow rate of 0.3 CC / min.
Heat to ° C. Also, TMA [trimethylaluminum: (C
H 3 ) 3 Al] is injected at a flow rate of 0.06 CC / min. In the present embodiment, the (0001) plane is used as the growth plane of the p-type SiC substrate 1. However, a so-called off-angle plane that is inclined by 10 ° or less from the low index plane of the crystal may be used.

【0020】次に第2の工程として、InGaN活性層
3をMOCVD(有機金属化学気相成長)法を用いて成
長させる。具体的には、TMI[トリメチルインジウ
ム:(CH33In]を流量15μmol/分、TEG
[トリエチルガリウム:(C253Ga]を流量0.
7μmol/分、NH3を流量2.0l/分の割合で注
入し、基板温度を800℃に加熱してInGaN層3を
成長させる。
Next, as a second step, an InGaN active layer 3 is grown by MOCVD (metal organic chemical vapor deposition). Specifically, TMI [trimethyl indium: (CH 3 ) 3 In] was supplied at a flow rate of 15 μmol / min and TEG.
[Triethylgallium: (C 2 H 5 ) 3 Ga] was added at a flow rate of 0.1%.
7 μmol / min and NH 3 are injected at a flow rate of 2.0 l / min, and the substrate temperature is heated to 800 ° C. to grow the InGaN layer 3.

【0021】次に第3の工程としてn型AlGaNクラ
ッド層4をMOCVD成長法を用いて成長させる。具体
的には、TMAを流量4.0μmol/分、TMGを流
量27μmol/分、NH3を流量2.0l/分の割合
で注入し、基板温度を1100℃に加熱する。また、S
iを添加する為にドーパントガスとしてSiH4を流量
1.5nmol/分の割合で注入する。
Next, as a third step, an n-type AlGaN cladding layer 4 is grown by MOCVD. Specifically, TMA is injected at a flow rate of 4.0 μmol / min, TMG at a flow rate of 27 μmol / min, and NH 3 at a flow rate of 2.0 l / min, and the substrate temperature is heated to 1100 ° C. Also, S
In order to add i, SiH 4 is injected as a dopant gas at a flow rate of 1.5 nmol / min.

【0022】次に第4の工程として、n型クラッド層4
上に、TiとAlの積層体からなるn型電極5を蒸着も
しくはスパッタリング装置を利用して2.0μm以上、
好ましくは2.5μm以上の厚さに成膜した後、必要に
応じて円形等の所望の形状にパターニング処理する。
Next, as a fourth step, the n-type cladding layer 4 is formed.
On top, an n-type electrode 5 made of a laminate of Ti and Al is deposited to a thickness of 2.0 μm or more using a vapor deposition or sputtering device.
Preferably, after forming a film having a thickness of 2.5 μm or more, a patterning process is performed, if necessary, into a desired shape such as a circle.

【0023】最後に、第5の工程として、基板1裏面
に、SiとAlとAuの積層体からなるp型電極6を蒸
着もしくはスパッタリング装置を利用して1.0μm前
後の厚さに成膜した後、必要に応じて円形等の所望の形
状にパターニング処理する。
Finally, as a fifth step, a p-type electrode 6 made of a laminate of Si, Al and Au is formed on the back surface of the substrate 1 to a thickness of about 1.0 μm using a vapor deposition or sputtering apparatus. After that, a patterning process is performed, if necessary, into a desired shape such as a circle.

【0024】このように、InGaN活性層3の上部に
は、SiCに比べて低温成長可能なAlGaNクラッド
層4を成長させるので、AlGaNクラッド層4の成長
中に、InGaN活性層3が格子欠陥を生じる危険性を
低減することができる。
As described above, since the AlGaN cladding layer 4 that can be grown at a lower temperature than SiC is grown on the InGaN active layer 3, the InGaN active layer 3 has a lattice defect during the growth of the AlGaN cladding layer 4. The risk of occurrence can be reduced.

【0025】上記実施例の構造によれば、GaN系化合
物クラッド層4はn型であるため、従来構造Bのように
GaN系の層をp型にする場合に比べて、比抵抗値を小
さくすることができ、従来構造Bの場合のようなp型化
するためのアニール処理や電子線照射処理等の後処理を
不要として製造工数の削減を図ることができる。
According to the structure of the above embodiment, since the GaN-based compound cladding layer 4 is of the n-type, the specific resistance is smaller than that of the conventional structure B in which the GaN-based layer is of the p-type. This eliminates the need for post-processing such as annealing or electron beam irradiation for p-type as in the case of the conventional structure B, thereby reducing the number of manufacturing steps.

【0026】また、GaN系化合物クラッド層4はn型
であり、p型である場合に比べて比抵抗値が小さいた
め、従来構造Bのような透明電極の形成も不要となり、
透明電極形成のための工程を不要として、構成部材の削
減と製造工数の削減を図ることができる。
Further, since the GaN-based compound cladding layer 4 is of the n-type and has a lower specific resistance value than that of the p-type, the formation of a transparent electrode as in the conventional structure B is unnecessary.
Since the process for forming the transparent electrode is unnecessary, the number of constituent members and the number of manufacturing steps can be reduced.

【0027】加えて、膜厚が2μm以上のn型電極5を
備えるので、このn型電極5がワイヤーボンド時に加わ
る衝撃を効果的に吸収する衝撃吸収層として機能し、n
型電極5の下の層を、格子定数差に起因するクラックの
発生が生じにくい薄膜に維持することができる。また、
n型GaN系化合物半導体層4の成膜時間に比べて、n
型電極5の成膜時間は数分の1程度で済むので、衝撃吸
収層として機能する層の成膜時間を大幅に短縮して製造
時間の短縮を図ることができる。
In addition, since the n-type electrode 5 having a thickness of 2 μm or more is provided, the n-type electrode 5 functions as a shock absorbing layer for effectively absorbing the shock applied during wire bonding.
The layer under the mold electrode 5 can be maintained as a thin film in which cracks due to a difference in lattice constant are less likely to occur. Also,
As compared with the film formation time of the n-type GaN-based compound semiconductor layer 4, n
Since the time required for forming the mold electrode 5 is only about a fraction, the time required for forming the layer functioning as the shock absorbing layer can be significantly reduced, and the manufacturing time can be reduced.

【0028】尚、上記実施例では、n型電極5としてT
iとAlの積層体を用いたが、n型電極5は、これ以外
の材料の組み合わせを利用することができ、例えば、A
lとSiの積層体、AlとCuの積層体なども利用する
ことができる。
In the above embodiment, the n-type electrode 5 is made of T
Although a laminated body of i and Al was used, the n-type electrode 5 can use a combination of other materials.
A laminate of l and Si, a laminate of Al and Cu, and the like can also be used.

【0029】また、上記実施例では、活性層3が単層構
造の場合を示したが、活性層3として多層膜活性層を利
用することができる。すなわち、前記活性層3として、
少なくともクラッド層2、4と接するように配置したI
(1-X1)GaX1N(0<X1<1)単結晶からなる複数
の第1のInGaN層3aと、第1のInGaN層3a
に挟まれるように配置した少なくとも1以上のIn
(1-X2)GaX2N(0≦X2<X1<1)単結晶からなる
第2のInGaN層3bを交互に積層した多層膜からな
る多層膜活性層(多重量子井戸構造層)構造を用いても
良い。
Further, in the above embodiment, the case where the active layer 3 has a single-layer structure is described, but a multi-layered active layer can be used as the active layer 3. That is, as the active layer 3,
At least I is disposed so as to be in contact with the cladding layers 2 and 4.
a plurality of first InGaN layers 3a made of n (1-X1) Ga X1 N (0 <X1 <1) single crystal; and a first InGaN layer 3a
At least one or more In
A (1-X2) Ga X2 N (0 ≦ X2 <X1 <1) multi-layer active layer (multi-quantum well structure layer) structure composed of a multi-layer film in which second InGaN layers 3b composed of single crystals are alternately stacked is used. May be.

【0030】また、n型AlGaNクラッド層4の上部
に必要に応じてn型GaN層をキャップ層として積層
し、その上部にn型電極を形成することもでき、このよ
うにすれば、n型電極とのオーミック特性を良好(電極
の接触抵抗が小さい)にして素子の駆動電圧を低下させ
ることができる。
Further, if necessary, an n-type GaN layer may be stacked as a cap layer on the n-type AlGaN cladding layer 4 and an n-type electrode may be formed on the cap layer. The driving voltage of the element can be reduced by improving the ohmic characteristics with the electrode (the contact resistance of the electrode is small).

【0031】さらに、上記実施例ではp型SiC基板に
p型SiCクラッド層、活性層、n型Al(1-Y)GaY
(0≦Y≦1)クラッド層を順に積層してなる構成につ
いて説明したが、n型SiC基板上にn型SiCクラッ
ド層、活性層、p型GaN系化合物半導体層(クラッド
層)を順に積層させた場合も上述の実施例と同様の効果
は得られる。しかし、p型GaN系化合物半導体層はn
型GaN系に比べて高抵抗であるため、透明電極の形成
など接合面での均一な電流分布を得るための構造が別途
必要となる。
Further, in the above embodiment, a p-type SiC cladding layer, an active layer, an n-type Al (1-Y) Ga Y N
(0 ≦ Y ≦ 1) The configuration in which the clad layers are sequentially stacked has been described. However, an n-type SiC clad layer, an active layer, and a p-type GaN-based compound semiconductor layer (clad layer) are sequentially stacked on an n-type SiC substrate. In this case, the same effect as in the above embodiment can be obtained. However, the p-type GaN-based compound semiconductor layer has n
Since the resistance is higher than that of the GaN type, a structure for obtaining a uniform current distribution at the joint surface such as formation of a transparent electrode is separately required.

【0032】また、n型またはi形(高抵抗)SiC基
板上にp型SiCクラッド層、活性層、n型GaN系化
合物半導体層(クラッド層)を順に積層させた場合も上
述の実施例と同様の効果は得られる。しかし、SiC基
板にp型電極を設けることができないので、従来構造B
と同様な電極構造が別途必要となる(但し、この場合
は、n型GaN系のクラッド層が低抵抗であるため、透
明電極の形成は不要である)。
In the case where a p-type SiC cladding layer, an active layer, and an n-type GaN-based compound semiconductor layer (cladding layer) are sequentially laminated on an n-type or i-type (high-resistance) SiC substrate, the above-described embodiment will be described. The same effect can be obtained. However, since the p-type electrode cannot be provided on the SiC substrate, the conventional structure B
(In this case, the formation of a transparent electrode is unnecessary because the n-type GaN-based cladding layer has a low resistance.)

【0033】また、上記実施例は発光ダイオードを例に
取り説明したが、本発明は受光素子、半導体レーザ等の
他の半導体素子にも適応することができる。
Although the above embodiment has been described by taking a light emitting diode as an example, the present invention can be applied to other semiconductor elements such as a light receiving element and a semiconductor laser.

【0034】[0034]

【発明の効果】本発明の半導体素子は、In(1-X)GaX
N(0≦X<1)からなる第2の層(活性層)の上部に
SiCに比べて低温成長可能なGaN系化合物半導体か
らなる第3の層(Al(1-Y)GaYN(0≦Y≦1)から
なるクラッド層)を成長させるので、第3の層の成長中
の第2の層の熱分解による格子欠陥の発生を回避するこ
とができる。加えて、第3の層の上に膜厚が2μm以上
のn型電極を備えるので、このn型電極がワイヤーボン
ド時に加わる衝撃を効果的に吸収する衝撃吸収層として
機能し、n型電極の下の層を、格子定数差に起因するク
ラックの発生が生じにくい薄膜に維持することができ
る。また、n型電極の下のn型GaN系化合物半導体層
の厚みを増加させて衝撃吸収層として機能させる場合
は、その成膜に長時間要するが、n型電極の場合は、そ
の成膜を短時間で行うことができ、製造時間の短縮を図
ることができる。
According to the present invention, the semiconductor device of the present invention comprises In (1-X) Ga X
A third layer (Al (1-Y) Ga Y N ( ) made of a GaN-based compound semiconductor that can be grown at a lower temperature than SiC on the second layer (active layer) made of N (0 ≦ X <1) Since the cladding layer (0 ≦ Y ≦ 1) is grown, lattice defects due to thermal decomposition of the second layer during growth of the third layer can be avoided. In addition, since the n-type electrode having a film thickness of 2 μm or more is provided on the third layer, the n-type electrode functions as a shock absorbing layer for effectively absorbing the shock applied at the time of wire bonding. The lower layer can be maintained as a thin film in which cracks due to a difference in lattice constant do not easily occur. Further, when the thickness of the n-type GaN-based compound semiconductor layer under the n-type electrode is increased to function as a shock absorbing layer, the film formation takes a long time. This can be performed in a short time, and the manufacturing time can be reduced.

【0035】以上のことから、本発明によれば、発光効
率が高く高品質な半導体素子を実現することができる。
As described above, according to the present invention, a high-quality semiconductor device having high luminous efficiency can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例における半導体素子の構造を
示した図である。
FIG. 1 is a diagram showing a structure of a semiconductor device according to one embodiment of the present invention.

【図2】電極の厚みとワイヤ−ボンド後の素子特性の関
係を示す特性図である。
FIG. 2 is a characteristic diagram showing a relationship between electrode thickness and device characteristics after wire-bonding.

【図3】本発明の実施例における半導体素子に使用する
各種材料の物性定数を示した図である。
FIG. 3 is a view showing physical property constants of various materials used for a semiconductor device in an example of the present invention.

【図4】(A)(B)は、従来技術による半導体素子の
構造を示した図である。
FIGS. 4A and 4B are views showing a structure of a semiconductor device according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 p型SiC基板 2 p型SiCクラッド層 3 InGaN活性層 4 n型AlGaNクラッド層 5 n型電極 6 p型電極 Reference Signs List 1 p-type SiC substrate 2 p-type SiC cladding layer 3 InGaN active layer 4 n-type AlGaN cladding layer 5 n-type electrode 6 p-type electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 p型SiCからなる第1の層、In
(1-X)GaXN(0≦X<1)からなる第2の層、n型G
aN系化合物半導体からなる第3の層、を順に積層した
半導体素子であって、前記第3の層の上に厚みが2μm
以上のn型電極を備えることを特徴とする半導体素子。
1. A first layer made of p-type SiC, In
(1-X) Second layer made of Ga X N (0 ≦ X <1), n-type G
a third layer made of an aN-based compound semiconductor, the second layer being sequentially stacked, and having a thickness of 2 μm on the third layer.
A semiconductor device comprising the above n-type electrode.
【請求項2】 SiC基板上にp型SiCからなる第1
のクラッド層、In(1 -X)GaXN(0≦X<1)からな
る活性層、n型Al(1-Y)GaYN(0≦Y≦1)からな
る第2のクラッド層を順に積層した半導体素子であっ
て、前記第2のクラッド層の上に厚みが2μm以上のn
型電極を備えることを特徴とする半導体素子。
2. The method according to claim 1, wherein a first type of p-type SiC is formed on a SiC substrate.
Cladding layer, an active layer composed of In (1- X) Ga X N (0 ≦ X <1), and a second cladding layer composed of n-type Al (1-Y) Ga Y N (0 ≦ Y ≦ 1) Are stacked in this order, wherein n having a thickness of 2 μm or more is formed on the second cladding layer.
A semiconductor element comprising a mold electrode.
【請求項3】 SiC基板上にCVD成長法によりp型
SiCからなるクラッド層を成膜する第1の工程と、前
記クラッド層上にIn(1-X)GaXN(0≦X<1)から
なる活性層をMOCVD成長法により成膜する第2の工
程と、前記活性層上にn型Al(1-Y)GaYN(0≦Y≦
1)からなるクラッド層をMOCVD成長法により成膜
する第3の工程と、n型Al(1-Y)GaYN(0≦Y≦
1)クラッド層の上に厚みが2μm以上のn型電極を蒸
着もしくはスパッタリングによって形成する第4の工程
を有することを特徴とする半導体素子の製造方法。
3. A first step of forming a clad layer made of p-type SiC on a SiC substrate by a CVD growth method, and forming an In (1-X) Ga X N (0 ≦ X <1 ) on the clad layer. A) forming an active layer of MOCVD growth method, and n-type Al (1-Y) Ga Y N (0 ≦ Y ≦
A third step of forming a cladding layer made of 1) by MOCVD growth, and n-type Al (1-Y) Ga Y N (0 ≦ Y ≦
1) A method for manufacturing a semiconductor device, comprising a fourth step of forming an n-type electrode having a thickness of 2 μm or more on a cladding layer by vapor deposition or sputtering.
JP4757698A 1998-02-27 1998-02-27 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3813347B2 (en)

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JP4757698A JP3813347B2 (en) 1998-02-27 1998-02-27 Semiconductor device and manufacturing method thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8076694B2 (en) 2005-05-02 2011-12-13 Nichia Corporation Nitride semiconductor element having a silicon substrate and a current passing region

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8076694B2 (en) 2005-05-02 2011-12-13 Nichia Corporation Nitride semiconductor element having a silicon substrate and a current passing region

Also Published As

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