JPH11251609A - Photovoltaic element and its manufacture - Google Patents

Photovoltaic element and its manufacture

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Publication number
JPH11251609A
JPH11251609A JP10053447A JP5344798A JPH11251609A JP H11251609 A JPH11251609 A JP H11251609A JP 10053447 A JP10053447 A JP 10053447A JP 5344798 A JP5344798 A JP 5344798A JP H11251609 A JPH11251609 A JP H11251609A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor layer
main surface
semiconductor
amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10053447A
Other languages
Japanese (ja)
Other versions
JP3679598B2 (en
Inventor
Toshio Asaumi
利夫 浅海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP05344798A priority Critical patent/JP3679598B2/en
Publication of JPH11251609A publication Critical patent/JPH11251609A/en
Application granted granted Critical
Publication of JP3679598B2 publication Critical patent/JP3679598B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Photovoltaic Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To generate superior photoelectric conversion characteristics without preventing the movement of carriers due to inverse junction, by providing inverse conduction-type semiconductor layers on both the main surfaces of a substrate, and providing rectifying junction on the entire surface of the substrate including a side surface. SOLUTION: A second semiconductor layer 7 is formed on one main surface of an n-type substrate 1. Then, a first semiconductor layer 3 is formed on the other. In this case, n/p/n rectifying junction where the second and first semiconductor layers 7 and 3 are successively laminated on the substrate 1 is formed at a peripheral end part on one main surface that becomes a light incidence side as in A. An n/n/p rectifying junction is formed also at a peripheral end part on the other main surface that becomes a light transmission side as in B. When the first semiconductor layer 3 is formed on one main surface of the n-type substrate 1, and then the second semiconductor layer 7 is formed on the other, the inverse junction of n/p/n where the second and first semiconductor layers 7 and 3 are successively laminated is formed on the substrate 1 at the periphery end part on one main surface of the light incidence side as in A, and the inverse junction of n/p/n is formed at the periphery end part on the other of the light transmission side as in B.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高い光電変換効率
を有する光起電力素子を製造する技術に属する。
The present invention relates to a technique for manufacturing a photovoltaic element having high photoelectric conversion efficiency.

【0002】[0002]

【従来の技術】太陽電池、光センサ等の光起電力素子に
おいては、近年高い変換効率と低い製造コストとを両立
するために、単結晶シリコン、多結晶シリコン等の結晶
系半導体と非晶質もしくは微結晶を有するシリコン等の
半導体とを組み合わせてなる光起電力素子が検討されて
いる(例えば特開平5−102504号に詳しい)。
2. Description of the Related Art In recent years, in photovoltaic elements such as solar cells and optical sensors, in order to achieve both high conversion efficiency and low production cost, crystalline semiconductors such as monocrystalline silicon and polycrystalline silicon have been used. Alternatively, a photovoltaic element formed by combining with a semiconductor such as silicon having microcrystals has been studied (for example, see JP-A-5-102504).

【0003】図4は斯かる光起電力素子の素子構造断面
図であり、1はn型の単結晶または多結晶シリコン等の
結晶系半導体からなる基板、2は該基板1の一主面上に
形成された、真性の非晶質または微結晶シリコン等の非
結晶性半導体からなる膜厚約100Åの真性半導体層、
3は該真性半導体層上に形成された、前記基板1とは逆
導電型を有するp型の非晶質または微結晶シリコン等の
非結晶性半導体からなる膜厚約100Åの第一半導体層
であり、該第一半導体層3上にはSnO2、ITO等の
透光性導電材からなる透光性電極4、及び櫛型形状を有
するAg,Al等の導電材からなる集電極5が形成され
ている。
FIG. 4 is a sectional view of the element structure of such a photovoltaic element. Reference numeral 1 denotes a substrate made of a crystalline semiconductor such as n-type single crystal or polycrystalline silicon; An intrinsic semiconductor layer having a thickness of about 100 ° and made of an amorphous semiconductor such as intrinsic amorphous or microcrystalline silicon,
Reference numeral 3 denotes a first semiconductor layer formed on the intrinsic semiconductor layer and made of a non-crystalline semiconductor such as p-type amorphous or microcrystalline silicon having a conductivity type opposite to that of the substrate 1 and having a thickness of about 100 °. On the first semiconductor layer 3, there are formed a light-transmissive electrode 4 made of a light-transmissive conductive material such as SnO 2 or ITO, and a collecting electrode 5 made of a comb-shaped conductive material such as Ag or Al. Have been.

【0004】また、前記基板1の他主面上には真性の非
晶質または微結晶シリコン等の非結晶性半導体からなる
膜厚約100Åの真性半導体層6、n型の非晶質または
微結晶シリコン等の非結晶性半導体からなる膜厚約20
0Åの第二半導体層7、及びSnO2、ITO等の透光
性導電材からなる透光性電極8、及び櫛型形状を有する
Ag,Al等の導電材からなる集電極9が順次形成され
ている。
On the other main surface of the substrate 1, an intrinsic semiconductor layer 6 having a thickness of about 100 ° made of an amorphous semiconductor such as intrinsic amorphous or microcrystalline silicon, or an n-type amorphous or A film thickness of about 20 made of an amorphous semiconductor such as crystalline silicon
A second semiconductor layer 7 of 0 °, a light-transmitting electrode 8 made of a light-transmitting conductive material such as SnO 2 , ITO, and a collecting electrode 9 made of a comb-shaped conductive material such as Ag or Al are sequentially formed. ing.

【0005】そして、斯かる光起電力素子においては基
板1の一主面上に備える真性半導体層2,第一半導体層
3及び他主面上の真性半導体層6,第二半導体層7をい
ずれも非晶質または微結晶の非結晶性半導体で構成して
いる。従って、上記各層2,3,6及び7の形成をいず
れもプラズマCVD法を用いて200℃程度の温度で行
うことができることから、従来pn接合の形成に100
0℃以上の高温を要していた結晶系光起電力素子に比べ
製造コストを低減でき、且つ特性的にも遜色のない光起
電力素子を得ることができる。
In such a photovoltaic device, the intrinsic semiconductor layer 2 provided on one main surface of the substrate 1, the first semiconductor layer 3, the intrinsic semiconductor layer 6 on the other main surface, and the second semiconductor layer 7 are formed. Is also composed of an amorphous or microcrystalline non-crystalline semiconductor. Therefore, since the formation of each of the layers 2, 3, 6, and 7 can be performed at a temperature of about 200 ° C. by using the plasma CVD method, the conventional method of forming a pn junction is 100%.
The manufacturing cost can be reduced as compared with a crystal-based photovoltaic element that required a high temperature of 0 ° C. or higher, and a photovoltaic element that is comparable in characteristics can be obtained.

【0006】[0006]

【発明が解決しようとする課題】ところで、図4に示し
た構造の光起電力素子を製造するにあたっては、洗浄済
の基板1をプラズマCVD装置内に導入し、そして該基
板1の一主面上に真性半導体層2,第一半導体層3を、
また前記基板1の他主面上に真性半導体層6,第二半導
体層7を、夫々プラズマCVD法により形成することと
なる。
In manufacturing a photovoltaic device having the structure shown in FIG. 4, a cleaned substrate 1 is introduced into a plasma CVD apparatus, and one main surface of the substrate 1 is manufactured. The intrinsic semiconductor layer 2 and the first semiconductor layer 3 are formed thereon.
In addition, the intrinsic semiconductor layer 6 and the second semiconductor layer 7 are formed on the other main surface of the substrate 1 by the plasma CVD method.

【0007】然し乍ら、斯かる従来の方法では、高い光
電変換特性を有する光起電力素子を再現性良く得ること
が困難であった。
However, it is difficult for such a conventional method to obtain a photovoltaic element having high photoelectric conversion characteristics with good reproducibility.

【0008】[0008]

【課題を解決するための手段】斯かる課題を解決するた
めに、本発明に係る光起電力素子は、基板の両主面上
に、夫々互いに逆導電型を有する半導体層を設けてなる
光起電力素子であって、側面を含む前記基板の全面に整
流接合を備えたことを特徴とする。
In order to solve the above-mentioned problems, a photovoltaic device according to the present invention is a photovoltaic device comprising semiconductor layers having opposite conductivity types on both main surfaces of a substrate. An electromotive element, wherein a rectifying junction is provided on the entire surface of the substrate including a side surface.

【0009】さらに、前記基板が結晶系半導体からな
り、前記半導体層が共に非晶質もしくは微結晶半導体か
らなることを特徴とし、前記基板の両主面と前記半導体
層との間に、非晶質もしくは微結晶半導体からなる真性
半導体層を介在せしめたことを特徴とする。
Further, the substrate is made of a crystalline semiconductor, and both of the semiconductor layers are made of an amorphous or microcrystalline semiconductor, and an amorphous material is provided between both main surfaces of the substrate and the semiconductor layer. Characterized in that an intrinsic semiconductor layer made of a crystalline or microcrystalline semiconductor is interposed.

【0010】また、本発明に係る光起電力素子の製造方
法は、基板の両主面上に、互いに逆導電型を有する半導
体層を備えてなる光起電力素子の製造方法であって、前
記基板の一方の主面上に、前記半導体層のうち前記基板
と同導電型を示す一方の半導体層を形成した後に、前記
基板の他方の主面上に他方の半導体層を形成することを
特徴とする。
Further, a method of manufacturing a photovoltaic element according to the present invention is a method of manufacturing a photovoltaic element comprising semiconductor layers having opposite conductivity types on both main surfaces of a substrate, Forming one semiconductor layer having the same conductivity type as that of the substrate on the one main surface of the substrate, and then forming the other semiconductor layer on the other main surface of the substrate. And

【0011】さらに、前記基板が結晶系半導体からな
り、前記半導体層が非晶質もしくは微結晶半導体からな
ることを特徴とし、加えて前記基板と前記半導体層との
間に、非晶質もしくは微結晶半導体からなる真性半導体
層を形成する工程を備えることを特徴とする。
Further, the substrate is made of a crystalline semiconductor, and the semiconductor layer is made of an amorphous or microcrystalline semiconductor. In addition, an amorphous or microcrystalline semiconductor is provided between the substrate and the semiconductor layer. A step of forming an intrinsic semiconductor layer made of a crystalline semiconductor.

【0012】[0012]

【発明の実施の形態】図1は本発明製造方法により図4
に示した光起電力素子を製造する工程を説明するための
工程別素子構造図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
FIG. 6 is an element structure diagram for each step for explaining a step of manufacturing the photovoltaic element shown in FIG.

【0013】まず、同図(A)に示す工程においては、
約500μmのn型の単結晶シリコンからなる基板1の
一方の主面上に、プラズマCVD法を用いて真性の非晶
質或いは微結晶シリコンからなる真性半導体層6及び、
前記基板と同導電型を示すn型の非晶質もしくは微結晶
シリコンからなる第二半導体層7を順次形成する。
First, in the step shown in FIG.
An intrinsic semiconductor layer 6 made of intrinsic amorphous or microcrystalline silicon on one main surface of a substrate 1 made of n-type single crystal silicon of about 500 μm using a plasma CVD method;
A second semiconductor layer 7 made of n-type amorphous or microcrystalline silicon having the same conductivity type as the substrate is sequentially formed.

【0014】次いで、同図(B)に示す工程において
は、上記基板1の他方の主面上に、プラズマCVD法を
用いて真性の非晶質或いは微結晶シリコンからなる真性
半導体層2及びp型の非晶質或いは微結晶シリコンから
なる第一半導体層3を順次形成する。
Next, in the step shown in FIG. 1B, the intrinsic semiconductor layer 2 made of intrinsic amorphous or microcrystalline silicon and the p-type semiconductor layer 2 are formed on the other main surface of the substrate 1 by plasma CVD. A first semiconductor layer 3 made of a type of amorphous or microcrystalline silicon is sequentially formed.

【0015】最後に、上記第一半導体層3及び第二半導
体層7上に夫々ITO又はSnO2からなる透光性導電
膜4,8を形成し、これら透光性導電膜4,8上に夫々
櫛型形状を有する集電極5,9を形成し、図4に示した
構成の光起電力素子を完成する。
Finally, light-transmitting conductive films 4 and 8 made of ITO or SnO 2 are formed on the first semiconductor layer 3 and the second semiconductor layer 7, respectively. Collector electrodes 5 and 9 each having a comb shape are formed, and the photovoltaic element having the configuration shown in FIG. 4 is completed.

【0016】本発明によれば、光電変換特性の良好な光
起電力素子を再現性良く得ることが可能となる。この理
由を以下に詳述する。
According to the present invention, it is possible to obtain a photovoltaic element having good photoelectric conversion characteristics with good reproducibility. The reason will be described in detail below.

【0017】図2は本発明により光電変換特性の良好な
光起電力素子を再現性良く得ることできる理由を説明す
るための説明図であり、同図(A)は先に基板の他主面
上に、該基板と同導電型を示す第二半導体層を形成して
製造した光起電力素子の、また同図(B)は、先に基板
の一主面上に、該基板と逆導電型を示す第一半導体層を
形成して製造した光起電力素子の、要部拡大断面図を夫
々示している。尚、簡単のために真性半導体層2及び6
は省略している。
FIG. 2 is an explanatory view for explaining the reason why a photovoltaic element having a good photoelectric conversion characteristic can be obtained with good reproducibility according to the present invention. FIG. A photovoltaic element manufactured by forming a second semiconductor layer having the same conductivity type as that of the substrate above, and FIG. The main part enlarged sectional view of the photovoltaic element manufactured by forming the 1st semiconductor layer which shows a type | mold is each shown. For simplicity, the intrinsic semiconductor layers 2 and 6
Is omitted.

【0018】一般にプラズマCVD法を用いて基板の一
方の面上に薄膜を形成せんとすると、基板の側面及び他
方の面上にも薄膜が回り込んで形成される。
In general, when a thin film is to be formed on one surface of a substrate by using a plasma CVD method, the thin film is formed so as to wrap around on the side surface and the other surface of the substrate.

【0019】従って、n型の基板1の他主面上に先に第
二半導体層7を形成し、然る後に基板1の一主面上に第
一半導体層3を形成した場合にあっては、図2(A)の
Aに示す如く、光入射側となる一主面上の周端部におい
て基板1上に第二半導体層7及び第一半導体層3が順次
積層されてなるn/n/pの整流接合が形成されること
となる。また、光透過側となる他主面上の周端部におい
てもBに示すようにn/n/pの整流接合が形成される
こととなる。
Therefore, in the case where the second semiconductor layer 7 is formed first on the other main surface of the n-type substrate 1 and then the first semiconductor layer 3 is formed on one main surface of the substrate 1 As shown in A of FIG. 2A, n / n is obtained by sequentially laminating the second semiconductor layer 7 and the first semiconductor layer 3 on the substrate 1 at the peripheral end on one main surface on the light incident side. An n / p rectifying junction is formed. Also, a rectifying junction of n / n / p is formed at the peripheral end on the other main surface on the light transmission side, as shown by B.

【0020】一方、 n型の基板1の一主面上に先に第
一半導体層3を形成し、しかる後に基板1の他主面上に
第二半導体層7を形成した場合にあっては、図2(B)
のAに示す如く、光入射側となる一主面上の周端部にお
いて基板1上に第一半導体層3及び第二半導体層7が順
次積層されてなるn/p/nの逆接合が形成されること
となる。また、光透過側となる他主面上の周端部におい
てもBに示すようにn/p/nの逆接合が形成されるこ
ととなる。
On the other hand, when the first semiconductor layer 3 is formed first on one main surface of the n-type substrate 1 and then the second semiconductor layer 7 is formed on the other main surface of the substrate 1, , FIG. 2 (B)
As shown in FIG. 1A, an n / p / n reverse junction formed by sequentially laminating the first semiconductor layer 3 and the second semiconductor layer 7 on the substrate 1 is formed at the peripheral end on one main surface on the light incident side. Will be formed. In addition, a reverse junction of n / p / n is formed at the peripheral end portion on the other main surface which is on the light transmission side as shown in B.

【0021】これらの場合において、本発明に相当する
図2(A)の場合にあっては、基板1の両主面上の周端
部A,Bに形成される接合はいずれもn/n/pの整流
接合であるので特に光電変換特性に大きな影響を与える
ことはない。
In these cases, in the case of FIG. 2A corresponding to the present invention, the joints formed at the peripheral ends A and B on both main surfaces of the substrate 1 are both n / n Since the rectifying junction is / p, the photoelectric conversion characteristics are not significantly affected.

【0022】然し乍ら、同図(B)の場合にあっては、
基板1の両主面上の周端部A,Bにいずれもn/p/n
の逆接合が形成されることとなり、この逆接合がキャリ
アの移動を妨げるバリアとして作用するために光電変換
特性が低下することとなる。特に第一半導体層の形成時
にドーピングガスとしてB26を用いた場合にあって
は、B26ガスは室温でも分解することから基板1の全
面にB26の分解生成物が付着し、このため基板1の他
主面上の全面においてn/p/nの逆接合が形成される
ことから、その影響が一層大きなものとなる。
However, in the case of FIG.
Both peripheral edges A and B on both main surfaces of the substrate 1 have n / p / n
Is formed, and this reverse junction acts as a barrier that hinders the movement of carriers, so that the photoelectric conversion characteristics are degraded. Particularly in a case where using a B 2 H 6 as a doping gas at the time of forming the first semiconductor layer, B 2 H 6 gas decomposition products of B 2 H 6 from decomposing even at room temperature over the entire surface of the substrate 1 is As a result, an n / p / n reverse junction is formed on the entire surface of the other main surface of the substrate 1, so that the influence is further increased.

【0023】以上詳述した如く、本発明によれば、基板
の一方の主面上に、該基板と同導電型を示す一方の半導
体層を先に形成し、然る後に基板の他方の主面上に逆導
電型を示す他方の半導体層を形成している。従って、得
られる光起電力素子は、基板の両主面上に、夫々互いに
逆導電型を有する半導体層を設けてなる光起電力素子で
あって、側面を含む前記基板の全面に整流接合を備える
こととなる。このことから、上記逆接合によるキャリア
移動の抑制等の悪影響が生じることがなく、光電変換特
性の良好な光起電力素子を再現性良く得ることができる
ものと考えられる。 (実施例)図3は、本発明光起電力素子の製造にプラズ
マCVD装置の装置構成概要図である。同図において、
P,I及びNは夫々第一半導体層、真性半導体層及び第
二半導体層を形成するための反応室となるP室,I室及
びN室である。そして、基板1は図示しない搬送系によ
りこれら各反応室P,I,N間を移動する。
As described in detail above, according to the present invention, one semiconductor layer having the same conductivity type as that of the substrate is formed first on one main surface of the substrate, and then the other semiconductor layer of the substrate is formed. The other semiconductor layer having the opposite conductivity type is formed on the surface. Therefore, the obtained photovoltaic element is a photovoltaic element in which semiconductor layers having opposite conductivity types are provided on both main surfaces of the substrate, and a rectifying junction is formed on the entire surface of the substrate including side surfaces. Will be prepared. From this, it is considered that there is no adverse effect such as suppression of carrier movement due to the reverse junction, and a photovoltaic element having good photoelectric conversion characteristics can be obtained with good reproducibility. (Embodiment) FIG. 3 is a schematic view of the structure of a plasma CVD apparatus for manufacturing a photovoltaic device according to the present invention. In the figure,
P, I, and N are a P chamber, an I chamber, and an N chamber that are reaction chambers for forming the first semiconductor layer, the intrinsic semiconductor layer, and the second semiconductor layer, respectively. Then, the substrate 1 is moved between these reaction chambers P, I, and N by a transfer system (not shown).

【0024】また、P室P,I室I及びN室Nには、夫
々図示しない排気系が独立して設けられると共に、図示
しない反応ガス供給系により各半導体層形成に必要な反
応ガス、即ちP室PにはSiH4, H2,B26が、I
室IにはSiH4及びH2が、N室NにはSiH4及びP
3が、夫々導入される。そして各反応室P,I,N内
にはRF電極P1,I1,N1及びアース電極P2,I
2及びN2が、夫々互いに対向して配置されている。ま
たLは、基板の仕込み及び取出し用の補助室である。
In the P chamber P, the I chamber I, and the N chamber N, an exhaust system (not shown) is independently provided, and a reaction gas required for forming each semiconductor layer by a reaction gas supply system (not shown). In the P chamber P, SiH 4 , H 2 , B 2 H 6 and I
The chamber I contains SiH 4 and H 2 , and the N chamber N contains SiH 4 and P 2
H 3 is introduced respectively. In each of the reaction chambers P, I and N, RF electrodes P1, I1 and N1 and ground electrodes P2 and I are provided.
2 and N2 are arranged opposite to each other. L is an auxiliary chamber for loading and unloading substrates.

【0025】次に、斯かるプラズマCVD装置を用いて
図4に示した光起電力装置を製造する工程について説明
する。
Next, a process of manufacturing the photovoltaic device shown in FIG. 4 using such a plasma CVD device will be described.

【0026】まず、厚み約500μmのn型の単結晶シ
リコンからなる基板1を、他主面側を成膜面として補助
室L内に導入すると共に、10-6Torr程度の真空度
に排気した状態で約250℃の温度に加熱し、上記基板
1に付着した水分等を脱ガスする。
First, the substrate 1 made of n-type single crystal silicon having a thickness of about 500 μm was introduced into the auxiliary chamber L with the other main surface side as a film forming surface, and was evacuated to a vacuum of about 10 −6 Torr. In this state, the substrate 1 is heated to a temperature of about 250 ° C. to degas moisture and the like attached to the substrate 1.

【0027】次いで、基板1を図示しない搬送系により
反応室I内に搬送し、例えば180℃程度の基板温度に
保持すると共に、図示しない原料ガス供給系よりSiH
4及びH2を例えば夫々20SCCMの流量で供給し、図
示しない排気系により反応室内を例えば50mTorr
程度の圧力に保持する。
Next, the substrate 1 is transferred into the reaction chamber I by a transfer system (not shown), and is kept at a substrate temperature of, for example, about 180 ° C., and SiH is supplied from a source gas supply system (not shown).
4 and H 2 are supplied at a flow rate of, for example, 20 SCCM, respectively, and the inside of the reaction chamber is, for example, 50 mTorr by an exhaust system (not shown).
And maintain a pressure of about

【0028】そして、この状態でRF電極I1に50m
W/cm2程度の電力密度で高周波電力を印加し、対向
するRF電極I1及びアース電極I2間でSiH4及び
2ガスのプラズマを生起せしめ、このプラズマ中で生
成されたラジカルを基板1の他主面上に堆積させて、膜
厚約50Åの非晶質シリコンからなる真性半導体層6を
形成する。
In this state, 50 m is applied to the RF electrode I1.
High frequency power is applied at a power density of about W / cm 2 to generate plasma of SiH 4 and H 2 gas between the opposing RF electrode I1 and ground electrode I2, and radicals generated in this plasma are An intrinsic semiconductor layer 6 made of amorphous silicon and having a thickness of about 50 ° is deposited on the other main surface.

【0029】次いで、RF電極I1に印加していた高周
波電力の供給及び反応室I内へのSiH4ガスの供給を
停止すると共に図示しない排気系により反応室I内を1
-7Torr程度の真空度にまで排気し、図示しない搬
送系により基板1をn室N内に搬送する。
Then, the supply of the high-frequency power applied to the RF electrode I1 and the supply of the SiH 4 gas into the reaction chamber I are stopped, and the inside of the reaction chamber I is released by an exhaust system (not shown).
The substrate 1 is evacuated to a degree of vacuum of about 0 -7 Torr, and the substrate 1 is transferred into the n chamber N by a transfer system (not shown).

【0030】そして、該n室N内において基板を例えば
180℃程度の基板温度に保持すると共に、図示しない
原料ガス供給系よりSiH4及びPH3ガスを例えば50
SCCMづつ供給し、図示しない排気系により反応室内
を例えば200mTorr程度の圧力に保持する。
In the n chamber N, the substrate is kept at a substrate temperature of, for example, about 180 ° C., and a SiH 4 gas and a PH 3 gas are supplied, for example, by a source gas supply system (not shown).
SCCM is supplied, and the reaction chamber is maintained at a pressure of, for example, about 200 mTorr by an exhaust system (not shown).

【0031】そして、この状態でRF電極N1に50m
W/cm2程度の電力密度で高周波電力を印加し、対向
するRF電極N1及びアース電極N2間でSiH4及びP
3ガスのプラズマを生起せしめ、このプラズマ中で生
成されたラジカルを真性半導体層6上に堆積させて、膜
厚約200Åのn型の非晶質シリコンからなる第二半導
体層7を形成する。
In this state, 50 m is applied to the RF electrode N1.
The RF power is applied at a W / cm 2 about the power density, SiH between RF electrodes N1 and the grounding electrode N 2 facing 4 and P
A plasma of H 3 gas is generated, and radicals generated in the plasma are deposited on the intrinsic semiconductor layer 6 to form a second semiconductor layer 7 of n-type amorphous silicon having a thickness of about 200 °. .

【0032】次いで、RF電極N1に印加していた高周
波電力の供給及びn室N内へのSiH4及びPH3ガス
の供給を停止すると共に図示しない排気系によりn室N
内を10-7Torr程度の真空度にまで排気し、図示し
ない搬送系により基板1を補助室Lに搬送する。
Next, the supply of the high-frequency power applied to the RF electrode N1 and the supply of the SiH4 and PH3 gases into the n-chamber N are stopped, and the n-chamber N is supplied by an exhaust system (not shown).
The inside is evacuated to a degree of vacuum of about 10 −7 Torr, and the substrate 1 is transferred to the auxiliary chamber L by a transfer system (not shown).

【0033】そして、該補助室L内において基板1の温
度を降温させた後に基板1を取出す。以上の工程によ
り、基板の他主面上に、真性半導体層6及び第二半導体
層7が積層形成されることとなる。
Then, after lowering the temperature of the substrate 1 in the auxiliary chamber L, the substrate 1 is taken out. Through the above steps, the intrinsic semiconductor layer 6 and the second semiconductor layer 7 are laminated on the other main surface of the substrate.

【0034】次いで、他主面上に真性半導体層6及び第
二半導体層7が積層形成された基板1の一主面側を成膜
面として、再度補助室L内に導入する。
Next, the substrate 1 on which the intrinsic semiconductor layer 6 and the second semiconductor layer 7 are laminated on the other principal surface is introduced into the auxiliary chamber L again with the one principal surface side as a film formation surface.

【0035】そして、10-6Torr程度の真空度に排
気した状態で約250℃の温度で加熱し、上記基板1に
付着した水分等を脱ガスする。
Then, the substrate 1 is heated at a temperature of about 250 ° C. in a state of being evacuated to a degree of vacuum of about 10 −6 Torr, and the moisture and the like adhering to the substrate 1 are degassed.

【0036】次いで、基板1を図示しない搬送系により
反応室I内に搬送し、例えば180℃程度の基板温度に
保持すると共に、図示しない原料ガス供給系よりSiH
4及びH2を例えば夫々20SCCMの流量で供給し、図
示しない排気系により反応室内を例えば50mTorr
程度の圧力に保持する。
Next, the substrate 1 is transferred into the reaction chamber I by a transfer system (not shown), and is kept at a substrate temperature of, for example, about 180 ° C., and SiH is supplied from a source gas supply system (not shown).
4 and H 2 are supplied at a flow rate of, for example, 20 SCCM, respectively, and the inside of the reaction chamber is, for example, 50 mTorr by an exhaust system (not shown).
And maintain a pressure of about

【0037】そして、この状態でRF電極I1に50m
W/cm2程度の電力密度で高周波電力を印加し、対向
するRF電極I1及びアース電極I2間でSiH4及び
2ガスのプラズマを生起せしめ、このプラズマ中で生
成されたラジカルを基板1の一主面上に堆積させて、膜
厚約50Åの非晶質シリコンからなる真性半導体層2を
形成する。
In this state, 50 m is applied to the RF electrode I1.
High frequency power is applied at a power density of about W / cm 2 to generate plasma of SiH 4 and H 2 gas between the opposing RF electrode I1 and ground electrode I2, and radicals generated in this plasma are An intrinsic semiconductor layer 2 made of amorphous silicon and having a thickness of about 50 ° is deposited on one main surface.

【0038】次いで、RF電極I1に印加していた高周
波電力の供給及び反応室I内へのSiH4ガスの供給を
停止すると共に図示しない排気系により反応室I内を1
-7Torr程度の真空度にまで排気し、図示しない搬
送系により基板1をP室P内に搬送する。
Next, the supply of the high-frequency power applied to the RF electrode I1 and the supply of the SiH 4 gas into the reaction chamber I are stopped, and the inside of the reaction chamber I is reduced to 1 by an exhaust system (not shown).
Evacuation is performed to a degree of vacuum of about 0 -7 Torr, and the substrate 1 is transferred into the P chamber P by a transfer system (not shown).

【0039】そして、該P室P内において基板を例えば
180℃程度の基板温度に保持すると共に、図示しない
原料ガス供給系よりSiH4, B26及びH2ガスを例
えば10SCCM, 100SCCM,100SCCM
づつ供給し、図示しない排気系により反応室内を例えば
200mTorr程度の圧力に保持する。尚、B26
スはH2で1000ppmに希釈されたものを用いた。
In the P chamber P, the substrate is maintained at a substrate temperature of, for example, about 180 ° C., and SiH 4 , B 2 H 6, and H 2 gases are supplied from a source gas supply system (not shown) to, for example, 10 SCCM, 100 SCCM, 100 SCCM.
The reaction chamber is maintained at a pressure of, for example, about 200 mTorr by an exhaust system (not shown). The B 2 H 6 gas used was diluted to 1000 ppm with H 2 .

【0040】そして、この状態でRF電極N1に50m
W/cm2程度の電力密度で高周波電力を印加し、対向
するRF電極N1及びアース電極N2間でSiH4, B
26及びH2ガスのプラズマを生起せしめ、このプラズ
マ中で生成されたラジカルを真性半導体層2上に堆積さ
せて、膜厚約200Åのp型の非晶質シリコンからなる
第一半導体層3を形成する。
In this state, 50 m is applied to the RF electrode N1.
High frequency power is applied at a power density of about W / cm 2 , and SiH 4 , B is applied between the opposing RF electrode N1 and ground electrode N2.
A plasma of 2 H 6 and H 2 gas is generated, and radicals generated in the plasma are deposited on the intrinsic semiconductor layer 2 to form a first semiconductor layer made of p-type amorphous silicon having a thickness of about 200 °. Form 3

【0041】次いで、RF電極N1に印加していた高周
波電力の供給及びp室P内へのSiH4, B26及びH
2ガスの供給を停止すると共に図示しない排気系により
p室P内を10-7Torr程度の真空度にまで排気し、
図示しない搬送系により基板1を補助室Lに搬送する。
Next, the supply of the high-frequency power applied to the RF electrode N1 and the introduction of SiH 4 , B 2 H 6 and H
(2) The supply of gas is stopped, and the inside of the p chamber P is evacuated to a degree of vacuum of about 10 −7 Torr by an exhaust system (not shown).
The substrate 1 is transported to the auxiliary chamber L by a transport system (not shown).

【0042】そして、該補助室L内において基板1の温
度を降温させた後に基板1を取出す。以上の工程によ
り、基板の一主面上に真性半導体層2及び第一半導体層
3が、また他主面上に真性半導体層6及び第二半導体層
7が積層形成されることとなる。
Then, the substrate 1 is taken out after the temperature of the substrate 1 is lowered in the auxiliary chamber L. Through the above steps, the intrinsic semiconductor layer 2 and the first semiconductor layer 3 are formed on one main surface of the substrate, and the intrinsic semiconductor layer 6 and the second semiconductor layer 7 are formed on the other main surface.

【0043】そして、スパッタ法によりITOからなる
膜厚700Å程度の透光性導電膜4及び8を夫々第一半
導体層3、第二半導体層7上に形成し、次いで該透光性
導電膜4,8上にスクリーン印刷法を用いてAgからな
る櫛型状の集電極5,9を形成し、図4に示した構造の
光起電力素子を完成する。
Then, light-transmitting conductive films 4 and 8 made of ITO and having a thickness of about 700 ° are formed on the first semiconductor layer 3 and the second semiconductor layer 7 by sputtering, respectively. , 8 are formed by screen printing to form comb-shaped collector electrodes 5 and 9 made of Ag to complete the photovoltaic element having the structure shown in FIG.

【0044】尚、この時前述した通り、基板の側面を含
んで両主面上における周端部に、真性半導体層2、6、
第一半導体層3及び第二半導体層7の積層体が形成され
ることとなり、この部分で第一半導体層3及び第二半導
体層7の短絡を生じる可能性がある。これを防止するた
めには、基板の一主面上或いは他主面上における周端部
或いは側面において、接合分離のための分離溝を設けれ
ば良い。
At this time, as described above, the intrinsic semiconductor layers 2, 6, and
A laminate of the first semiconductor layer 3 and the second semiconductor layer 7 is formed, and there is a possibility that the first semiconductor layer 3 and the second semiconductor layer 7 may be short-circuited at this portion. In order to prevent this, a separation groove for joining and separating may be provided on the peripheral end or side surface on one main surface or the other main surface of the substrate.

【0045】以上の製造方法を用いて図4の構造の光起
電力素子を20個形成し、その光電変換特性を測定し
た。また比較のため、基板1の一主面上に先に真性半導
体層2及び第一半導体層3を形成し、次いで他主面上に
真性半導体層6及び第二半導体層7を形成する順序で2
0個の光起電力素子を製造し、その光電変換特性を測定
した。
Using the above manufacturing method, 20 photovoltaic elements having the structure shown in FIG. 4 were formed, and their photoelectric conversion characteristics were measured. For comparison, the order in which the intrinsic semiconductor layer 2 and the first semiconductor layer 3 are formed first on one main surface of the substrate 1, and then the intrinsic semiconductor layer 6 and the second semiconductor layer 7 are formed on the other main surface. 2
Zero photovoltaic elements were manufactured, and their photoelectric conversion characteristics were measured.

【0046】表1に本実施例と比較例の光起電力素子の
光電変換特性をあわせて示す。尚、同表において、光電
変換特性の各パラメータは夫々20個の光起電力素子の
平均値であり、本実施例による値を1とした相対値で示
している。
Table 1 also shows the photoelectric conversion characteristics of the photovoltaic devices of this embodiment and the comparative example. In the table, each parameter of the photoelectric conversion characteristic is an average value of 20 photovoltaic elements, and is shown as a relative value where the value according to the present embodiment is 1.

【0047】[0047]

【表1】 [Table 1]

【0048】同表から明らかに、本実施例により製造し
た光起電力装置の方が各パラメータとも良好な値を示
し、変換効率で18%程度も向上した値が得られた。
As is clear from the table, the photovoltaic device manufactured according to the present example exhibited better values for each parameter, and a value improved by about 18% in conversion efficiency was obtained.

【0049】尚、上述した実施例においては真性半導体
層2,6を備えるものについて説明したが、これに限ら
ず真性半導体層2,6を備えないものについても本発明
は適用することができる。
In the above-described embodiment, the semiconductor device having the intrinsic semiconductor layers 2 and 6 has been described. However, the present invention is not limited to this, and the present invention can be applied to the semiconductor device without the intrinsic semiconductor layers 2 and 6.

【0050】但し、特開平5−102504号に開示し
た如く、非晶質もしくは微結晶からなる第一及び第二半
導体層3,7と基板1との間の界面特性を良好なものと
するために、約250Å以下の膜厚を有する真性半導体
層を備えることが好ましい。また、以上の説明において
は、基板1としてn型を有する基板を用いたが、p型を
有する基板を用いた光起電力素子についても本発明を適
用することがでることは言うまでもない。
However, as disclosed in Japanese Patent Application Laid-Open No. 5-102504, in order to improve the interface characteristics between the first and second semiconductor layers 3 and 7 made of amorphous or microcrystal and the substrate 1. Preferably, an intrinsic semiconductor layer having a thickness of about 250 ° or less is provided. In the above description, a substrate having n-type is used as the substrate 1. However, it is needless to say that the present invention can be applied to a photovoltaic element using a substrate having p-type.

【0051】[0051]

【発明の効果】以上説明した如く、本発明によれば、基
板の一方の主面上に、該基板と同導電型を示す一方の半
導体層を先に形成し、然る後に基板の他方の主面上に逆
導電型を示す他方の半導体層を形成している。従って、
得られる光起電力素子は、基板の両主面上に、夫々互い
に逆導電型を有する半導体層を設けてなる光起電力素子
であって、側面を含む前記基板の全面に整流接合を備え
ることとなる。このことから、上記逆接合によるキャリ
ア移動の抑制等の悪影響が生じることがなく、光電変換
特性の良好な光起電力素子を再現性良く得ることができ
るものと考えられる。
As described above, according to the present invention, one semiconductor layer having the same conductivity type as that of the substrate is first formed on one main surface of the substrate, and then the other semiconductor layer of the substrate is formed. The other semiconductor layer having the opposite conductivity type is formed on the main surface. Therefore,
The obtained photovoltaic element is a photovoltaic element in which semiconductor layers having opposite conductivity types are provided on both main surfaces of the substrate, and a rectifying junction is provided on the entire surface of the substrate including side surfaces. Becomes From this, it is considered that there is no adverse effect such as suppression of carrier movement due to the reverse junction, and a photovoltaic element having good photoelectric conversion characteristics can be obtained with good reproducibility.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明製造方法を説明するための工程別素子構
造図である。
FIG. 1 is an element structure diagram for each step for explaining a manufacturing method of the present invention.

【図2】本発明の効果を説明するための説明図であ
る。。
FIG. 2 is an explanatory diagram for explaining an effect of the present invention. .

【図3】プラズマCVD装置の装置構成概要図である。FIG. 3 is a schematic diagram illustrating the configuration of a plasma CVD apparatus.

【図4】従来の光起電力素子の素子構造断面図である。FIG. 4 is a sectional view of an element structure of a conventional photovoltaic element.

【符号の説明】[Explanation of symbols]

1…基板、2,6…真性半導体層、3…第一半導体層、
4、8…透光性導電膜、5,9…集電極、7…第二半導
体層
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2, 6 ... Intrinsic semiconductor layer, 3 ... First semiconductor layer,
4, 8: translucent conductive film, 5, 9: collecting electrode, 7: second semiconductor layer

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 基板の両主面上に、夫々互いに逆導電型
を有する半導体層を設けてなる光起電力素子であって、 側面を含む前記基板の全面に整流接合を備えたことを特
徴とする光起電力素子。
1. A photovoltaic element comprising semiconductor layers having opposite conductivity types on both main surfaces of a substrate, wherein a rectifying junction is provided on the entire surface of the substrate including side surfaces. Photovoltaic element.
【請求項2】 前記基板が結晶系半導体からなり、前記
半導体層が共に非晶質もしくは微結晶半導体からなるこ
とを特徴とする請求項1記載の光起電力素子。
2. The photovoltaic device according to claim 1, wherein said substrate is made of a crystalline semiconductor, and said semiconductor layers are both made of an amorphous or microcrystalline semiconductor.
【請求項3】 前記基板の両主面と前記半導体層との間
に、非晶質もしくは微結晶半導体からなる真性半導体層
を介在せしめたことを特徴とする請求項2記載の光起電
力素子。
3. The photovoltaic device according to claim 2, wherein an intrinsic semiconductor layer made of an amorphous or microcrystalline semiconductor is interposed between both principal surfaces of said substrate and said semiconductor layer. .
【請求項4】 基板の両主面上に、互いに逆導電型を有
する半導体層を備えてなる光起電力素子の製造方法であ
って、 前記基板の一方の主面上に、前記半導体層のうち前記基
板と同導電型を示す一方の半導体層を形成した後に、前
記基板の他方の主面上に他方の半導体層を形成すること
を特徴とする光起電力素子の製造方法。
4. A method for manufacturing a photovoltaic element comprising: semiconductor layers having opposite conductivity types on both main surfaces of a substrate, wherein the semiconductor layer is provided on one main surface of the substrate. Forming a semiconductor layer having the same conductivity type as that of the substrate, and then forming the other semiconductor layer on the other main surface of the substrate.
【請求項5】 前記基板が結晶系半導体からなり、前記
半導体層が非晶質もしくは微結晶半導体からなることを
特徴とする請求項4記載の光起電力素子の製造方法。
5. The method according to claim 4, wherein the substrate is made of a crystalline semiconductor, and the semiconductor layer is made of an amorphous or microcrystalline semiconductor.
【請求項6】 前記基板と前記半導体層との間に、非晶
質もしくは微結晶半導体からなる真性半導体層を形成す
る工程を備えることを特徴とする請求項5記載の光起電
力素子の製造方法。
6. The method according to claim 5, further comprising the step of forming an intrinsic semiconductor layer made of an amorphous or microcrystalline semiconductor between the substrate and the semiconductor layer. Method.
JP05344798A 1998-03-05 1998-03-05 Photovoltaic element and manufacturing method thereof Expired - Lifetime JP3679598B2 (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
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WO2011125861A1 (en) 2010-03-31 2011-10-13 三洋電機株式会社 Method for manufacturing solar cell, and solar cell
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