JPH11249930A - System verification method and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily verify a system with high debugging performance by executing the simulation or emulation at a desired time based on the stored data and specifying a trouble of the system. SOLUTION: A data storage mechanism 17 which stores the contents of a storage element necessary for the rerun is previously added to a model (9), the S/E(simulation/emulation) is executed (10) and the information on the storage element is stored in the mechanism 17 at each fixed time. Then the S/E result is checked (11). If the S/E result is not correct, a time (t) when a trouble occurred is specified and the data at the time Ti preceding the stored time (t) are loaded into an S/E model (18). Then the S/E is started again at the time Ti (19), and the trouble area is specified by the detailed check of the signal value, etc. (15)., Thereafter, the trouble area is corrected (16) and the S/E is carried on again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system verification method and a verification apparatus based on simulation / emulation, and more particularly to a verification method and a verification apparatus for a system (LSI) including hardware and application software.

[0002]

2. Description of the Related Art A system (LSI) usually includes a CPU.
(Central Processing Unit), memory, and peripheral hardware {ASIC: Application Specific IC}. In these system designs, it is necessary to simultaneously verify the hardware portion and application software operating on the CPU for system verification. In general, two methods, a simulation method and an emulation method, are used for system verification, but each has the following advantages and disadvantages.

(1) Simulation method The simulation method is an HDL (Hardware Description)
This is a method in which the whole system is modeled by a programming language such as Ction Language (hardware description language) or C, and the system is verified by simulation on a computer (EWS: Engineering Work Station, personal computer, etc.).

FIG. 10 is a schematic configuration diagram for explaining a simulation method. In the figure, reference numeral 1 denotes a computer for executing a simulation. On this computer 1, a CPU model 2, a memory model 3, and hardware ( ASIC etc.) Model 4 operates.

This simulation method has the following features (advantages / disadvantages). (Advantages) All software is verified by simulation using a model realized on a computer.
The operation of all signals in the system can be observed, the execution can be stopped at an arbitrary time, the execution of steps can be performed, and the like, flexible verification can be performed, and debugging (specifying / correcting a defective portion) becomes easy. (Disadvantages) It takes a huge amount of execution time to perform all verifications by computer simulation.

(2) Emulation (prototyping) system An emulation system is a real CPU chip (or IC).
E: In-Circuit Emulator), real parts (memory, etc.), FP
This is a method in which an ASIC part or the like implemented by a GA (Field Programmable Gate Array) or the like is mounted (prototyping) on a board, and system verification is performed by emulation.

FIG. 11 is a diagram for explaining the emulation method. In the figure, reference numeral 5 denotes a board for executing the emulation.
PU chip (or ICE) 6, real parts (memory, etc.) 7,
An ASIC (FPGA) 8 is mounted.

This emulation system has the following features (advantages / disadvantages). (Advantage) Since the verification is performed by emulation using real parts, the execution time is very short as compared with the simulation method. (Disadvantages) Since system verification is performed by hardware using emulation, observation of internal signals is limited, and execution cannot be stopped at an arbitrary time. Therefore, flexible verification is impossible, and debugging is extremely difficult. is there.

A flow chart of system verification by simulation / emulation is generally shown in FIG.
It becomes as shown in. In FIG. 12, Step 9 represents the start of system verification, and prepares a model for simulation / emulation as shown in FIG. 10 or FIG. After that, simulation / emulation is executed in Step 10, and it is checked in Step 11 whether the simulation / emulation result is correct. St
If the result is correct at ep12, the process proceeds to Step 13 to end the system verification. If not correct, proceed to Step 14.
In Step 14, the simulation / emulation is re-executed from the beginning up to a time shortly before the time at which the failure occurred in order to identify the location of the failure. Next, in Step 15, a defective portion is specified by executing steps, checking signal values in detail, and the like. Thereafter, in Step 16, a defective portion of the system design is corrected, and the process returns to Step 10 again to execute the simulation / emulation again.

[0010]

In the above-described conventional system verification flow using simulation / emulation, the simulation / emulation method has the disadvantages, and the simulation method requires re-execution up to the error point in step 14 in the simulation method. Time becomes very long.
5 has a problem that it is difficult to identify a defective portion.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and utilizes the advantages of each of the simulation and emulation methods to provide a high-speed system verification method and a high-performance debug apparatus. I will provide a.

[0012]

The invention of a system verification method according to claim 1 is a system verification method for verifying a system including hardware and software by simulation or emulation, and verifies the system by simulation or emulation model. And storing the contents of the storage elements in the system necessary for re-execution of the system in the data storage mechanism at each predetermined time during the execution of the simulation or emulation, and simulating or emulating the data stored in the data storage mechanism. And executing a simulation or emulation from a desired time T _i to specify a defective portion of the system.

According to a second aspect of the present invention, there is provided a system verification method, comprising the steps of: verifying a system by using an emulation model;
Loads and storing the contents of the system memory element needed to re-run the system in the data storage mechanism, the data stored in the data storage mechanism to the simulation model, running the simulation from a desired time T _i,
And a step of identifying a defective portion of the system.

[0014] invention the system verification method of claim 3 wherein loads after identifying the problem location system, the data of the time T _k for the system to work properly from a data storage mechanism within system memory element, this time It is characterized in that the system is re-verified from T _k .

According to a fourth aspect of the present invention, a storage element (SFF) having a scan function is connected to each storage element (FF, etc.) in the system, and the storage elements (SFF, etc.) for scanning are connected continuously. (Scan chain configuration) and scan the contents of the storage elements (FF etc.) in the system necessary for re-execution of the system.
The data is continuously stored in the data storage mechanism through the data storage device.

According to a fifth aspect of the present invention, when the contents of the storage elements in the system are stored in the data storage mechanism, the contents are advanced to a time suitable for storage (a break in a bus cycle or a break in an instruction cycle). After that, it is automatically saved.

According to a sixth aspect of the present invention, when the contents of the storage elements in the system are stored in the data storage mechanism, the data is subjected to data compression processing and stored.

According to a seventh aspect of the present invention, there is provided a data storage mechanism for storing contents of a storage element in a system necessary for re-execution of a system at a predetermined time during execution of simulation or emulation, and a data storage mechanism. Load the data saved in the storage element in the system,
Means for restarting simulation or emulation from a desired time.

According to an eighth aspect of the present invention, there is provided an emulation model for verifying a system, and a data storage mechanism for storing the contents of a storage element in the system necessary for re-execution of the system at predetermined times during execution of the emulation. And load the data saved in the above saving mechanism,
And a simulation model for executing a simulation from a desired time T _i to specify a failure point of the system.

According to a ninth aspect of the present invention, a storage element having a scan function is connected to the storage element in the system, and the contents of the storage element in the system required for re-execution of the system are stored in the storage element for scanning. Through a data storage mechanism.

According to a tenth aspect of the present invention, there is provided a system verification device including a data compression mechanism for performing data compression processing on the contents of the storage elements in the system and storing the data in a data storage mechanism.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a diagram showing a verification flow of the system verification apparatus according to Embodiment 1 of the present invention.

In the figure, Step 9 indicates the start of system verification, and prepares a model for simulation / emulation as shown in FIG. 10 or FIG. On this occasion,
The contents of storage elements (registers, memories, etc.) related to hardware / software in the system necessary for re-execution are stored at regular time intervals (Step 19) so that re-execution from an intermediate time is possible in a later process (Step 19). (For example, every 1,000 clocks)
A data saving mechanism 17 for saving (dumping the contents) to the model is added to the model. Thus, if the simulation / emulation is performed in Step 10, the storage element (memory / register) information at a certain time is stored in the data storage mechanism 1
7 is stored. Then, in Step 11, it is checked whether the simulation / emulation result is correct. If the result is correct in Step 12, the process goes to Step 13 to end the system verification. Step 18 if not correct
Proceed to.

In Step 18, the time t at which the failure point has occurred (possibly) is first specified, and the time T _i (T _i <t ≦ T _{i + 1)} before the time t stored by the storage unit 17 is specified. ) Is loaded into the simulation / emulation model {return to storage element (memory / register)}. In order to identify the defect in Step 19,
Resume the simulation / emulation from time T _i. Next, in Step 15, a defective part is specified by executing a step, checking a signal value in detail, and the like. Hereafter, Step
Step 16 corrects the faulty part of the system and repeats Step 1
Return to 0 and re-execute simulation / emulation.

[0025] In FIG. 1, after correcting the problem location in Step 16, when it resumes execution at the first back to Step10, until a certain time T _k is known to be working properly, the Step10 load the data of time T _k from the storage means 17 in the stage, it is also possible to resume execution of the simulation / emulation from the time T _k.

In addition, when a storage means for performing a dump process at fixed time intervals is added to the simulation / emulation model, if the fixed time interval for dumping can be easily changed by changing parameters or the like, system verification can be performed more flexibly. It can be performed.

As described above, according to the first embodiment, since the simulation / emulation can be restarted from an appropriate time if necessary, the execution time required for debugging (specifying and correcting a defective portion) is reduced. be able to.

In particular, in the case of a simulation that can be carried out at an early stage of the design unlike emulation, it is possible to greatly reduce the time required for debugging, which requires a very long execution time.

In the present embodiment, not only the debugging efficiency of the software of the system is improved, but also the debugging efficiency is improved from the viewpoint of both software and hardware.

Embodiment 2 FIG. FIG. 2 is a diagram showing a verification flow of the system verification device according to the second embodiment, and FIG. 3 is a schematic diagram for explaining control of the system verification device.

In FIG. 2, Step 9 indicates the start of system verification, and prepares a model for emulation as shown in FIG. At this time, a data storage mechanism 17 for dumping the contents of the storage elements (registers, memories, etc.) in the system at regular time intervals (for example, every 1,000 clocks) described in the first embodiment is added to the model, and the dumping is performed. The dump format to be saved is shared between emulation and simulation so that the obtained information can be loaded into the simulation model. Next, emulation is performed in Step 20, and the memory / register information for each fixed time is dumped to the data storage mechanism 17. Then, Step 11
Check if the emulation result is correct. If the emulation result is correct in Step 12, Step
Proceed to 13 to end the system verification. St if not correct
Proceed to ep21.

In Step 21, the time t at which the failure point occurs (possibly) is first specified, and the data saving mechanism 17
At the time T _i (T _i <t ≦ T
_{i + 1} ) is loaded into the simulation model as shown in FIG. 10 {memory element (memory / register)
Return to｝. In Step 22, in order to identify the trouble spot,
Resume the simulation from the time T _i. Next, Step
At 15, a defective portion is identified by executing a step, checking a signal value in detail, and the like. Thereafter, in Step 16, a defective portion of the system design is corrected, and the process returns to Step 20 again to execute the emulation again.

[0033] In FIG. 2, after correcting the problem location in Step 16, has been to resume execution at the first back to Step 20, if it is known that to operate normally until the time T _k is the Step 20 load the data of time T _k from the data storage mechanism 17 in the stage, it is also possible to resume execution at the time T _k. FIG. 3 schematically shows this system verification.

As described above, according to this embodiment,
Since the simulation result can be taken to the simulation device at the halfway time obtained by the emulation and the simulation can be resumed from that time, both the high-speed emulation and the ease of debugging (specifying and correcting defects) of the simulation can be performed. You can take advantage of the advantages.

Embodiment 3 FIG. FIG. 4 is a diagram schematically illustrating a logic circuit of a general LSI (large-scale integrated circuit). Generally, an LSI is composed of a combinational circuit 23 and a flip-flop (F
F) and a storage element 24 such as a latch, and a process is performed in synchronization with a clock (clk) 27. In addition,
(Data_in_1 to n) 25 is a system input terminal,
(Data_out_1 to m) 26 represents a system output terminal.

In the third embodiment of the present invention, before the system verification, the LSI circuit of FIG. 4 is converted into a system verification circuit as shown in FIG. 5 (this conversion process can be automated by a program). In this circuit conversion (FIG. 5), a storage element 28 having a scan function (a scan flip-flop in this example) is provided for each storage element 24 (FF in this example) necessary for re-executing the simulation / emulation. Then, the output terminal Q of each FF 24 and the data input terminal D of each SFF 28 are connected. Next, a scan mode signal (scan) is applied to the scan mode terminal SM and the clock terminal T of all SFFs 28, respectively.
_Mode) 31 and the clock signal (clk) 27 are connected. Further, all the SFFs 28 are sequentially connected by a scan chain. A scan chain is, as shown in FIG.
From the scan-in signal (scan_in) 29 to the scan-out signal (scan_out) 30, each S
This means that all SFFs are continuously connected via the scan-in terminal SI and the output terminal Q of the FF.

In the circuit simulation / emulation of FIG. 5, the scan mode signal (scan_mod)
e) Regardless of the value of 31, (data_in) terminal 2
5 to the (data_out) terminal 26 is exactly the same as the original circuit (the circuit of FIG. 4). On the other hand, when it is desired to dump the contents of the storage element required for re-execution at time t, the following procedure is performed (see FIG. 6).

(1) Until the time (t + 1), the value of the scan mode signal (scan_mode) 31 is set to “0” (invalid). As a result, each SFF 28 has its D
The value one clock before the previous FF 24 connected to the terminal is always stored (see arrow 32). Therefore, the time (t +
In 1), each SFF 28 stores the contents of each FF at time t.

(2) The value of the scan mode signal (scan_mode) 31 is changed from “0” to “1” (valid: enable) between the time (t + 1) and the time (t + 2). Thus, after time (t + 2), the SFF enters the scan mode, and the value of the SFF becomes independent of the value of the FF. In the scan mode, the data of the SFF is shifted bit by bit in the order of the scan chain from the scan-in signal (scan_in) 29 to the scan-out signal (scan_out) 30 in synchronization with the clock.

(3) After time (t + 2), data is sequentially extracted from the scan-out signal (scan_out) 30 in synchronization with the clock, and stored in the above-mentioned data storage mechanism by the number of SFFs 28 connected to the scan chain. In the example of FIG. 5, since the four SFFs 28 are connected to the scan chain, the scan-out signal (sca) is output for four clocks from time (t + 2) (until time t + 5).
n_out) 30 will be saved.

(4) After the above process (3) is completed, the scan mode is ended by returning the value of the scan mode signal (scan_mode) 31 to "0" (invalid) again. Of each FF 24 is
It will be stored in F28. In the example of FIG. 5, (3)
The value of the scan mode signal (scan_mode) 31 may be returned to “0” (invalid) after the time (t + 5) at which the processing of (1) is completed.

(5) When the dump process is performed at regular time intervals (for example, at every 1,000 times), the above (1) to (4) are performed at each time.
The process of (4) is repeated. However, as a condition here, it is necessary to set the time cycle (for example, 1,000 clocks) of the dump processing to be larger than the number of storage elements (FFs or the like) to be stored. If this time cycle is small,
New data comes into the verification storage element (SFF) before the dump processing ends.

Although the flip-flop FF is used as the storage element in the above-described example, it is also possible to dump a storage element such as a latch or a memory.

In this example, the circuit is constituted by one scan chain. However, a plurality of scan chains can be formed.

As described above, according to this embodiment,
By utilizing the scan design method, there is no execution time penalty associated with the dump processing, and a small number of external terminals (scan_in29, scan_out30, scana
Simulation / emulation can be performed only by increasing n_mode 31). The process of inserting a scan circuit (FIG. 5) is only for system verification, and the actual design (implementation) uses the original circuit (FIG. 4), so there is no hardware penalty in the design. .

Embodiment 4 FIG. 7 and 8 are views showing a dump test bench for explaining the fourth embodiment.

The number of storage elements required for re-execution from the middle differs depending on the system. However, even in a single system, the number of storage elements can be considered at the break of a bus cycle or the break of an instruction (eg, a read instruction / write instruction) cycle. In many cases, the number of storage elements to be stored may be small.

FIG. 7 is a diagram showing a normal dump bench test used to implement the first embodiment. FIG.
, The variable “Last” represents the last time of the simulation (emulation), and the variable “Inter”.
"val" indicates a time interval for dumping. For in FIG.
The sentence indicates that "from time 0 to the last time" Last ", information on storage elements necessary for re-execution is dumped at each time interval" Interval "".

FIG. 8 is a diagram showing a dump bench test for realizing the fourth embodiment. In the bench test of FIG. 7, the dump is performed exactly for each “Interval”, but in FIG. 8, a time suitable for dumping (for example,
After advancing the time until a bus cycle break or an instruction cycle break), a dump process is executed. This conditional statement (i
f statement) in the condition "whether the time is suitable for dumping"
Can be described as a condition by monitoring the appropriate signal in the system. That is, the dumping time is not a clock time designated in advance, but is automatically corrected to a time at which information necessary for re-execution, such as a break of a bus cycle or an instruction cycle, which is close to the time, requires as little information as possible.

Although the test bench is described in C language in FIG. 8, it can be described in HDL or the like. Further, the same processing can be described using a statement other than the for statement and the if statement.

As described above, according to this embodiment,
Since the dump processing can be executed after automatically proceeding to a time suitable for dumping, the amount of data to be saved can be reduced.

Embodiment 5 FIG. FIG. 9 is a diagram showing a verification flow of the system verification device according to the fifth embodiment.

The fifth embodiment of the present invention is characterized in that a data compression process is performed when data of a storage element necessary for re-execution is stored in a storage mechanism. That is, as shown in FIG. 9, a data compression mechanism 33 is added to the verification flow (FIG. 1) shown in the first embodiment. When storing data of the storage element required for re-execution by the data compression mechanism 33, the data compression mechanism 33 performs a data compression process and then stores the data in the data storage mechanism 1.
Save to 7. This is particularly effective when storing memory data when there are many unused areas or portions where the value is not determined (the value is an undefined value “X”) in the memory (DRAM or the like). For this data compression processing, an existing data compression algorithm can be implemented and used.

In the case of emulation, the data compression processing can be implemented as hardware.

As described above, according to this embodiment,
Since the data of the dump can be automatically compressed and saved,
The amount of data to be saved can be reduced.

[0056]

As described above, according to the first to ninth aspects of the present invention, the simulation / emulation time can be shortened, and the debugging (specifying and correcting a defective portion) of the system verification is improved.

In particular, according to the second or eighth aspect of the present invention, the dump result at an intermediate time obtained by the emulation model can be taken to the simulation model, and the simulation can be resumed from that time. You can take advantage of the advantages of both high speed and easy debugging of simulation.

According to the third or ninth aspect of the present invention, by utilizing the scan design method, there is no execution time penalty associated with the dump processing, and simulation / emulation can be performed only by increasing a small number of external terminals. It can be carried out. Also, there is no hardware penalty in the design.

Further, according to the invention of claim 4 or claim 10, since the dump result can be automatically compressed and stored, the amount of data to be stored can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a verification flow of a system verification device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a verification flow of a system verification device according to a second embodiment.

FIG. 3 is a schematic diagram for explaining control of a system verification device according to a second embodiment.

FIG. 4 is a diagram showing a logic circuit of a general LSI.

FIG. 5 is a diagram showing a configuration of a logic circuit for system verification according to a third embodiment;

FIG. 6 illustrates a flip-flop (F) according to the third embodiment.
FIG. 3F is a diagram showing a change (signal propagation) of the value of the scan flip-flop (SFF).

FIG. 7 is a diagram showing a dump bench test according to the first embodiment.

FIG. 8 is a diagram showing a dump bench test according to the fourth embodiment.

FIG. 9 is a diagram showing a verification flow of the system verification device according to the fifth embodiment.

FIG. 10 is a schematic configuration diagram for explaining a simulation method.

FIG. 11 is a schematic configuration diagram illustrating an emulation method.

FIG. 12 is a diagram showing a system verification flow according to a conventional simulation / emulation method.

[Explanation of symbols]

1. Computer for executing simulation, 2 CPU
Model, 3 memory model, 4 hardware (ASI
C) model, 5 emulation execution board, 6
Real CPU chip (or ICE), 7 real parts (memory, etc.), 8 ASIC (FPGA), 17 data storage mechanism, 24 storage element (FF) in system, 28 storage element for scanning (SFF), 33 data compression mechanism.

Claims (10)

[Claims] 1. A system verification method for verifying a system including hardware and software by simulation or emulation, comprising the steps of: verifying a system by simulation or emulation model; time T _i which of and storing the contents of the system memory device required for data storage mechanism to re-execute, load the data stored in the storage mechanism to the simulation or emulation model, desired
Run a simulation or emulation from
A step of identifying a faulty part of the system. 2. A system verification method for verifying a system, comprising the steps of: verifying the system by an emulation model; and storing data of a storage element in the system required for re-execution of the system at predetermined times during execution of the emulation. A system verification method comprising: a step of storing data in a storage mechanism; and a step of loading data stored in the storage mechanism into a simulation model, executing a simulation from a desired time T _i , and identifying a defective portion of the system. 3. After identifying the defective part of the system, the data of the time T _k for the system to work properly loaded into system memory element from the storage mechanism, to perform the revalidation of the system from the time T _k The system verification method according to claim 1 or 2, wherein: 4. A storage element having a scan function is connected to the storage element in the system, and the contents of the storage element in the system necessary for re-execution of the system are continuously stored in the data storage mechanism via the storage element for scanning. The system verification method according to any one of claims 1 to 3, wherein the system verification method is performed. 5. When storing the contents of a storage element in a system in a data storage mechanism, advance to a time suitable for storage.
The system verification method according to claim 1, wherein the system verification is automatically stored. 6. The system according to claim 1, wherein when the contents of the storage elements in the system are saved in the data saving mechanism, the contents are subjected to data compression processing and saved. Method of verification. 7. A system verification device for verifying a system by simulation or emulation, wherein at every predetermined time during execution of simulation or emulation, a data storage mechanism for storing contents of a storage element in the system required for re-execution of the system; Means for loading data stored in the storage mechanism into a storage element in the system and restarting simulation or emulation from a desired time. 8. A system verification device for verifying a system, comprising: an emulation model for verifying the system; and data for storing contents of a storage element in the system required for re-execution of the system at predetermined times during execution of the emulation. a storage mechanism, and load the data stored in the storage mechanism, system verification apparatus and a simulation model to identify the problem location of the system running the simulation from a desired time T _i. 9. A storage element having a scan function is connected to the storage element in the system, and the contents of the storage element in the system necessary for re-execution of the system are continuously stored in the data storage mechanism via the storage element for scanning. 9. The system verification device according to claim 7, wherein the system verification is performed. 10. The system verification apparatus according to claim 7, further comprising a data compression mechanism for performing data compression processing on the contents of the storage elements in the system and storing the data in a data storage mechanism.