JPH11243391A - System for transmitting and receiving atm cell data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simply execute in a small scale a format conversion processing for adding and erasing an overhead. SOLUTION: One byte which is originally used in header error control(HEC) is used for cell overhead information OH and one cell is processed by 53 bytes being the same number as that of a transmission path cell so that the number of cells in one frame is made to be the same as that of the transmission path. Then, control for stuffing and destuffing is not reguired. Since switching is executed through the use of cell overhead information, a high speed switching processing is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM cell data transmission / reception system, and more particularly, to a transmission / reception system based on an ATM transmission system, which has an ATM layer termination and a virtual path (VP) or virtual channel (VC). The present invention relates to an ATM cell data transmitting / receiving system for performing a switch, a receiving device, and a transmitting device.

[0002]

2. Description of the Related Art Conventional cell format conversion is disclosed in
-326726. This conventional cell format conversion will be described with reference to FIGS.

FIG. 14 is a block diagram showing a configuration of a format converter on the input side (hereinafter, referred to as an input format converter). In the figure, the input format converter performs demultiplexing of 8-bit parallel data into 32-bit parallel data.
A DMUX circuit 1, format conversion circuits 2 and 4 for converting the format of data, and a FIFO (Firs
(t In First Out) structure, a speed matching FIFO 3 for matching clock speeds, a 32-8 MUX circuit 5 for multiplexing 32-bit parallel data into 8-bit parallel data, and 1 /
Frequency dividing circuits 6 and 7 and dividing the received clock 10 by 1
A 分 frequency divider circuit 6 that outputs a 分 frequency-divided clock 14,
The system clock 11 is divided to １ ／ divided clock 1
And a 1/4 frequency dividing circuit 7 for outputting the signal 5. The conversion unit receives the received data 8 synchronized with the reception clock 10 and outputs the in-device data 9 synchronized with the system clock 11.

FIG. 15 is a block diagram showing the configuration of a format converter on the output side (hereinafter referred to as an output format converter). In the figure, the output format converter performs demultiplexing of 8-bit parallel data into 32-bit parallel data.
A DMUX circuit 16, format conversion circuits 17 and 19 for converting the format of data, and a speed matching FIFO for matching clock speeds by a FIFO structure
O18 and multiplexing of 32-bit parallel data into 8-bit parallel data 32-8
The frequency of the MUX circuit 20 and the frequency of the system clock 25 are divided into 1
A 含 ん frequency divider 21 outputs a 回路 frequency divided clock, and a ４ frequency divider 22 divides the transmission clock 26 and outputs a ４ frequency clock 30. .
This conversion unit receives the in-device data 23 synchronized with the system clock 25 as input and outputs the transmission data 24 synchronized with the transmission clock 26.

FIG. 16 is a diagram showing the configuration of a device when the format converter shown in FIGS. 14 and 15 is mounted on a cross-connect / switch device.
Referring to FIG. 1, an input format converter 31 is provided on the input side of the apparatus, and an output format converter 3 is provided on the output side of the apparatus.
4 are provided respectively. Then, these conversion units 31
Between the routing information adding unit 32 and the exchange /
A cross connect switch section 33 is provided. That is, FIG. 16 shows the position of each format conversion unit.

Returning to FIG. 14, in such a configuration, the input-side format converter converts the received clock to the system clock, and adds an OH (overhead) byte to the received cell to convert it into a cell in the apparatus. And do.

In FIG. 14, received data 8 is an STM
(Synchronous Transfer Mod
e) Data after termination and data synchronized with the reception clock. First, the received data 8 is parallel-expanded into 32 parallel by the 8-32 DMUX circuit 1 and input to the format conversion circuit 2. The format conversion circuit 2 removes 1 byte of HEC from the cell format of FIG. 17A and converts the cell after the parallel development into the cell format data 12 shown in FIG. 17B. The cell of the data 12 has the speed matching F at the timing synchronized with the reception clock.
The data is written to the IFO 3 and read at a timing synchronized with the system clock 10. The read data 13 is converted by the format conversion circuit 4 into cells having the format shown in FIG. 17C by adding OH bytes and HEC bytes to the cells having the format shown in FIG. 17B. The converted data is output to the subsequent processing unit in the apparatus as 8-parallel data by the 32-8 MUX circuit 5.

During this series of processing, the frame structure of the received data shown in FIG. 18A is converted into the format shown in FIG. In the inside of the device, 0.6 cells per frame are missing due to format conversion. For this reason, the speed difference is absorbed by using a speed matching FIFO. In the figure, the hatched portion is a cell region. In FIG. 3A, 44.4 is included in one frame.
There are cells, and in FIG. 3B, 45 cells exist in one frame.

On the other hand, the format converter on the output side shown in FIG. 15 performs switching from the system clock to the transmission clock, and processing for removing OH bytes from cells in the device and converting the cells into transmission cells.

In FIG. 15, data 23 in the apparatus is data after processing in the apparatus synchronized with the system clock.
The in-device data 23 is first sent by the 8-32 DMUX circuit 16 to 3
Two parallel expansions are performed and the format conversion circuit 17
To enter. The format conversion circuit 17 removes the OH byte and the HEC byte shown in FIG. 19A from the cells after the parallel development, and converts the cells into data 27 in the cell format shown in FIG. 19B. The cell of the data 27 is written into the speed matching FIFO 18 at the timing synchronized with the system clock, and the transmission clock 2
6 is read out at the timing synchronized with 6. The read data 28 is converted into a cell of the format shown in FIG. 19C by adding a HEC byte to the cell of the format shown in FIG. I do. The converted data is 32-8 MUX
The data is output to the signal transmission unit of the device as eight parallel data by the circuit.

During this series of processing, the frame structure of the received data shown in FIG. 20A is converted into the format shown in FIG. On the transmitting side, extra cells of 0.6 cells are generated per frame due to format conversion. For this reason, the speed difference is absorbed by using a speed matching FIFO. In FIG. 20, a hatched portion is a cell region. The same applies to the following drawings.
In FIG. 10A, 45 cells exist in one frame, and in FIG. 10B, 44.4 cells exist in one frame.

In FIG. 7, an input format conversion unit 3
The data 35 received at 1 is added with an OH byte and output to the routing information adding unit 32. The routing information adding unit 32 calculates cell identification information, broadcast instruction information, priority information, and switch output port number from the cell header as shown in FIG.
Write to byte. The data to which the routing information is added is sent to the cross-connect / switch unit 33 by the OH
The switch is performed based on the byte routing information. After the switch output, the output format conversion unit 34
The H bytes are removed, and the data 36 is transmitted.

[0013]

As described above, in the format conversion section, a shortage cell of 0.6 cells on the input side and a surplus cell of 0.6 cells on the output side occur per frame. For this reason, it is necessary to perform stuff control on the input side when the speed matching FIFO falls below the threshold value. On the output side, when the speed matching FIFO becomes full (full state), it is necessary to perform destuff control.

The stuff control and destuff control will be described with reference to FIGS. 22 and 23. FIG. 22 is a block diagram showing a circuit configuration for performing stuff control. In the figure, reference numeral 22a denotes an input format conversion unit, and 22b denotes a switch unit.

The input format conversion unit 22a includes a stuff cell generation circuit 37 for generating a stuff cell, a speed matching FIFO 41, a FIFO vacancy determination circuit 43 for determining whether the FIFO 41 is vacant, a stuff cell 50 and a general cell 51. And a selector 38 for selecting the above. The switch unit 22b includes a cell type determination circuit 39 for determining the type of the cell and a switch buffer 4
0 and a stuff cell discarding circuit 42 for discarding the stuff cell 49.

FIG. 23 is a block diagram showing a circuit configuration for performing destuff control. In the figure, 2
3a is a switch unit, and 23b is an output format conversion unit.

The switch unit 23a includes a destuff cell generator 52 for generating a destuff cell, a switch buffer 56, and a selector 53 for selecting a destuff cell 65 or a general cell 66. . The output format conversion unit 23b includes a cell type determination circuit 54 for determining a cell type, a destuff cell discard circuit 55 for discarding the destuff cell 59, and a speed matching FIFO.
57 and a FIFO for performing a FULL determination of this FIFO
And a FULL determination circuit 58.

The operation of the stuff control will be described with reference to FIG. In the input format converter, the receiving cell 44
Is input to the speed matching FIFO 41.
At this time, when the capacity of the FIFO is determined and it is determined that the capacity is equal to or smaller than the threshold, the FIFO empty signal 45 is output.
In the FIFO empty determination circuit 43, the FIFO empty signal 45
, The cell output INH (inhibit) signal 46
And a stuff cell selection signal 47 is output. Cell output IN
The H signal 46 is detected by the reading unit of the speed matching FIFO 41, and stops the cell reading operation. The stuff cell selection signal 47 is detected by the selector circuit 38, the input cell is switched from the general cell 51 to the stuff cell 50, and the stuff cell generated by the stuff generation circuit 37 is output.

In the switch section, the cell type determination circuit 39 determines the cell type of the input cell. When the cell type is the general cell 48, writing is performed on the switch buffer 40. If the cell type is the stuff cell 49, the writing to the switch buffer is stopped and the stuff cell 49 is output to the stuff cell discarding circuit 42. The stuff cell discarding circuit 42 discards the input stuff cell 49.

Next, the operation of the destuff control will be described with reference to FIG.
In the output format conversion unit, when a general cell is input from the switch unit, the output type conversion unit 5
9 to the speed matching FIFO 57. At this time, when the capacity of the FIFO is determined and the capacity is determined to be equal to or larger than the threshold value, a FIFO FULL signal 62 is output. In the FIFO FULL determination circuit 58, the FIFO
When the FULL signal 62 is received, the cell output INH signal 64
And a destuff cell selection signal 63 to the switch section.

In the switch section, the cell output INH signal 64
Is detected by the switch buffer 56, the output of the general cell 66 is stopped. The destuff cell selection signal 63 is detected by the selector circuit 53, and when the detection is performed, the selector circuit 53 changes the input cells from the general cells 66 to the destuff cells 6
5 and outputs the destuff cell generated by the destuff cell generation circuit 52.

In the interface unit, a cell type judgment circuit 54 judges the cell type of the input cell. When the cell type is the general cell 60, the speed matching FI
The cell is written to the FO 57. When the cell type is the destuff cell 59, the write operation to the speed matching FIFO 57 is stopped, and the destuff cell 59 is output to the destuff cell discarding circuit 55. The destuff cell discarding circuit 55 discards the input destuff cell 59.

Since the conventional cell format conversion is performed as described above, when performing the format conversion for adding OH to the cell, the speed matching FIFO and the stuff,
A destuff control circuit is required. This has the disadvantage that the circuit scale is large and complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to transmit and receive ATM cell data capable of performing simple and small-scale format conversion processing for adding and deleting overhead. Is to provide a system.

[0025]

An ATM cell data transmitting and receiving system according to the present invention is a system for transmitting and receiving received ATM cell data by performing a routing process, wherein the received ATM cell data has a header error. Storage means for storing cell overhead information used for routing in an area where header error control information used for control is to be stored, routing means for performing routing processing on the stored data, and cells of the data after the routing processing Adding means for adding header error control information instead of overhead information.

An ATM cell data receiving apparatus according to the present invention is an ATM cell data receiving apparatus for performing a routing process on received ATM cell data, and stores header error control information used for header error control of the received ATM cell data. It is characterized by including storage means for storing cell overhead information used for routing in an area to be routed, and routing means for performing routing processing on the stored data.

An ATM cell data transmitting apparatus according to the present invention is an ATM cell data transmitting apparatus for performing routing processing on ATM cell data and transmitting the result.
Routing means for performing routing processing on data after cell overhead information used for routing is stored in an area where header error control information used for header error control of TM cell data is to be stored, and cells of the data after the routing processing Adding means for adding header error control information instead of overhead information.

In short, in this system, the HEC
Is used for COH, and one cell is processed with 53 bytes, the same number of bytes as the transmission line cell. As a result, the number of cells in one frame becomes the same as the number of transmission lines, so that stuff and destuff control is not required. In addition, since switching can be performed using COH information, high-speed switching processing can be performed.

[0029]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a cell format in a device used in the ATM cell data transmission / reception system according to the present invention. The present invention solves the above-mentioned drawbacks of the prior art by changing the cell format in the device, as described below.

In the figure, the number of bytes of the cell is 53 bytes, and an OH byte is added at the position of the HEC byte.
The OH byte carries routing information such as cell identification information, broadcast instruction information, priority order information, and switch output port number.

FIG. 2A shows the cell format of the internal data, and FIG. 2B shows the frame structure of the internal data. FIG. 3A shows the cell format of the received data, and FIG. 3B shows the frame configuration of the received data. The cells of the received data shown in FIG. 3A have the same 53 bytes as the cells of the in-apparatus data shown in FIG. 2A in terms of the number of bytes per cell. As described above, since the number of bytes of the received cell is equal to the number of bytes of the cell in the device, the frame configuration of the received data shown in FIG. 3B and the frame of the data in the device shown in FIG. The configuration is the same. Therefore, in the input-side format conversion processing, speed matching is not required.

FIG. 1 shows the structure of the format converter on the input side.
4 (a). Since the speed conversion is not required in the format conversion process, the speed matching FIFO and the stuff control circuit are deleted from the conventional configuration.
For this reason, the input-side format converter can be constituted only by a clock transfer circuit.

FIG. 5A shows the cell format of the transmission data, and FIG. 5B shows the frame configuration of the transmission data. The cell of the in-device data in FIG. 2A has the same number of bytes as the transmission data cell shown in FIG. 5A in the number of bytes per cell. Also, since the number of bytes in the cell in the device and the number of bytes in the transmission cell are the same, the frame configuration of the data in the device shown in FIG. 2B and the frame configuration of the received data shown in FIG. Will be the same.
Therefore, the output format conversion does not require speed matching.

The configuration of the output-side format converter is shown in FIG.
This is shown in (b). Since speed matching is no longer required in the format conversion process, the speed matching FIFO and the destuff control circuit are eliminated from the conventional configuration.
For this reason, the output-side format converter can be constituted only by the clock transfer circuit.

FIG. 6 shows the apparatus configuration and the HEC in each processing unit.
Indicates the function of the (OH) byte. In FIG. 6, reference numeral 67 denotes an input format conversion unit for performing HEC reference for cell synchronization; 68, a routing information addition unit for adding routing information (OH); 69, a cross connect / switch unit for referring to routing information (OH). , 70 are output format converters for adding HEC, 71 is received data,
72 is transmission data.

The function of the HEC (OH) byte in this device will be described with reference to FIG. The received data 71 input to the device is input to the input format
C is referenced, and cell synchronization is established. The next routing information adding unit 68 deletes the HEC information and adds the routing information. The next switch unit 69 refers to the routing information and performs writing to the switch buffer. Finally, the output format converter 70 deletes the routing information, adds the HEC operation value, and outputs it as transmission data 36 to the outside of the device.

As described above, according to the configuration of the present invention, the circuit scale can be reduced and the circuit can be simplified without impairing the functions of the prior art. Hereinafter, more specific examples will be described.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Two embodiments will be described below.

In the first embodiment, the present system
(Synchronous Digital Hier
archy) -based ATM cells in a cross-connect / switch device. This embodiment will be described with reference to FIGS.

FIG. 7A shows an input format conversion section 67.
8A is a block diagram showing a configuration of a routing information adding unit 68, FIG. 9A is a block diagram showing a configuration of a switch unit 69, and FIG. 10A is an output format conversion. FIG. 3 is a block diagram illustrating a configuration of a unit 70.

In FIG. 7 (a), the input format converter receives the received data 78 and terminates the SDH.
A DH termination circuit 73, a cell synchronization circuit 74 for establishing cell synchronization, an error correction circuit 75 for correcting errors in the header,
A descrambling circuit 76 for performing a descrambling process;
It includes a clock transfer circuit 77 that performs clock transfer from the reception clock 80 to the system clock 81 and outputs data 79 in the device.

In FIG. 8A, a routing information adding unit extracts a header from an in-device data input 85 and outputs a header information 88, and a header detection circuit 82 which receives the header information 88 as an input and outputs the header information. VPI (Vi
rtual Path Identifier), VC
I (Virtual Channel Identif)
ier) with new VPI and VCI values, a routing conversion circuit 83, and header & overhead information 89.
And a header adding circuit 84 that writes the data into the cell and outputs the data as an in-device data output 86. In addition,
87 is a system clock.

In FIG. 9A, the switch unit includes an OH detection circuit 90 for extracting OH information 99 from the in-device data input 96, and a write address calculation for calculating a write address based on the extracted OH information 99. A circuit 91, a buffer write determination circuit 92, a switch buffer 93 that outputs an in-device data output 97, a discard cell decision circuit 94 that decides whether to discard a cell, and a cell discard circuit 95 that discards a cell. It is comprised including. Note that 98 is a system clock, 100 is write address information, and 101 is discard instruction information.

In FIG. 10 (a), the output format conversion unit includes the internal data 108 and the system clock 1
A clock transfer circuit 102 having an input of 10 and a scramble circuit 103 for scrambling a payload section
And a header detection circuit 104 for extracting a header, and HE
An HEC generation circuit 107 for generating C, an HEC addition circuit 105 for adding HEC, and an SDH termination circuit 106 for outputting transmission data 109 are included. Note that 110 is a system clock, 111 is a transmission clock, 112 is header information, and 113 is HEC information.

First, the operation of the input-side format converter will be described with reference to FIG. The received data 78 input to the device terminates the SDH section at the SDH termination section 73,
OH (Section Over Head) information and POH (Pass Over Head) information are extracted. The SOH and POH positions are set as unused areas in the apparatus as a stuff area. Next, the cell synchronization circuit 74
To establish cell synchronization with reference to the HEC byte. if,
When an error is detected in the header, the error correction circuit 75 performs one-bit error correction of the header part and error detection of two or more bits. The cells output from the error correction circuit 75 are subjected to the descrambling process of the payload portion by the descrambling circuit 76 and output to the clock transfer circuit 77. In the clock transfer circuit 77, the data synchronized with the reception clock 80 is rewritten with the system clock 81, and is output to the routing information adding unit in a state synchronized with the system clock 81.

In the input-side format converter, HEC information is added to the cell format at the time of reception as shown in FIG. 7B, but the cell format at the time of output is as shown in FIG. 7C. HEC as shown in
Converting bytes to unused bytes. Also, the frame configuration at the time of reception is as shown in FIG.
H and POH are added, but in the frame configuration at the time of output, as shown in FIG.
The OH area is converted to a stuff area.

Next, the operation of the routing information adding unit will be described with reference to FIG. The in-apparatus data 85 input from the format converter is first sent to the header detection circuit 8.
In step 2, a header is extracted, and header information 88 is output. The cell is output to the header adding circuit 84. The routing conversion circuit 83 inputs the header information 88 and refers to the corresponding routing table from the VPI and VCI of the header information 88 and replaces them with new VPI and VCI values. Also, VPI, VCI, PT (Payload T)
ype), CLP (Cell Loss Priori)
ty), cell identification determination, broadcast instruction determination, priority determination, and reading of the corresponding switch output port number are performed, and the cell identification information, broadcast instruction information, priority information, and switch output number are used as OH information as header information. To be added. The converted header and the added OH are output to the header adding circuit 84 as header & OH information 89, and are written in the cell by the header adding circuit 84. The cell after writing the header is output to the switch unit.

The cell format at the time of input to the routing addition unit is such that unused bytes are added as shown in FIG. 8B, but the cell format at the time of output is
As shown in FIG. 8C, since the routing information is added, the unused bytes are converted into OH bytes. Further, the frame configuration at the time of input and the frame configuration at the time of output are not changed as shown in FIGS. 8 (d) and 8 (e).

Next, the operation of the switch unit will be described with reference to FIG.
Description will be made based on (a). The output data 96 of the routing information adding unit is first input to the OH detection circuit 90, and OH information 99 is extracted from the OH byte. OH information 9 extracted
9 is a write address operation circuit 91 and a discard cell determination circuit 9
4 is output. At the same time, the cell is output to the buffer write determination circuit. In the write address operation circuit 91, the OH information 99
The write address in the switch buffer 93 is calculated from the switch output port number and the broadcast instruction information, and the write address 100 is output to the buffer write determination circuit 92. The discarded cell determination circuit 94 determines whether to discard the cell in accordance with the cell identification information and the priority information of the OH information 99. If the determination result is that the cell is to be discarded, the discard instruction information 101 is output to the buffer write judgment circuit 92. When the discard instruction information 101 is input, the buffer write determination circuit 92 outputs the input cell to the cell discard circuit 95, and
To discard the cell. When the discard instruction information 101 is not input by the buffer write determination circuit 92, the write address 1
According to the value of 00, the input cell is stored in the switch buffer 93.
Write to. The cells written in the switch buffer 93 are read out at the output port and output to the output format converter.

In the switch section, the cell format at the time of input and the cell format at the time of output are shown in FIGS.
No change was made as shown in (c). In addition, in the frame configuration at the time of input, a stuff area is added as shown in FIG.
Since no data is written in the switch buffer, no stuff area exists in the switch buffer. However, on the reading side of the switch buffer, the reading operation is stopped at the stuff region timing in the frame. Therefore, the frame configuration at the time of output from the switch unit is the same as the frame configuration at the time of input as shown in FIG. does not change.

Next, the operation of the output format converter will be described with reference to FIG. When the in-device data 108 that is synchronized with the system clock is input, the data is first overwritten with the transmission clock 111 in the clock transfer circuit 102 and synchronized with the transmission clock 111. The cells after the synchronization are scrambled in the payload portion by the scramble circuit 103 and the header is extracted by the header detection circuit 104. The extracted data is output to the HEC generation circuit 107 as header information 112. At the same time, the cell outputs to the HEC addition circuit 105. HEC
The generation circuit 107 calculates the HEC value from the header information 112, and the calculation result is used as the HEC information 113 as the HEC value.
Notify the additional circuit 105. The HEC addition circuit 105 adds HEC information 1 to the HEC byte of the input cell.
13 to write the HEC value. Thereafter, SOH and POH are generated in the SDH termination unit 106, and SOH and POH are generated.
OH is inserted into the stuff area and transmitted from the device.

The cell format at the time of input to the output-side format converter is O as shown in FIG.
Although H bytes are added, the cell format at the time of transmission is such that OH bytes are converted to HEC bytes as shown in FIG.

The frame structure at the time of input is shown in FIG.
Although a stuff area is added as shown in (d), the frame configuration at the time of transmission is as shown in FIG.
H information has been overwritten.

In the second embodiment, the present system is applied to a device for cross-connecting / switching cell-based ATM cells. 11 to 1 for this embodiment.
3 will be described.

First, the operation of the input-side format converter will be described with reference to FIG.

The received data 119 input to the device terminates the physical layer OAM cell in the physical layer OAM termination unit 114 and extracts OAM information. The physical layer OAM cell position is used as a stuff area and is not used in the apparatus. Next, the cell synchronization circuit 115 establishes cell synchronization with reference to the HEC byte. If an error is detected in the header,
The error correction circuit 116 performs one-bit error correction of the header part and error detection of two or more bits. The cells output from the error correction circuit 116 are subjected to the descrambling process of the payload portion by the descrambling circuit 117 and are input to the clock transfer circuit 118. In the clock transfer circuit 118, data synchronized with the reception clock 121 is rewritten by the system clock 122, and the system clock 122
Is output to the routing information adding unit in a state synchronized with.

The cell format at the time of reception by the input-side format converter is H as shown in FIG.
Although the EC information is added, the cell format at the time of output is such that the HEC bytes are converted into unused bytes as shown in FIG. In addition, the frame configuration at the time of reception is as shown in FIG. 11D, but all the regions are cell regions, but the frame configuration at the time of output is as shown in FIG. As in the case of reception, all areas are cell areas. The physical layer OAM cell is terminated inside the frame, and the stuff area is scattered inside the frame. However, other cell positions are the same as when the frame was received.

Next, the operation of the routing information adding unit and the switch unit will be described with reference to FIG. The in-device data 125 output by the format conversion unit is input to the routing information addition unit 123, and the VPI, V
The CI refers to the corresponding routing table and replaces them with new VPI and VCI values. Also, the header VP
From the I, VCI, PT, and CLP, cell identification, broadcast instruction determination, priority determination, and reading of the corresponding switch output port number are performed, and the cell identification information, broadcast instruction information, priority information, and switch output number are determined. O as routing information
Write to the H byte.

The data 126 output from the routing information adding unit 123 is input to the switch unit 124, and reads the cell identification information and the priority information, which are the OH byte routing information, and determines whether to discard the cell. If the judgment result is that the cell is discarded, the inputted cell is discarded. If the cell is not discarded, the write address of the switch buffer is calculated from the switch output port number of the routing information and the broadcast instruction information, and the input cell is written in the switch buffer. The cell written in the switch buffer is read and output to the output-side format converter.

The operation and configuration of this series of routing information adding unit and switch unit are the same as in the first embodiment.

As shown in FIG. 12 (b), the cell format at the time of input to the routing adding unit is such that routing information is added, but the intermediate cell format is shown in FIG. 12 (c). The unused bytes are converted into OH bytes because the routing information is added as shown in FIG.

As shown in FIGS. 12 (c) and 12 (d), the intermediate cell format and the output cell format are different between the intermediate and output cell formats because the processing is only the reference of the OH byte. Then it has not changed.

FIGS. 12 (e), 12 (f), and 12 (g) show the frame configuration when input by the routing addition unit, the intermediate frame configuration, and the frame configuration when output. In addition, there is no change in that everything is a cell area. However, when writing to the switch buffer, writing to the stuff area is prohibited, and when reading from the switch, the reading operation is stopped at the position where the physical layer OAM cell is to be inserted, and the stuff area is set. Then the staff positions are different.

Next, the operation of the output format converter will be described with reference to FIG. When the in-apparatus data 134 synchronized with the system clock is input, the data is first overwritten by the transmission clock 137 in the clock transfer circuit 128 and synchronized with the transmission clock 137. The cells after the synchronization are scrambled in the payload portion by the scramble circuit 129, and the header is extracted in the header detection circuit 130. The extracted data is output to the HEC generation circuit 133 as a header information section 138.
At the same time, the cell outputs to the HEC addition circuit 131. HE
The C generation circuit 133 calculates the HEC value from the header information 138, and uses the calculation result as the HEC information 139,
Notify the C adding circuit 131. In the HEC addition circuit 131, HEC information 1 is added to the HEC byte of the input cell.
The HEC value is written based on 39. Thereafter, the physical layer OAM termination unit 132 generates a physical layer OAM cell, inserts the physical layer OAM cell into the stuff area, and transmits the stuff cell from the device.

The cell format at the time of input to the output-side format converter is O as shown in FIG.
Although the H byte is added, the cell format at the time of transmission is as shown in FIG.
It has been converted to EC bytes.

The frame configurations at the time of input and at the time of output are as follows:
As shown in FIGS. 13 (d) and 13 (e), it is the same, but the physical layer OAM
Cells are inserted.

FIG. 11A is a block diagram showing a configuration of an input format conversion unit, FIG. 12A is a block diagram showing a configuration of a routing information addition unit and a switch unit, and FIG.
FIG. 3A is a block diagram illustrating a configuration of an output format conversion unit.

In FIG. 11A, the input format conversion unit receives the received data 119 as an input, and outputs an OAM (Ope)
rating Administration Mon
OAM physical layer termination circuit 114 for extracting information, and cell synchronization circuit 11 for establishing cell synchronization
5, an error correction circuit 116 for correcting errors in the header,
Descramble circuit 117 for performing descrambling processing
And a clock switching circuit 118 that switches the clock from the reception clock 121 to the system clock 122 and outputs the in-device data 120.

In FIG. 12A, the routing information adding unit 123 performs a routing process on the input device data 125. In addition, the switch unit 124 determines the discard of the cell with respect to the input device data 126.

In FIG. 13 (a), the output format converter outputs the internal data 134 and the system clock 1
And a descramble circuit 12 for scrambling the payload section.
9, a header detection circuit 130 for extracting a header,
An HEC generation circuit 133 that generates an EC, an HEC addition circuit 131 that adds an HEC, and a physical layer OAM termination circuit 132 that outputs transmission data 135 are configured. 136 is a system clock, and 137 is a transmission clock.

As described above, in the present system, one byte originally used for HEC is used for COH,
One cell is processed with 53 bytes, the same number of bytes as the transmission path cell. As a result, the number of cells in one frame becomes the same as the number of transmission lines, so that stuff and destuff control is not required. In addition, since switching can be performed using COH information, high-speed switching processing can be performed.

That is, in this system, first, cell synchronization processing is performed on a cell input from the transmission
Drop C bytes. In this case, since the HEC information is not used in the device after cell synchronization, HE HE
No problem occurs when the C byte is dropped. Thereafter, the cell type is determined from the header information, and COH information is created together with the input port number. This COH information is inserted at the position where the HEC byte was. The in-device cell generated in this way is sent to the switch unit.

The switch unit performs VPI and VCI routing and performs switching based on COH information.
The COH byte is dropped for the cell output from the switch unit. Then, the HEC is calculated, and this HEC is inserted at the position where the COH byte was. The transmission line cell thus regenerated is output to the transmission line.

As described above, by equalizing the number of cells in one frame in the apparatus and in the transmission line, stuffing and destuffing are not required, so that the processing is simplified and at the same time as high speed as in the prior art. Switching is possible.

The present invention can take the following aspects in connection with the description of the claims.

(1) The data is an SDH-based AT
A transmission / reception system, which is an M cell.

(2) The data is a cell-based ATM
A transmission / reception system, being a cell.

(3) The data is an SDH-based AT
An ATM cell data receiving device comprising M cells.

(4) The data is a cell-based ATM
An ATM cell data receiving device, which is a cell.

(5) The data is an SDH-based AT
An ATM cell data transmission device characterized by M cells.

(6) The data is a cell-based ATM
An ATM cell data transmitting device, which is a cell.

[0083]

As described above, according to the present invention, one byte originally used for header error control is used for cell overhead information, and one cell is processed with 53 bytes of the same number of bytes as a transmission line cell. Accordingly, the number of cells in one frame becomes the same as that of the transmission path, and there is an effect that control of stuff and destuff becomes unnecessary. In addition, since switching can be performed using cell overhead information, there is an effect that high-speed switching processing can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cell format in an apparatus used for ATM cell data according to the present invention.

2A is a diagram illustrating a cell format of data in the device, and FIG. 2B is a diagram illustrating a cell format of data in the device.

3A is a diagram illustrating a cell format of received data, and FIG. 3B is a diagram illustrating a frame configuration of the received data.

FIG. 4A is a block diagram illustrating a configuration of an input-side format converter, and FIG. 4B is a block diagram illustrating a configuration of an output-side format converter.

5A is a diagram illustrating a cell format of transmission data, and FIG. 5B is a diagram illustrating a frame configuration of transmission data.

FIG. 6 is a block diagram showing a configuration of a device of a transmission / reception system according to an embodiment of the present invention.

7A is a block diagram illustrating a configuration of an input format conversion unit, FIG. 7B is a diagram illustrating a cell format at the time of reception, FIG. 7C is a diagram illustrating a cell format at the time of output,
(D) is a diagram illustrating a frame configuration at the time of reception, and (e) is a diagram illustrating a frame configuration at the time of output.

8A is a block diagram illustrating a configuration of a routing information adding unit, FIG. 8B is a diagram illustrating a cell format at the time of input, FIG. 8C is a diagram illustrating a cell format at the time of output,
(D) is a diagram showing a frame configuration at the time of input, and (e) is a diagram showing a frame configuration at the time of output.

FIG. 9A is a block diagram illustrating a configuration of a switch unit.
(B) shows a cell format at the time of input, (c) shows a cell format at the time of output, (d) shows a frame configuration at the time of input, and (e) shows a frame configuration at the time of output. FIG.

10A is a block diagram illustrating a configuration of an output format conversion unit, FIG. 10B is a diagram illustrating a cell format at the time of input, FIG. 10C is a diagram illustrating a cell format at the time of output,
(D) is a diagram showing a frame configuration at the time of input, and (e) is a diagram showing a frame configuration at the time of output.

FIG. 11A is a block diagram illustrating a configuration of an input-side format converter, a diagram illustrating a cell format at the time of reception,
(C) is a diagram showing a cell format at the time of output, (d) is a diagram showing a frame configuration at the time of reception, and (e) is a diagram showing a frame configuration at the time of output.

12A is a diagram illustrating a routing information adding unit and a switch unit, FIG. 12B is a diagram illustrating a cell format at the time of input, FIG. 12C is a diagram illustrating an intermediate cell format,
(D) is a diagram showing a cell format at the time of output, (e) is a diagram showing a frame configuration at the time of input, (f) is a diagram showing a frame configuration at the middle, and (g) is a diagram showing a frame configuration at the time of output. It is.

13A is a block diagram illustrating a configuration of an output format converter, FIG. 13B is a diagram illustrating a cell format at the time of input, FIG. 13C is a diagram illustrating a cell format at the time of transmission,
(D) is a diagram showing a frame configuration at the time of input, and (e) is a diagram showing a frame configuration at the time of output.

FIG. 14 is a block diagram showing a configuration of an input side of a conventional ATM cell data transmission / reception system.

FIG. 15 is a block diagram showing a configuration of an output side of a conventional ATM cell data transmission / reception system.

FIG. 16 is a diagram showing an arrangement of each format conversion unit.

17A is a diagram showing a cell format of received data, FIG. 17B is a diagram showing a cell format of FIFO data for speed matching, and FIG. 17C is a diagram showing a cell format of data in the device.

18A is a diagram illustrating a frame configuration of received data, and FIG. 18B is a diagram illustrating a frame configuration of data in the apparatus.

19A is a diagram illustrating a cell format of data in the device, FIG. 19B is a diagram illustrating a cell format of FIFO data for speed matching, and FIG. 19C is a diagram illustrating a cell format of transmission data.

20A is a diagram illustrating a frame configuration of data in the device, and FIG. 20B is a diagram illustrating a frame configuration of transmission data.

FIG. 21 is a diagram showing the contents of overhead information.

FIG. 22 is a diagram showing a circuit configuration for performing stuff control.

FIG. 23 is a diagram showing a circuit configuration for performing destuff control.

[Explanation of symbols]

 67 Input format conversion unit 68 Routing information addition unit 69 Cross connect / switch 70 Output format conversion unit 73 SDH termination circuit 74,115 Cell synchronization circuit 75,116 Error correction circuit 76,117 Descramble circuit 77,102,118 Circuits 82, 104 Header detection circuit 83 Routing conversion circuit 84 Header addition circuit 90 OH detection circuit 91 Write address operation circuit 92 Buffer write judgment circuit 93 Switch buffer 94 Discarded cell judgment circuit 95 Cell discarding circuit 103 Scramble circuit 105 HEC addition circuit 106 SDH Termination circuit 107 HEC generation circuit 114 OAM physical layer termination circuit

Claims (11)

[Claims] An ATM cell data transmitting / receiving system for performing routing processing on received ATM cell data and transmitting the ATM cell data, wherein the ATM cell data is routed to an area where header error control information used for header error control of the received ATM cell data is to be stored. Storage means for storing cell overhead information used for the routing, routing means for performing routing processing on the stored data, and addition means for adding header error control information instead of cell overhead information of the data after the routing processing An ATM cell data transmission / reception system comprising: 2. The apparatus according to claim 1, further comprising a clock changing means for synchronizing the received ATM cell data with an internal clock, wherein the storage means stores the cell overhead information for the data after the clock changing. The ATM cell data transmitting / receiving system according to claim 1, wherein: 3. The system according to claim 2, further comprising a clock changing means for synchronizing the data to which the header error control information is added with a transmission clock, and transmitting the data after changing the clock. 2. The ATM cell data transmission / reception system according to 1. 4. The ATM cell data according to claim 1, wherein said storage means includes means for overwriting the cell overhead information in an area where the header error control information is to be stored. Transmission / reception system. 5. The AT according to claim 1, wherein the adding unit includes a unit that overwrites the cell error information with the header error control information.
M cell data transmission / reception system. 6. An ATM cell data receiving apparatus for performing a routing process on received ATM cell data, wherein the ATM cell data receiving apparatus performs routing processing to an area where header error control information used for header error control of the received ATM cell data is to be stored. A storing means for storing cell overhead information to be used, and a routing means for performing a routing process on the stored data.
TM cell data receiving device. 7. A clock changing means for synchronizing the received ATM cell data with an internal clock, wherein the storage means stores the cell overhead information for the data after the clock change. 7. The ATM cell data receiving device according to claim 6, wherein: 8. The ATM cell data receiving apparatus according to claim 6, wherein said storage means includes means for overwriting the cell overhead information in an area where the header error control information is to be stored. 9. An ATM cell data transmitting apparatus for performing a routing process on ATM cell data and transmitting the ATM cell data, wherein the ATM cell data is used for routing to an area where header error control information used for header error control of the ATM cell data is to be stored. Routing means for performing routing processing on the data after storing the cell overhead information;
An ATM cell data transmitting apparatus comprising: an adding unit for adding header error control information instead of the cell overhead information of the data after the routing processing. 10. The system according to claim 1, further comprising clock changing means for synchronizing the data to which the header error control information is added with a transmission clock, and transmitting the data after changing the clock. ATM described in 9
Cell data transmission device. 11. The ATM cell data transmitting apparatus according to claim 9, wherein said adding means includes means for overwriting said cell error information with said header error control information.