JPH05252188A - Interface circuit for atm transmission and method for using cell - Google Patents

Abstract

PURPOSE:To distinguish an in-device generated empty cell from other cells by newly generating an empty cell at the time of transfer of timing and outputting specific information. CONSTITUTION:A write address control circuit 16 inputs a transmission line extraction timing signal 3 and controls operation for writing a cell in a cell buffer 12 according to a clock extracted from the reception signal of an ATM transmission line. Further, a phase supervisory and control circuit 17 is equipped with a means which monitors the phase of write timing and inserts an empty cell when there is no cell stored in the cell buffer 12 or when a cell buffer number becomes less than a predetermined numeral. Then an emptiness marker adding circuit 13 outputs information indicating a generated empty cell when the phase supervisory and control circuit 17 newly generates the empty cell. The phase supervisory and control circuit 17 and emptiness marker adding circuit 13 are provided with an empty cell generating means and a monitor means which outputs information for distinguishing the in-device empty cell from other cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an asynchronous transfer mode (Asyn
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching system and a transmission system that form a communication network by a chronous transfer mode (hereinafter abbreviated as ATM), and more particularly to a method of configuring and using a cell used in the system.

[0002]

2. Description of the Related Art ATM divides digital information such as voice, data, and images into fixed-length blocks (called cells) with a header and transmits them in cell units. Cell length is 32 ~
It can be arbitrarily defined with 128 bytes, for example, 53
It can be a bite. Serial bit stream
ATM communication device receives an ATM signal
The timing signal extracted from the signal received from the transmission line (hereinafter referred to as "transmission line extraction timing signal") must be used to establish cell synchronization with the serial bit stream signal. Also, the ATM communication device sends the cell synchronized with the transmission path extraction timing signal to the ATM
In addition to performing the operation of transferring to the internal timing signal for driving the entire communication device, the cell format conversion is performed so that it can be easily processed in the ATM communication device. As a conventional example of a method for realizing the above cell synchronization function and timing transfer function, there is a known document “Nagano, et al .:“ Practical application of high-speed CMOS LSI group for ATM switch ””, IEICE Tech., SSE90-36, pp. .31-36 (flat
2). There is a method described in ".

[0003]

A cell conversion circuit which realizes the cell synchronization function and the timing transfer function described in the above-mentioned publicly known document has a FIFO (First In First Out) memory for temporarily storing cell information. It is realized by controlling the timing of writing and reading in the buffer memory. The serial bit stream signal becomes an empty cell when there is no information because cells are continuously transmitted. At this time, the empty cells received from the ATM transmission line (hereinafter referred to as the first empty cells) are discarded at the front stage of the buffer memory, and new empty cells (when the buffer memory becomes empty at the latter stage of the buffer memory). Less than,
The second empty cell) is added. Therefore, in the latter stage of the circuit, the first empty cell included in the cell flow on the ATM transmission line and the second empty cell generated in the process of transferring the timing signal cannot be distinguished, and a single kind of empty cell I have no choice but to handle it. That is, since the first empty cell is discarded, the position where the second empty cell is arranged is not necessarily the same as the position where the first empty cell was, and the throughput of the cell on the ATM transmission line and the device The second empty cell number and the first empty cell number are not the same because the throughput of the cells in the cell is different.

This has a problem that the position of the empty cell (first empty cell) on the ATM transmission line cannot be specified in the latter stage of the buffer memory, that is, inside the ATM communication device. As a result, it becomes difficult to realize the function of handling cell arrangement information on the ATM transmission path inside the ATM communication device. As an example of the function of handling cell placement information, there is a policing function that monitors the occupied bandwidth of the user cell and controls cell discard at the time of violation. The policing function is a function of monitoring cell placement information, obtaining an occupied band from a used cell and a vacant cell for a certain period, and discarding the cell if the occupied band is larger than the occupied band preliminarily contracted by the user.

An object of the present invention is to solve the above problems.
It is to provide a means for distinguishing an empty cell generated in the device from other cells.

[0006]

In order to solve the above problems, an ATM transmission line for transferring cells which are fixed length blocks is connected in an asynchronous transfer mode, and the timing on the transmission line is set to the timing within its own device. In the ATM transmission interface circuit for transfer, an empty cell generating means for newly generating an empty cell at the time of changing the timing, and a monitoring means for outputting information for distinguishing the generated empty cell from other cells. Have.

The monitoring means can output, as the information for discriminating cells, the information indicating the generated empty cells, and the information indicating the other cells.

The monitoring means can output information for distinguishing cells when the empty cell generating means newly generates an empty cell.

Further, the monitoring means detects that the cell received from the ATM transmission line is an empty cell, and outputs information indicating that the cell is an empty cell received from the ATM transmission line as information for distinguishing cells. It is possible to output the information indicating that the generated empty cell and the empty cell received from the ATM transmission line. Further, the monitoring means detects that the cell received from the ATM transmission line is an empty cell, and as the information for distinguishing cells, the generated empty cell and the empty cell received from the ATM transmission line. Information indicating that there is a cell and cells other than that may be output.

Further, the monitoring means has an addition means for adding information for identifying a cell to the cell and outputting the information.

The above-mentioned monitoring means has an addition means for adding information for distinguishing a cell as code information to the cell and outputting it.

Further, the monitoring means can output information for distinguishing cells via a control line.

The vacant cells received from the ATM transmission line are recommended by International Telegraph and Telephone Consultative Committee (CCITT) Recommendation I.I. Three
It is an idle cell defined by 61.

As a circuit for realizing the above means, an ATM for transferring cells of a fixed length block in an asynchronous transfer mode.
In a cell conversion circuit in which a transmission line is connected and the timing on the transmission line is transferred to the timing in the device itself,
A cell buffer for accumulating cells from the transmission line, a write address control circuit for instructing a write address of the cell buffer at a timing on the transmission line, and a read address control circuit for instructing a read address of the cell buffer at a timing within the own device. , An address comparison circuit for comparing a write address and a read address, an empty cell instruction circuit for outputting an instruction of an empty cell based on a comparison result from the address comparison circuit, and an instruction from the empty cell instruction circuit The read address control circuit has an additional circuit for adding information for discriminating between the empty cell and the other cells to the cell, and the read address control circuit can stop the reading of the cell according to an instruction from the empty cell instruction circuit. ..

[0015]

The operation of the solving means will be described below.

In the ATM transmission interface circuit, the empty cell generating means newly generates an empty cell.
The monitoring means outputs the information for distinguishing the generated empty cell from the other cells, so that the generated empty cell and the other cells can be distinguished and used.

Further, the monitoring means detects that the cell received from the ATM transmission line is an empty cell,
It is possible to distinguish between the generated empty cell and the cell received from the ATM transmission line.

The adding means of the monitoring means adds the information for distinguishing the cell to the cell as bit assignment or code information and outputs it. Alternatively, the monitoring means outputs the information for distinguishing the cells via the control line.

In the circuit realizing the above means, the cell buffer stores cells from the ATM transmission line, the write address control circuit indicates the write address of the cell buffer at the timing on the transmission line, and the read address control circuit, It designates the read address of the cell buffer at the timing within its own device. The address comparison circuit compares the write address and the read address, and the empty cell instruction circuit outputs an instruction of the empty cell to the additional circuit and the read address control circuit based on the comparison result. In response to an instruction from the empty cell instruction circuit, the addition circuit adds information for distinguishing the generated empty cell and other cells to the cell, and the read address control circuit stops reading the cell.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration diagram of an interface section showing a first embodiment of the present invention. In this embodiment, as a means for distinguishing the types of empty cells, the case of using the empty cell type information installed in the cells will be described. FIG. 1 shows the configuration of the interface section between the ATM transmission line and the ATM communication device.

In FIG. 1, the interface section is provided with a function of converting the cell structure in the ATM communication apparatus of the present invention, and is an interface circuit for changing the timing on the transmission path to the timing in the own apparatus. The interface part is SDH (Synchronous Digital Hierarch)
y) It has a termination circuit 10, a cell synchronization circuit 11, and a cell configuration conversion circuit 18. The SDH termination circuit 10 has A
The TM transmission line 1 is connected, and a cell stream which is a serial bit stream signal according to the format of the ATM transmission line is input. The cell synchronization circuit 11 receives a continuously flowing cell stream and synchronizes with the cell. Cell configuration conversion circuit 18
Then, the highway 2 in the ATM communication device is connected, and the cell flow having the empty cell identification information is output. This AT
The output end of the highway 2 in the M communication device is connected to the policing circuit 20. Further, the cell configuration conversion circuit 18
It has a cell buffer 12, an empty marker adding circuit 13, a read address control circuit 15, a write address control circuit 16 and a phase monitoring control circuit 17. Cell buffer 12
Stores the cells synchronized in the cell synchronization circuit 11 including a valid cell and an empty cell by a write instruction,
The cell is output according to the read instruction. The writing timing and the reading timing can be changed so that they can be exchanged. The write address control circuit 16 inputs the transmission path extraction timing signal 3 and, based on the clock extracted from the reception signal of the ATM transmission path, the cell buffer 12
Controls the operation for writing cells to. Further, the read address control circuit 15 inputs the in-device timing signal 4 and, based on a common clock inside the ATM communication device,
It controls the operation of reading cells from the cell buffer 12.
The phase monitoring control circuit 17 monitors the phase between the timing of writing and the timing of reading, and when there are no cells stored in the cell buffer 12 or when the number of cell buffers is equal to or less than a predetermined number, empty cells It has an empty cell generation means for inserting Empty marker addition circuit 13
When the phase monitoring control circuit 17 newly creates a free cell, outputs the information indicating that the created free cell. The phase monitoring control circuit 17 and the vacant marker adding circuit 13 distinguish between a vacant cell generation means for newly generating a vacant cell (hereinafter referred to as intra-device generated vacant cell) and the intra-device generated vacant cell. And a monitoring means for outputting information. What is an empty cell created in the device?
This is a cell to be inserted as a dummy in the cell configuration conversion circuit 18 because the throughput of the accommodation portion of the cell on the output side of the cell configuration conversion circuit 18 is higher than that on the input side. For example, when the frequency of the common clock inside the ATM communication device is the same as the frequency of the clock on the transmission line, the cell length within the device is 54 bytes, and the cell length on the transmission line is 53 bytes. The cell throughput (cell / sec) ratio in the transmission path and device when the SOH, which is the header of, is erased after cell conversion is taken as an example. Since the ratio of SOH in one cell is 1/27, the ratio of other information in one cell is 26/27. From these, the cell throughput (cell / sec) ratio in the transmission line and the device is (2
6/27). (54/53) = 52/53. As a result, one empty cell is inserted for every 53 cells.

Next, the operation of the cell configuration conversion circuit 18, which plays a central role in implementing the present invention, will be described with reference to FIGS.

First, a signal format at the input / output of the cell configuration conversion circuit 18 shown in FIG. 1 will be described. FIG. 2 shows a frame configuration at the input and output of the cell configuration conversion circuit 18. In this embodiment, CCITT Recommendation I.S. An example is shown in which an ATM transmission line based on SDH (Synchronous Digital Hierarchy) defined by H.432 is accommodated.

In FIG. 2, a solid outline on the outer side indicates a frame unit, and a small rectangle inside the frame is an ATM cell accommodated in the frame. The alphabetic characters described in the cell indicate the cell type (U: valid cell, V: transmission line reception empty cell), and the numbers indicate the serial number in each cell type. ATM handled in this embodiment
The cells are classified into three types: valid cells (including user cells and network OAM (Operation and Maintenance) cells), transmission line empty cells (shown by diagonal lines), and device-generated empty cells (shown by dashed lines). I am handling. FIG. 2A shows a frame configuration at the time of input to the cell configuration conversion circuit 18, that is, before the cell configuration conversion. A cell is accommodated in a portion excluding SOH in the head area of a transmission path management frame. In this frame structure, the cell stream includes valid cells and empty cells equipped with a transmission path. 2B shows a frame structure at the time of output from the cell structure conversion circuit 18, that is, after the cell structure conversion, and cells are accommodated in the entire frame. In this frame structure, in-cell generated empty cells are included in the cell flow in addition to the two types of (a). As for the valid cells and the empty cells equipped with a transmission line shown in FIG. 2B, all the cells on the ATM transmission line shown in FIG. 2A are stored. Therefore, if it is possible to identify the existence of an empty cell generated in the apparatus as described later, it is understood that the arrangement of the effective cell on the ATM transmission line and the empty cell mounted on the transmission line can be reproduced in the subsequent stage.

FIG. 3 shows a cell configuration at the time of input to the cell configuration conversion circuit 18, and corresponds to one cell accommodated in the frame shown in FIG. 2 (a). The cell configuration shown in FIG. 36
1 is an example of the cell configuration on the ATM transmission line defined in 1. The cell configuration shown in FIG. 3 has a VPI (Virtua
l Path Identifier (mounting area) 100, VCI (Virtual
It has a channel identifier) mounting area 101, a control information mounting area 102, an HEC (Header Error Control) mounting area 103, and a user information mounting area 104.

On the other hand, FIG. 4 shows the cell configuration conversion circuit 1
8 shows the cell configuration at the time of outputting to FIG.
The HEC mounting area 103 is deleted from the cell configuration shown in (1), and an in-device control information mounting area 105 is newly added. Information for identifying the above-mentioned three types of cells, that is, the valid cell, the transmission path-installed empty cell, and the in-apparatus generated empty cell is installed in the in-apparatus control information installation area 105. The conversion from the cell configuration of FIG. 3 to the cell configuration of FIG. 4 is performed by the cell configuration conversion circuit 18 together with the conversion of the frame configuration shown in FIG.

FIG. 5 shows an example of the basic structure of the in-apparatus control information 105. In this example, the 1-byte in-apparatus control information 105 has a 1-bit identification bit mounting area 200 and a 7-bit routing information / control code mounting area 201. The identification bit mounting area 200 assigns a bit for identifying whether it is routing information or a control code. In the routing information / control code mounting area 201, for example, when the identification bit is 1, routing information indicating the output highway number is assigned, and when the identification bit is 0, each cell type is added as a control code.

FIG. 6 shows an example of coding of the identification bit mounting area 200 and the routing information / control code mounting area 201. In this example, the lower 7 bits of the in-device control information 105 are shared by the routing information (output highway number) and the control code, and the upper 1 bit of the in-device control information 105, that is, the logical value of the identification bit. Identify them by. According to this coding method, valid cells can be identified only by the logical value of the identification bit, and transmission channel reception empty cells and in-device generated empty cells can be identified by the identification bit and the logical value of the control code. .. In addition, it is also possible to identify cells other than the above-mentioned three types, for example, in-apparatus supervisory control cells that are closed inside the ATM communication apparatus and used for supervisory control of the apparatus. Routing information is AT
This is information added in the subsequent stage of the cell configuration conversion circuit 18 inside the M communication device.

Further, code information, which is a predetermined bit string determined in advance, may be added to the cell information in an area other than the routing information / control code mounting area 201. Further, in the case of distinguishing between the in-device generated empty cell and the transmission path mounted empty cell, it may be indicated as 1-bit bit information (bit assignment).

As described above, as information for distinguishing cells,
It is possible to output information indicating that the cell is an intra-device generated empty cell, and output information indicating that the cell is another cell. Further, it is possible to detect that the empty cell installed in the transmission path is an empty cell, and output the information indicating the empty cell installed in the transmission path as the information for distinguishing the cell, and the empty cell generated in the device. And information indicating that the cell is an empty cell equipped with a transmission path. Also,
The monitoring means detects that the cell received from the ATM transmission line is an empty cell, and as the information for distinguishing the cell,
Information indicating that the cell is an intra-apparatus generated empty cell, that the cell is an empty cell equipped with a transmission path, and that it is another cell may be output.

Based on the above contents, the internal operation of the cell configuration conversion circuit 18 shown in FIG. 1 will be described. The cell buffer 12 has a function of accumulating cell information received from the ATM transmission line. The write address control circuit 16 connected to this has a function of controlling writing of cell information to the cell buffer 12, and the read address control circuit 15 has a function of controlling reading of cell information. Here, the cell information is written and read for both the effective cell and the transmission path mounted empty cell. The phase control circuit 17 has a function of monitoring the phase relationship between the write address and the read address, and the cell buffer 12
By stopping the reading from the cell according to the address phase relationship, a newly created empty cell in the device is inserted. When adding the cell information to the empty cell generated in the device, the phase control circuit 17 sends a control signal to the empty marker adding circuit 13, and the empty marker adding circuit 13 adds a code for identifying the empty cell generated in the device to the corresponding cell. To do. In addition, for empty cells equipped with a transmission path, the empty marker adding circuit 13 detects preassigned values (usually all 0) of VPI and VCI in the header portion, and a code for identifying empty cells equipped with a transmission path is detected. Add to the corresponding cell.

FIG. 8 shows a detailed block diagram of the inside of the cell configuration conversion circuit 18 shown in FIG. The operation will be described in detail with reference to FIG.

The cell buffer 12 is, for example, a FIFO.
(First In First Out) It is composed of the memory 304, etc., and is read out from the cell written previously. The write address of the FIFO memory 304 is designated by the write address counter 302, which is the write address control circuit 16. The write address counter 302 operates by a clock on the transmission path, and is incremented by 1 when the FIFO memory 304 writes, and decremented by 1 when the FIFO memory 304 is read, thereby designating a write address. The read address of the FIFO memory 304 is designated by the read address counter 303, which is the read address control circuit 15. The read address counter 303 operates according to the internal clock of the ATM communication device, and always indicates the head address in the case of a FIFO memory. Further, the read address counter 303 can stop the reading according to the instruction of the empty cell from the phase monitoring circuit 17. The phase monitor circuit 17 has an address comparison means 300 and an empty cell indication means 301. The address comparison means 300 compares the addresses of the write address counter 302 and the read address counter 303 and outputs the difference between the addresses. The empty cell instructing means 301 instructs the read address counter 303 to make an empty cell when the address difference from the address comparing means 300 becomes equal to or less than a predetermined numerical value, and instructs the empty marker adding circuit 13 to perform the operation in the apparatus. It is instructed to add information indicating that it is an empty cell. For example, the empty cell instructing means 301 sets the address difference to 2 cells in advance, and when the address difference between the write address counter 302 and the read address counter 303 becomes 2 cells, the empty cell instruction means 301 sets the cell as an empty cell. In this way, the read address counter 303 is instructed to stop reading one cell. Thereby, an empty cell can be generated in the device. The vacant marker adding circuit 13, when instructed by the vacant cell instructing means 301 of the phase monitoring circuit 17, indicates the information indicating that it is an intra-apparatus generated vacant cell in the predetermined area shown in FIG. 5 and FIG. Is added to the empty cell and transmitted. Further, the empty marker adding circuit 13 may detect the pre-assigned values of VPI and VCI in the header part of the empty cell equipped with the transmission path, and add the code for identifying the empty cell equipped with the transmission path to the corresponding cell. .. In this case, since a transmission path-equipped empty cell can be detected, information indicating that the transmission path-equipped empty cell is added to the transmission-path-equipped empty cell can be distinguished from the intra-device-generated empty cell. Therefore, information may not be added to the empty cell generated in the device. Further, if the cell is not an empty cell generated in the apparatus and is not a transmission path-installed empty cell, it may be determined that the cell is a valid cell and predetermined code information may be added to all cells.

As described above, the cell configuration conversion circuit 18
Is output with the information for distinguishing the in-device generated cell like the cell configuration shown in FIG. The policing circuit 20 shown in FIG. 1 receives a cell having the configuration shown in FIG. 4 from the in-device highway 2 connected to the cell configuration conversion circuit 18. Therefore, the policing circuit 20 can decode the in-device control information 105 having the cell structure shown in FIG. 4 and reproduce the cell arrangement on the ATM transmission line by identifying the empty cells generated in the device. It becomes possible to carry out a polishing process.

FIG. 7 is a block diagram of an interface section showing a second embodiment of the present invention. In the present embodiment, a case where a signal line for identifying an empty cell is provided on a separate line will be described.

In FIG. 7, the interface section is SD
It has an H termination circuit 10, a cell synchronization circuit 11, and a cell configuration conversion circuit 19. An ATM transmission line 1 is connected to the SDH termination circuit 10, and a cell stream which is a serial bit stream signal according to the format of the ATM transmission line is input.
The cell synchronization circuit 11 receives a continuously flowing cell stream and synchronizes with the cell. The cell configuration conversion circuit 19 has A
The highway 2 in the TM communication device is connected and the cell flow converted into the cell configuration in the ATM communication device is output. The output end of the highway 2 in the ATM communication device is connected to the policing circuit 20. Further, the cell configuration conversion circuit 19
Has a cell buffer 12, a read address control circuit 15, a write address control circuit 16 and a phase monitoring control circuit 17. An empty cell identification signal 5 is output from the phase monitoring / monitoring circuit 17 and connected to the policing circuit 20.

The operation of the second embodiment shown in FIG. 7 will be described next. The write operation and read operation of the cell buffer 12 of this embodiment are the same as those of the first embodiment. The difference from the first embodiment is that the signal for notifying the type of the empty cell to the subsequent stage, that is, the empty cell identification signal 5 is connected to the polishing circuit 20 as a separate line from the output from the cell buffer 12. is there. The policing circuit 20 refers to the content of the empty cell identification signal 5 to identify the empty cell generated in the device in the in-device highway 2, and A
After the cell arrangement on the TM transmission line is reproduced, the policing process is performed. The phase monitoring circuit 17 can output the empty cell identification signal 5 when the empty cell instructing means 301 generates an empty cell in the device.
That is, instead of instructing the empty marker adding circuit 13, the empty cell identification signal 5 can be output to the read address counter 303 simultaneously with the instruction to stop reading one cell. According to the cell usage method of the present invention, it is possible to realize a function of handling cell arrangement information on an ATM transmission line, such as a policing function, inside an ATM communication device.

As described above, according to the present invention, it is possible to recognize an in-device generated empty cell and distinguish between an in-device generated empty cell and a transmission path mounted empty cell.

The cells included in the cell flow inside the ATM communication device can be roughly classified into the following three types of cells.

Valid cells (including user cells and network OAM cells). An empty cell equipped with a transmission line. Free cells generated in the device.

Of these, the objects to be polished are
These are valid cells and empty cells equipped with transmission paths, which can be identified by referring to the empty cell identification information installed in the cells or the empty cell identification signal transmitted on a separate line.

Further, in realizing the ATM communication device, even when a cell type is newly defined in addition to the above three types, the identification information for identifying the added cell type is additionally mounted in the cell. By doing so, or by adding a cell type identification signal, an effect equivalent to the above case can be obtained.

[0044]

According to the present invention, after the cell configuration conversion, the in-apparatus generated empty cell can be distinguished from other cells.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an interface unit showing a first embodiment of the present invention.

FIG. 2 is a frame configuration diagram illustrating the operation of the cell configuration conversion circuit of the present invention.

FIG. 3 is a cell configuration diagram in an ATM transmission line to which the present invention is applied.

FIG. 4 is a block diagram of a cell in a device showing a first embodiment of the present invention.

FIG. 5 is a basic configuration diagram of in-device control information according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of code designation of in-apparatus control information according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram of an interface unit showing a second embodiment of the present invention.

FIG. 8 is a block diagram of monitoring means.

[Explanation of symbols]

1 ... Receiving side transmission line, 2 ... Device internal highway, 3 ... Transmission line extraction timing signal, 4 ... Device timing signal, 1
0 ... SDH termination circuit, 11 ... Cell synchronization circuit, 12 ... Cell buffer, 13 ... Empty marker addition circuit, 15 ... Read adrel control circuit, 16 ... Write address control circuit, 17 ... Phase monitoring circuit, 18 ... Cell configuration conversion Circuits, 19 ... Cell configuration conversion circuit, 20 ... Polishing circuit, 100 ... VPI mounting area, 101 ... VCI mounting area, 102 ... Control information mounting area, 103 ... HEC mounting area, 104 ... User information mounting area, 105 ... In-apparatus Control information mounting area, 200 ... Identification bit mounting area, 201 ... Routing information / control code mounting area, 5 ... Empty cell identification signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuhiro Ashi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd., Information & Communication Division (72) Inventor Masahiro Takatori 1-280, Higashi-Kengokubo, Kokubunji, Tokyo Stock Hitachi, Ltd. Central Research Laboratory (72) Inventor Yukio Nakano 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Metropolitan Hitachi Ltd. (72) Inventor Hiromi Ueda 1-6 Uchiyuki-cho, Chiyoda-ku, Tokyo Nihon Telegraph Telephone Co., Ltd. (72) Inventor Takashi Nakajima 1-1-6 Uchiyuki-cho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation In-house (72) Inventor Hiroshi Takeo 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Masaaki Kawai, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Inside Fujitsu Limited (72) Inventor, Ikuo Taniguchi, 1015, Kamedotachu, Nakahara-ku, Kawasaki-shi, Kanagawa Inside Fujitsu Limited (72) Person Takaki Kurano 5-7-1, Shiba 5-chome, Minato-ku, Tokyo Inside NEC Corporation (72) Motoo Nishihara 5-7-1, Shiba 5-chome, Minato-ku, Tokyo Within NEC Corporation

Claims (13)

[Claims] 1. Asynchronous transfer mode (ATM)
In the ATM transmission interface circuit in which an ATM transmission line for transferring cells of fixed length blocks in the Transfer Mode) is connected, and the timing on the transmission line is changed to the timing in the own device, a new vacancy is obtained when the above timing is changed. An ATM transmission interface circuit comprising: an empty cell generating means for generating a cell; and a monitoring means for outputting information for distinguishing the generated empty cell from other cells. 2. The ATM transmission interface circuit according to claim 1, wherein the monitoring means outputs, as the information for distinguishing the cells, information indicating the generated empty cells. 3. The ATM transmission interface circuit according to claim 1, wherein the monitoring means outputs, as the information for distinguishing the cells, information indicating that the cells are cells other than the generated empty cells. 4. The ATM transmission interface circuit according to claim 1, wherein the monitoring means outputs information for distinguishing cells when the empty cell generating means newly generates an empty cell. 5. The monitoring means according to claim 1, wherein the cell received from the ATM transmission line is an empty cell,
An ATM transmission interface circuit characterized by outputting information indicating an empty cell received from an ATM transmission line as information for distinguishing cells. 6. The monitoring means according to claim 1, wherein the cell received from the ATM transmission line is an empty cell,
An ATM transmission interface circuit, which outputs, as information for distinguishing cells, information indicating that the cell is the generated empty cell and that the cell is an empty cell received from an ATM transmission line. 7. The monitoring means according to claim 1, wherein the cell received from the ATM transmission line is an empty cell,
As information for distinguishing cells, the information indicating that the cell is the generated empty cell, the empty cell received from the ATM transmission line, and the other cells is output. Interface circuit. 8. The ATM transmission according to claim 1, 2, 3, 4, 5 or 6, wherein the monitoring means has an addition means for adding information for identifying a cell to the cell and outputting the information. Interface circuit. 9. The monitoring means according to claim 1, 2, 3, 4, 5, 6 or 7, wherein the monitoring means has an addition means for adding information for identifying a cell to the cell as code information and outputting the code information. ATM transmission interface circuit. 10. Claims 1, 2, 3, 4, 5, 6, 7, 8
Alternatively, in 9, the monitoring means outputs the information for distinguishing the cells via the control line, and the ATM transmission interface circuit is characterized. 11. The ATM according to claim 5, 6 or 7.
The empty cell received from the transmission line is the International Telegraph and Telephone Consultative Committee (CCITT) Recommendation I. An interface circuit for ATM transmission, which is an idle cell defined by 361. 12. Asynchronous transfer mode (ATM)
A cell buffer that stores cells from an ATM transmission line in a cell conversion circuit that connects an ATM transmission line that transfers cells that are fixed-length blocks in us Transfer Mode) and that transfers the timing on the transmission line to the timing in the device itself. And a write address control circuit for instructing a write address of the cell buffer at a timing on the transmission path, a read address control circuit for instructing a read address of the cell buffer at a timing in the own device, and comparing the write address and the read address. An address comparison circuit, an empty cell instruction circuit that outputs an instruction of an empty cell based on a comparison result from the address comparison circuit, an empty cell generated by an instruction from the empty cell instruction circuit, and other cells. An adder circuit for adding distinguishing information to the cell, the read address control circuit It is cell conversion circuit, characterized in that stopping the reading of the cell in response to an instruction from the air-out cell indicating circuit. 13. Asynchronous transfer mode (ATM)
When a cell that is a fixed-length block is transferred using us Transfer Mode) and the transmission timing is changed to another timing, a new empty cell is generated at the time of changing the above timing, and the generated empty cell and other A method of using a cell, characterized by distinguishing it from a cell.