JPH11242882A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize matched layout corresponding to variable capacity by simplifying only in the increment function of cyclic type address. SOLUTION: The device is equipped with a read control section 14 for independently controlling the read row/column shift register 10, 12 and with a write control section 15 for independently controlling the write row/column shift register 11, 13, performing write-in and read-out. Address selection in the row and column directions is made by means of a write/read column shift register 11, 10 that successively selects and circulates the write/read word lines of the memory cell in the row of the memory cell array 1 and by means of a write/read row shift register 13, 12 that successively selects and circulates the write/read bit lines of the memory cell in the column of the memory cell array 1. The circuit scale can be reduced, through the cyclic shift action of each shift register, by performing the increment operation of address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for performing input / output of a first-in first-out (hereinafter, referred to as FIFO) method using a shift register for sequential address selection.

[0002]

2. Description of the Related Art A semiconductor memory device which performs input / output according to a conventional FIFO method will be described below. FIG. 4 is a block diagram of a semiconductor memory device that performs input / output by a FIFO method using a dual-port RAM, a counter circuit, and a control circuit of the counter circuit.

In FIG. 4, reference numeral 1 denotes a static memory core (memory cell (not shown)) arranged in a matrix of a desired capacity in a row direction and a column direction, and a write word line (not shown) in a row direction. ) And read word line (not shown)
, And a read row decoder unit for selecting a read word line of the memory cell array 1, a memory cell array connected to a write bit line (not shown) and a read bit line (not shown) in the column direction, 3 is a write row decoder for selecting a write word line of the memory cell array 1, 4 is a read column decoder for selecting a read bit line of the memory cell array 1, and 5 is a write bit line of the memory cell array 1. , An interface section comprising a latch circuit for input data and an amplifier circuit for output data of the memory cell array 1, and 7 an address signal to the read row decoder section 2 and the read column decoder section 4. A read counter circuit provided, 8 is a write counter circuit for providing an address signal to the write row decoder unit 3 and the write column decoder unit 5, and 9 is a read counter circuit. Counter is a control unit of circuit 7 and the write counter circuit 8.

The operation of the semiconductor memory device configured as described above for inputting and outputting data by the FIFO method will be described below with reference to FIG.

First, the write operation is performed by the NWR of the control unit 9.
A reset signal is input to the terminal (write reset terminal).
The reset signal is processed by the control unit 9 and is output to the write counter circuit 8 as an address reset signal, and the write counter circuit 8 is reset to a state indicating "0" of the initial address. Next, the initial address indicated by the write counter circuit 8 is written into the write row decoder 3 and the write column decoder 5.
, A write word line and a write bit line of a memory cell to be an initial address of the memory cell array 1 are selected. As a result, the data input to the DI terminal (data input terminal) is taken into the latch circuit (not shown) of the interface unit 6, and the output is stored in the memory cell at the initial address via the write bit line. You. Then, the address is incremented in synchronization with the increment operation of the write counter circuit 8, and the input data is sequentially stored from the initial address to the final address. When the last address of the memory cell array 1 is reached, the output of the write counter circuit 8 is decoded to reset the write counter circuit 8 internally to return to the initial address, and the write operation cycling from the initial address is performed. Will be

Next, in the read operation, the reset signal input to the NRR terminal (read reset terminal) is processed by the control unit 9 and output as a reset signal of the address to the read counter circuit 7, and the initial address "0" is read. The read counter circuit 7 is reset to a state indicating "". Next, the initial address indicated by the read counter circuit 7 is stored in the read row decoder unit 2.
Then, the read word line and the read bit line of the memory cell serving as the initial address of the memory cell array 1 are selected by input to the read column decoder unit 4. Thereby,
The data stored in the memory cell is transferred to the amplifier circuit (not shown) of the interface unit 6 via the read bit line.
And is amplified by an amplifier circuit of the interface unit 6 and output through a DO terminal (data output terminal). The address is incremented in synchronization with the increment operation of the read counter circuit 7, and data stored sequentially from the initial address to the final address is output. When the final address of the memory cell array 1 is reached, the output of the read counter circuit 7 is decoded to internally reset the read counter circuit 7 to return to the initial address, and a read operation cycling from the initial address is performed.

As described above, the write operation and the read operation are incremented by the increment operation of the counter circuit, and the NWR terminal (write reset terminal) and NRR (read reset terminal) are set so that the write address and the read address do not become the same. By inputting a reset to the terminal, a semiconductor memory device that performs input / output by a FIFO method in which a write operation and a read operation can be independently controlled is realized.

[0008]

However, a semiconductor memory device which performs input / output by the FIFO method having such a configuration, uses a counter circuit for a circuit having a random access function to an address of a dual port RAM.
Since the operation of incrementing the address is performed, the circuit has an unnecessary function, and the circuit scale is increased by adding a circuit for resetting the initial address after reaching the final address. . Further, when the memory capacity is increased, the increase in the counter circuit must be covered by the increase in the size in the X direction due to the increase in the write row decoder section and the read row decoder section. There is a problem that the matched layout is also difficult.

SUMMARY OF THE INVENTION The present invention is directed to solving the above-mentioned problem of the prior art, which simplifies only to a function of incrementing a cyclic address and can easily realize an aligned layout corresponding to variable capacitance. It is an object of the present invention to provide a semiconductor memory device which performs input / output by a FIFO method.

[0010]

In order to achieve this object, a semiconductor memory device according to the present invention comprises: a memory cell array in which static memory cells are arranged in a matrix of a desired capacity in a row direction and a column direction; A first shift register having a function of sequentially selecting and circulating write word lines of memory cells in a row of the memory cell array, and a function of sequentially selecting and circulating read word lines of memory cells in a row of the memory cell array A second shift register, a third shift register having a function of sequentially selecting and circulating a write bit line of a memory cell in a column of the memory cell array, and sequentially selecting a read bit line of a memory cell in a column of the memory cell array A fourth shift register having a function of circulating the first shift register, a first shift register, a second shift register, and a third shift register. It is obtained by configured with circuits to independently control the motor and the fourth shift register.

According to the above configuration, it is possible to easily configure the address increment operation by the cyclic shift operation of each shift register section, and to configure the shift register section by the increment of X and Y in the row direction and the column direction. Therefore, the size can be reduced, and a matching layout corresponding to the variable capacitance can be easily configured.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a semiconductor memory device according to a first embodiment of the present invention, which inputs and outputs by a FIFO method. Here, components having substantially the same functions as those described in FIG. 4 showing the conventional example and having substantially the same functions are denoted by the same reference numerals. In FIG. 1, 1 is a memory cell array of m rows and n columns, 6 is an interface unit, and 10 is a read row shift for sequentially selecting a read word line (not shown) of a memory cell (not shown) of a row of the memory cell array 1. A register section 11 is a write row shift register section for sequentially selecting a write word line (not shown) of a memory cell in a row of the memory cell array 1, and 12 is a read bit line of a memory cell in a column of the memory cell array 1 (see FIG. Read column shift register unit for sequentially selecting write bit lines (not shown) of memory cells in a column of the memory cell array 1; and read row shift register 14 for sequentially selecting write bit lines (not shown) of memory cells in a column of the memory cell array 1. Part 1
Reference numeral 15 denotes a read control unit that controls 0 and the read column shift register unit 12, and 15 denotes a write control unit that controls the write row shift register unit 11 and the write column shift register unit 13.

FIG. 2 shows the FI according to the first embodiment.
FIG. 3 is a circuit diagram showing a configuration of a read row shift register section, a write row shift register section, a read column shift register section, and a write column shift register section of the semiconductor memory device which inputs and outputs by the FO method.

As shown in FIG. 2, the read-out row shift register section 10 forms a shift register by connecting one OR circuit and m D-FF (D flip-flop) circuits in a row, and forms each D-FF. The output Q of the circuit is connected to the read word line of the memory cell array 1 and the output Q of the final stage D-FF circuit is connected.
Is input to the input D of the first stage D-FF circuit through the OR circuit to form a cyclic shift register unit.

In the write row shift register section 11,
One OR circuit and m D-FF circuits are connected in a row to form a shift register, and the output Q of each D-FF circuit is connected to the write word line of the memory cell array 1 to form a final D-FF circuit. -The output Q of the FF circuit is supplied to the first stage D through the OR circuit.
-A shift register unit that circulates by inputting to the input D of the FF circuit is configured.

The read column shift register section 12 forms a shift register by connecting one OR circuit and n D-FF circuits in a line, and outputs the output Q of each D-FF circuit to the memory cell array 1. Read bit line and interface unit 6
Are connected to a selector that connects the first and second stages, and the output Q of the last-stage D-FF circuit is input to the input D of the first-stage D-FF circuit through the OR circuit to form a cyclic shift register unit.

In the write column shift register section 13,
One OR circuit and n D-FF circuits are connected in a line to form a shift register, and the output Q of each D-FF circuit is connected to a selector connecting the write bit line of the memory cell array 1 and the interface unit 6. The shift registers are connected to each other so that the output Q of the last stage D-FF circuit is input to the input D of the first stage D-FF circuit through the OR circuit.

The operation of the semiconductor memory device configured as described above, which inputs and outputs by the FIFO method of the first embodiment, will be described below with reference to the drawings.

First, during a write operation, an "L" level reset signal is input to an NWR terminal (write reset terminal). The reset signal enters the write control unit 15, and the write row shift register unit WRR1 (row write initial shift register signal) and the write column shift register unit WCR1 (column write initial shift register signal). )
Output an “H” level. The "H" level signal is input to the D-FF circuit through the OR circuit and WRCLK
An "H" level shift operation of the output from the D-FF circuit is performed in synchronization with the signal (row direction write reference clock) and the WCCLK signal (column direction write reference clock). However, the WRCLK signal is a clock of a cycle of the n × WCLK signal (write reference clock), and the WCCLK signal is a WCL signal.
A clock having the same cycle as the K signal is input.

From the above, at first, WW0 (write word line 0) of the write row shift register section 11 goes to the "H" level, and the memory cell in that row is selected. Further, WB0 (write bit line selector 0) to WB (n-1) (write bit line selector (n-1)) of the write column shift register section 13 sequentially become "H" level, and The selectors are sequentially opened, and the input data input from the DI terminal (data input terminal) of the interface unit 6 is written to the memory cells in the column through the write bit line.

Next, the WW of the write row shift register 11
1 (write word line 1) attains the "H" level, the memory cell of that row is selected, and similarly, WB0 (write bit line selector 0) to WB (n
-1) The selectors are sequentially opened up to the (write bit line selector (n-1)), and the input data input from the DI terminal (data input terminal) of the interface unit 6 is written into the memory cells in that column. Written through the line.

As described above, writing is performed on the memory cell selected by the sequentially incremented address,
After writing to the memory cell at the final address, the write row shift register section 11 and the write column shift register section 13
When the "H" level is input to the WRR2 signal (row-wise cyclic shift register signal) and the WCR2 signal (column-wise cyclic shift register signal) of the OR circuit, the write operation is performed cyclically.

Next, in a read operation, an "L" level reset signal is input to an NRR terminal (read reset terminal). The reset signal enters the read control unit 14, and
RRR1 (row direction read initial shift register signal) of read row shift register section 10 and read column shift register section 12
"H" level is output to RCR1 (column-direction read initial shift register signal). The "H" level signal is O
The RRCLK signal (row direction read reference clock) input to the D-FF circuit at the “H” level through the R circuit and the RCC
In synchronization with the LK signal (column direction read reference clock), D-
An "H" level shift operation of the output from the FF circuit is performed. However, a clock in the cycle of the n × RCLK signal (read reference clock) is input as the RRCLK signal, and a clock in the same cycle as the RCLK signal is input as the RCCLK signal.

As a result, initially, RW0 (read word line 0) of read row shift register unit 10 attains an "H" level, and a memory cell in that row is selected. Further, RB0 (read bit line selector 0) to RB (n-1) (read bit line selector (n-1)) of the read column shift register unit 12 sequentially become "H" level, and each selector sequentially becomes It is opened, and output data is read from the memory cells in the column through the read bit line. And
The output data is output to the DO terminal (data output terminal) through the interface unit 6.

Next, the RW of the read row shift register 10
1 (read word line 1) attains the "H" level, the memory cell in that row is selected, and RB0 (read bit line selector 0) of read column shift register 12
The selectors are sequentially opened up to (n-1) (read bit line selector (n-1)), output data is read from the memory cells in the column through the read bit line, and the output data is output through the interface unit 6 to the DO. Output to the terminal (data output terminal).

In this manner, reading is performed from the memory cell at the sequentially incremented address, and after reading from the memory cell at the final address, the RRR2 of the OR circuit of the read row shift register section 10 and the read column shift register section 12 is read. The signal (the row-direction read cyclic shift register signal) and the RCR2 signal (the column-direction read cyclic shift register signal) are input with the “H” level, whereby the read operation is performed cyclically.

As described above, according to the first embodiment, O
A read row shift register section 10 and a write row shift register section 11 each composed of an R circuit and a D-FF circuit;
Column shift register unit 12 and write column shift register unit 13 composed of a circuit, a D-FF circuit, and a selector
Is provided, it is possible to easily configure the address increment operation by the shift operation of the shift register unit, and further, it is possible to configure the shift register unit by the increment of X and Y in the row direction and the column direction. For this reason, the size can be reduced, and the layout for matching the variable capacity can be easily configured.

(Embodiment 2) FIG. 3 shows a read row shift register section, a write row shift register section of a semiconductor memory device which inputs and outputs by a FIFO method according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a read column shift register unit and a write column shift register unit. The circuit diagram shown in FIG. 3 is substantially the same as the configuration of FIG. 2 for describing the first embodiment, and differs from the configuration in that one D-FF corresponds to one row of memory cells. What was selected in the circuit,
One row of memory cells is selected by one D-FF circuit and two AND circuits.

The operation of the semiconductor memory device configured as described above, which inputs and outputs by the FIFO method of the second embodiment, will be described below with reference to the drawings.

First, at the time of a write operation, an "L" level reset signal is input to the NWR terminal (write reset terminal) as in the first embodiment, and the reset signal enters the write control unit 15 to write data. Included row shift register 1
The “H” level is output to the WRR1 (row-direction initial shift register signal) and the WCR1 (column-direction initial shift register signal) of the write column shift register unit 13.
The "H" level signal is input to the D-FF circuit through the OR circuit, and the shift operation is performed in synchronization with the WRCLK signal (row direction writing reference clock) and the WCCLK signal (column direction writing reference clock). Further, the D-FF is generated by the “H” level, the WRCLK signal and the WCCLK signal.
An operation of sequentially selecting two AND circuits connected to the output Q of the circuit is performed. However, the WRCLK signal is 2n
The clock of the cycle of the × WCLK signal (write reference clock) and the clock of the same cycle as the WCLK signal are input to the WCCLK signal.

At first, WW0 (write word line 0) of the write row shift register section 11 is set to the "H" level of the output Q of the D-FF circuit and the WRCLK signal (row direction write reference clock). The “H” level causes the output of the AND circuit to go to the “H” level, and the memory cell in that row is selected. Further, WB0 of the write column shift register unit 13
(Write bit line selector 0) to WB (n-1) (write bit line selector (n-1)) in order from the D-FF
The AND circuit connected to the output Q of the D-FF circuit and the inverter are connected to the input section by the "H" level of the output Q of the circuit and the "H" level and the "L" level of the WCCLK signal (column direction write reference clock). The outputs of the AND circuits are sequentially turned to "H" level, and the selector is opened. By repeating this sequentially, the input data input through the DI terminal (data input terminal) of the interface unit 6 is written into the memory cells of the column in which the selector is opened through the write bit line.

Next, WW1 (write word line 1) is DF
AND “H” level of the output Q of the F circuit and “L” level of the WRCLK signal (row direction write reference clock)
The output of the circuit (with an inverter at the input section) becomes "H" level, and the memory cell in that row is selected. Further WB
0 (write bit line selector 0) to WB (n-1) (write bit line selector (n-1)) in order from DF
Depending on the "H" level of the output Q of the F circuit and the "H" level and "L" level of the WCCLK signal (column-direction write reference clock), the outputs of the AND circuits receiving the output Q of the D-FF circuit are in order. , And the selector is opened. The input data input through the DI terminal (data input terminal) of the interface unit 6 is written into the memory cells in the column where the selector is opened through the write bit line.

In this manner, the write operation is performed on the memory cell of the sequentially incremented address, and after the write operation is performed on the memory cell of the final address, the OR circuit of the write row shift register section 11 and the write column shift register section 13 is written. WRR2 signal (rowwise write cyclic shift resist signal)
When the "H" level is input to the WCR2 signal (column direction write cyclic shift resist signal), the write operation is performed cyclically.

Next, in the read operation, when an "L" level reset signal is input to the NRR terminal (read reset terminal), the reset signal enters the read control unit 14, and the RRR1 (row direction) of the read row shift register 10 is read. Read initial shift register signal) and RCR1 (column direction read initial shift register signal) of read column shift register section 12
Output an “H” level. The “H” level signal is input at an “H” level to the D-FF circuit through an OR circuit, and the RRCLK signal (row direction read reference clock) and RC
The "H" level shift operation is performed in synchronization with the CLK signal (column direction read reference clock). An operation of sequentially selecting the two AND circuits is performed according to the “H” level of the output Q of the D-FF circuit and the RRCLK signal (row-direction read reference clock) or the RCCLK signal (column-direction read reference clock). However, the RRCLK signal is 2n ×
A clock of the cycle of the RCLK signal (read reference clock) and a clock of the same cycle as the RCLK signal are input to the RCCLK signal.

As a result, RW0 (read word line 0) of the first read row shift register section 10 outputs the "H" level of the output Q of the D-FF circuit and the "H" level of the RRCLK signal (row direction read reference clock). The output of the AND circuit attains the "H" level according to the "level", and the memory cell in that row is selected. Further, RB0 of the read column shift register unit 12
(Read bit line selector 0) to RB (n-1) (read bit line selector (n-1)) in order from the D-FF
According to the "H" level of the output Q of the circuit and the "H" level and "L" level of the RCCLK signal (column-direction read reference clock), the output of the AND circuit sequentially becomes "H" level, and the selector is opened. Output data is read from the memory cells in the column through the read bit line, and the output data is output to the DO terminal (data output terminal) through the interface unit 6.

Next, the RW of the read row shift register 10
1 (read word line 1), the output of the AND circuit (with an inverter at the input section) becomes "H" by the H level of the output Q of the D-FF circuit and the "L" level of the RRCLK signal (row direction read reference clock). Level, and the memory cells in that row are selected. Then, the read column shift register unit 1
2 RB0 (read bit line selector 0) to RB (n-
1) Up to the (read bit line selector (n-1)), the "H" level of the output Q of the D-FF circuit and the "H" level and "L" of the RCCLK signal (column direction read reference clock) in order.
Depending on the level, the output of the AND circuit becomes "H" level, the selector is opened, the data is read out from the memory cell in that column through the read bit line, and the output data is output to the DO terminal (data output terminal) through the interface unit 6. You.

In this way, the output data is read from the memory cell at the sequentially incremented address, and after reading from the memory cell at the last address, the OR circuit of the read row shift register section 10 and the read column shift register section 12 is read. When an "H" level is input to the RRR2 signal (row-direction read cyclic shift resist signal) and the RCR2 signal (column-direction read cyclic shift resist signal), the read operation is performed cyclically.

As described above, according to the present embodiment, the read row shift register section 10 and the write row shift register section 11 constituted by the OR circuit, the D-FF circuit, and the AND circuit.
And a read column shift register unit 12 and a write column shift register unit 13 each composed of an OR circuit, a D-FF circuit, an AND circuit, and a selector, so that the address increment operation is performed by the shift operation of each shift register unit. Can be easily configured, and the shift register section can be configured with the increase in X and Y in the row direction and the column direction. The layout can be easily configured.

[0040]

As described above, according to the present invention,
A semiconductor memory that performs input / output by an excellent FIFO method that realizes an address increment operation by a shift operation of a shift register unit, and that can be easily configured to have a small-sized and easily laid out layout for matching a variable capacity. There is an effect that the device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to a first embodiment of the present invention, which inputs and outputs by a FIFO method;

FIG. 2 is a diagram illustrating a read-out row shift register unit of a semiconductor memory device which performs input / output by a FIFO method according to the first embodiment of the present invention;
FIG. 2 is a circuit diagram showing a configuration of a write row shift register unit, a read column shift register unit, and a write column shift register unit.

FIG. 3 is a diagram illustrating a read-out row shift register unit of a semiconductor memory device which performs input / output by a FIFO method according to a second embodiment of the present invention;
FIG. 2 is a circuit diagram showing a configuration of a write row shift register unit, a read column shift register unit, and a write column shift register unit.

FIG. 4 is a block diagram of a conventional dual port RAM, a counter circuit, and a semiconductor memory device that performs input / output by a FIFO method using a counter circuit control circuit;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 read row decoder section 3 write row decoder section 4 read column decoder section 5 write column decoder section 6 interface section 7 read counter circuit 8 write counter circuit 9 control section 10 read row shift register section 11 write row Shift register unit 12 Read column shift register unit 13 Write column shift register unit 14 Read control unit 15 Write control unit

Claims (2)

[Claims] 1. A function of sequentially selecting and circulating a memory cell array in which static memory cells are arranged in a matrix of a desired capacity in a row direction and a column direction, and a write word line of a memory cell in a row of the memory cell array. A first shift register, a second shift register having a function of sequentially selecting and cycling a read word line of a memory cell in a row of the memory cell array, and a write bit of a memory cell in a column of the memory cell array. A third shift register having a function of sequentially selecting and circulating lines, a fourth shift register having a function of sequentially selecting and circulating read bit lines of memory cells in a column of the memory cell array, and the first shift register. Independently control the shift register, the second shift register, the third shift register, and the fourth shift register. A semiconductor memory device comprising a circuit for performing the following. 2. A function of controlling a plurality of write word lines by one first shift register, a function of controlling a plurality of read word lines by one second shift register, and a function of controlling a plurality of write bit lines by one. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a function of controlling with three third shift registers and a function of controlling a plurality of read bit lines with one fourth shift register.