JPH11242650A - Interface - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use write data in a complete state at a suitable timing when handling data for plural addresses on a transmitter side as data of one word length on a receiver side, to inhibit the use of write data in an incomplete state, and further to simplify a data exchange configuration for each address. SOLUTION: This interface is provided with a decoder 141 for making the K input of a JK flip-flop(JKFF) 142 high when an address from a D flip-flop(DFF) 111 is a high-order address and making the J input of the JKFF 142 high when the address from the DFF 111 is a low-order address on the other hand, and with a JKFF 142 for generating a use disable control signal to fall at a rising time of a write enable signal when the K input is high and generating a use enable control signal to rise at a rising time of a write enable signal when the J input is high on the other hand.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention resides between a sender and a receiver that handles data for a plurality of addresses handled by the sender as data having a length of one word. It is related to the interface that performs delivery.

[0002]

2. Description of the Related Art Hitherto, in intelligent buildings and the like, a dimming system in which a dimming control circuit manages a lighting state of a large number of lighting devices and the like has been widely adopted. FIG.
FIG. 3 is a schematic configuration diagram of an interface used in the dimming control circuit as described above. The interface 90 is
Address (A), chip select (CS), write enable (W) from central processing unit (CPU) outside (left side)
E) and data (D) are taken in and D flip-flops (DFF) 911, 912, and 9 are sent out in synchronization with the rise of the system clock (CLK).
13 and 914, and a DFF
Each output signal of 911, 912, and 913 is fetched and used for decoding. Write conditions (switching information for the selector 931 and 1 corresponding to the address fetched by the DFF 911)
Decoder 92 that obtains information indicating the face register 933)
, Selectors 931 and 932, and a plurality of registers (DF
F) 933 (indicated by one block and dotted line in FIG. 5) and a plurality of registers (DFF) 934 (indicated by one block and dotted line in FIG. 5). A write holding unit 93 is provided to sequentially fetch and hold data from the DFF 914 in accordance with the output and the system clock.

FIG. 6 is a diagram showing the timing of each input / output signal in the above configuration. The general operation of the interface 90 will be described with reference to this drawing. The address, chip select, and write enable from the CPU are synchronized with the system clock (outputs 911, 912, and 913), and thereafter, the data is used for decoding. Is obtained (92 outputs).

On the other hand, data from the CPU is synchronized with the system clock (914 output), and thereafter, is passed to the first-side register 933 of the plurality of registers 933, which is switched by the selector 931 according to the write condition. Then, it is transmitted according to the system clock (933 output), and is taken in and held by the second-side register 934 corresponding to the first-side register 933 via the selector 932.

As described above, when data from a CPU that is asynchronous with the system clock is used after being synchronized with the system clock, a single register configuration is indicated by "933 output" in FIG. As indicated by the shaded area, there is always a timing at which an indefinite value is written to the output of the first register. When such an output is used as valid data, a problem occurs in which a normal system operation is hindered by the written indefinite value (Japanese Patent Laid-Open No. 2-1).
No. 83844).

Therefore, in the configuration of FIG. 5, in order to prevent such a problem, a DFF 93 is provided for each address.
In this case, a three-sided register of 934 is used, and an undefined value to be written into the first-side register is masked and used as valid data using the condition (913 output) in which the write enable is shifted.

[0007]

However, in the conventional example shown in FIG. 5, for example, the dimming control circuit (recipient) side has two switches.
If byte data is treated as one word length (word), and if the CPU (sender) is composed of an 8-bit CPU operating with one word and one byte, two bytes corresponding to two addresses from the sender Is finally taken into the register 934 corresponding to the two addresses. However, in this case, these registers 9
If the data in these registers 934 is used by the recipient before the data corresponding to the address of the two addresses which is taken later in time,
On the receiving side, since all the data of one word has not been fetched, a normal operation cannot be obtained. Therefore, the data for a plurality of addresses on the sender side is
When the data is handled as word data, the above-described conventional configuration cannot be adopted.

Further, in the above configuration, since two registers are arranged for each address, the ratio of the area occupied by the registers to the entire circuit becomes very large, which causes an increase in chip cost. The present invention has been made in view of the above circumstances, and in a case where data for a plurality of addresses on the sender side is treated as data of one word length on the receiver side, write data in a complete state can be transmitted at a suitable timing. It is another object of the present invention to provide an interface that can be used in a computer, can prohibit the use of write data in an incomplete state, and can simplify a configuration for data transfer for each address.

[0009]

SUMMARY OF THE INVENTION The present invention for solving the above problems is provided between a sender and a receiver which handles data of a plurality of addresses handled by the sender as data of one word length, Address input means for individually transferring a plurality of addresses corresponding to the data of one word length from the sender according to a predetermined order; and A write holding unit for sequentially receiving and holding data corresponding to the address fetched by the address input unit for the transfer in response to a write enable from the sender; Utilizing the order of the addresses, a signal toggling at the write enable edge is generated, and this signal is held by the write holding means. It is obtained by a control means having a JK flip-flop to be transmitted to the receiver side as a control signal indicating the usability of the write data is.

In this configuration, if the address fetched by the address input means is the first address to be fetched for data of one word length, the writing and holding means corresponds to the address of that order. A control signal for inhibiting the use of write data can be generated from the time when data is taken in and held for data transfer, while the address taken in by the address input means is taken in last for data of one word length. If it is a power-of-order address,
From the point in time when the write holding unit takes in and holds the data corresponding to the address of the order for transfer, a control signal for permitting use of the write data can be generated. As a result, when data for a plurality of addresses on the sender side is treated as data of one word length on the receiver side,
It becomes possible to use the write data in an incomplete state at a suitable timing and to prohibit the use of the write data in an incomplete state.

Further, since the control signal has an effect of masking a data change point of data from a sender asynchronous with the receiver, another means for masking becomes unnecessary, and the data for each address is eliminated. The configuration for delivery is simplified. The address input means individually takes in the first and second place addresses corresponding to the data of one word length in this order, and the JK flip-flop uses the address taken in by the address input means as the address. If the address is the first address, a signal which falls at the rising edge of the write enable is generated as the unusable control signal, while the address fetched by the address input means is the second address. In some cases, a signal that rises at the rise of the write enable may be generated as the usable control signal. In this configuration, the write data becomes incomplete and is prohibited from being used when the data corresponding to the first address is taken in and held by the write holding unit for delivery. On the other hand, the data corresponding to the second address is taken into the writing and holding means for delivery and is held at a point in time when the data is held and used at a suitable timing.

The control means may synchronize the control signal with a clock on the receiver side. According to this configuration, a problem that may occur when the control signal is not synchronized with the clock on the receiver side is avoided.

[0013]

FIG. 1 is a schematic configuration diagram showing a first embodiment of the present invention. The interface 10 includes an input unit 11, a decoder 12, a write holding unit 13, and a control unit 14.
And a receiver (for example, a dimming control circuit of a dimming system) that handles two addresses of data handled by the sender as one-word data. And passes data from the sender to the receiver.

The input unit 11 receives two addresses corresponding to one word data on the receiver side from the CPU for each word.
D flip-flop (DFF) as address input means which individually fetches an upper address (ADDRESS1) and a lower address (ADDRESS2) in accordance with a predetermined fetching order and sends out the data in synchronization with the rising edge of the system clock (CLK). And DFFs 112, 113, and 114 that fetch chip select (CS), write enable (WE), and data (D) from the CPU and transmit them in synchronization with the rising edge of the system clock. I have.

The decoder 12 includes DFFs 111, 112,
Each output signal of 113 is fetched and used for decoding to obtain a write condition. This writing condition is switching information used by the selectors 131 and 132 described later, and indicates one of the registers 133 and 134 corresponding to the address fetched by the DFF 111. Write holding unit 1
3 denotes selectors 131 and 132 and a register (DFF)
133, 134, and fetches and holds data from the DFF 114. That is, D
Data from the FF 114 is fetched and held in a register (one of the DFFs 133 and 134) to which the selectors 131 and 132 switch according to the write condition from the decoder 12. In the present embodiment, the final data writing is designed to be performed on the registers 133 and 134 when the write enable rises (see FIG. 2). This is to secure a hold time for address, chip select, data, and the like for write enable.

The control unit 14 includes a decoder 141 and a JK flip-flop (JKFF) 142.
Using the order of the addresses from the DFF 111, a signal that toggles at the edge of the write enable is generated, and this signal is sent to the receiver as a control signal indicating whether or not the write data held in the write holding unit 13 can be used. Is to be sent.

The decoder 141 has a JKFF 142 at the subsequent stage.
If the address from the DFF 111 is an upper address for the K input, a HIGH signal is sent out; otherwise, a LOW signal is sent out.
HIG if the address from F111 is a lower address
An H signal is sent, otherwise a LOW signal is sent (see FIG. 2).

The JKFF 142 receives the K input from the decoder 14.
When the signal is changed to HIGH by the HIGH signal from 1, that is, when the address from the DFF 111 is an upper address, a signal which falls at the rising edge of the write enable is generated as an unusable control signal.
The input is HI by the HIGH signal from the decoder 141.
When the signal becomes GH, that is, when the address from the DFF 111 is a lower address, a signal that rises at the rising edge of the write enable is generated as a usable control signal (see FIG. 2).

As a result, the write data for the two addresses held in the write holding unit 13 is captured at the time when the data corresponding to the upper address is captured and held by the DFF 133 for delivery (t1 in FIG. 2). From the time point), the state becomes incomplete and the use is prohibited by the control signal, while the data corresponding to the lower address is captured and held by the DFF 134 for delivery (t in FIG. 2).
At 2 points), the state becomes complete and the control signal permits the use at a suitable timing. That is, when the control signal is LOW, the use of the write data is prohibited, and when the control signal is HIGH, the use of the write data is permitted.

Further, since the control signal has an effect of masking a data change point of data from the sender asynchronous with the receiver, the configuration for data transfer for each address is simplified. Becomes For example, when 2-byte data is treated as one word on the receiving side,
8-bit CP that operates on one byte per word on the sender side
U, the write holding unit conventionally has a 32-bit register configuration, whereas in the present embodiment,
The write holding unit 13 has a 16-bit register configuration (17 bits even when the JKFF 142 is added thereto). As described above, the effect that the ratio of the area occupied in the entire circuit of the write register is reduced is obtained.

FIG. 2 is a diagram showing the timing of each input / output signal in the above configuration. The operation of the interface 10 will be described with reference to FIG. When the address, chip select, write enable, and data from the CPU are input to the input unit 11, (A, CS, WE, D)
Synchronizes with the system clock (111, 112, 11
3,114 outputs).

Thereafter, the outputs of the DFFs 111, 112 and 113 are used for decoding to obtain write conditions (12 outputs). Next, the data (output 114) synchronized with the system clock is fetched and held in one of the registers 133 and 134 which is switched by the selectors 131 and 132 in accordance with the write condition. On the other hand, if the address from the DFF 111 is the upper address (111 output), the K input of the JKFF 142 becomes HIGH (K input), and the JKFF 142 generates a signal that falls at the rising edge of the write enable. Then, it is sent to the receiver as an unusable control signal (14 output).

On the other hand, if the address from the DFF 111 is a lower address (111 output), the JKFF1
42 J input becomes HIGH (J input) and JKFF1
At 42, a signal which rises at the rise of the write enable is generated and sent to the receiver as an available control signal (14 outputs). FIG. 3 is a schematic configuration diagram showing a second embodiment of the present invention.

The interface 20 includes an input unit 11, a decoder 12, and a write holding unit 13 as in the first embodiment.
And a control unit 24 having a configuration different from that of the first embodiment. Therefore, the description of the same blocks as those in the first embodiment will be omitted, and only the different blocks will be described.
And a DFF for synchronizing the control signal from the JKFF 142 with the system clock (clock on the receiver side)
243.

The simplification of the register configuration is described below.
Compared with the conventional example as in the first embodiment, the write holding unit 13 has two registers 133 and 134 (16 bits).
On the other hand, the control unit 24 needs the JKFF 142 and the DFF 243 (2 bits), so that
8 bit configuration, about 40% higher than the conventional example of FIG.
The effect of reduction is obtained.

FIG. 4 is a diagram showing the timing of each input / output signal in the above configuration. The operation of the control unit 24 will be described with reference to FIG. If the address from the DFF 111 is an upper address (111 output), the K input of the JKFF 142 becomes HIGH (K input), and the JKFF 142 generates a signal that falls at the rising edge of the write enable (142 output). Next, after synchronizing with the system clock, the generated signal is sent to the receiver as an unusable control signal (24 outputs).

On the other hand, if the address from the DFF 111 is a lower address (output 111), the JKFF 142 J
The input becomes HIGH (J input), and a signal that rises at the rising edge of the write enable is generated by the JKFF 142 (142 output). Next, the generated signal is transmitted to the receiver as an available control signal after being synchronized with the system clock (24 outputs).

This avoids a problem that may occur when the control signal is not synchronized with the clock on the receiver side. As described above, according to the first and second embodiments, for example, in order to realize a high-performance dimming system, a high-performance CPU is added to the dimming control circuit on the receiver side.
However, even if a high-performance CPU is not installed, a CPU having a smaller number of bits (for example, 8-bit CPU) than a receiver-side CPU (for example, 16-bit CPU) is required for a sender that does not require such a highly functional CPU. CPU) can be mounted, and a well-balanced dimming system according to each function can be constructed.

In the first and second embodiments, the receiver connected to the interface 10 handles data of two addresses handled by the sender as one-word data. However, the present invention is not limited to this. The receiver connected to the interface of the present invention may handle data of a plurality of addresses, which is not limited to "2" handled by the sender, as one-word data. in this case,
When the address fetched by the address input means is the first address to be fetched for data of one word length, the control means of the present invention makes the write holding means correspond to the address of the order. From the point in time when data is taken in and held for transfer, a control signal for inhibiting use of write data is generated, while the address taken in by the address input means should be taken in last for data of one word length. If the address is in the order, the write holding unit generates a control signal for permitting use of the write data from the time when the data corresponding to the address in the order is taken in for transfer and held.

[0030]

As is apparent from the above description, according to the first aspect of the present invention, when data for a plurality of addresses on the sender side is treated as data of one word length on the receiver side, complete data is not obtained. The write data in the state can be used at a suitable timing, the use of the write data in the incomplete state can be prohibited, and the configuration for data transfer for each address can be simplified. .

According to the second aspect of the present invention, when data for a plurality of addresses on the sender side is handled as data of one word length on the receiver side, write data in a complete state is used at a suitable timing. In addition to making it possible, it becomes possible to prohibit the use of write data in an incomplete state. According to the third aspect of the invention, it is possible to avoid a problem that may occur when the control signal is not synchronized with the clock of the receiver.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing the timing of each input / output signal in the configuration of FIG.

FIG. 3 is a schematic configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing the timing of each input / output signal in the configuration of FIG. 3;

FIG. 5 is a schematic configuration diagram of a conventional interface.

6 is a diagram showing the timing of each input / output signal in the configuration of FIG.

[Explanation of symbols]

 10, 20 interface 11 input unit 12 decoder 13 write holding unit 14, 24 control unit 141 decoder 142 JKFF 111, 112, 113, 114, 243 DFF 131, 132 selector 133, 134 register (DFF)

Claims (3)

[Claims] An interface that is interposed between a sender and a receiver that handles data for a plurality of addresses handled by the sender as data of one word length, and that transfers data from the sender to the receiver. Address input means for individually receiving a plurality of addresses corresponding to the one-word-length data from the sender in accordance with a predetermined order; and, according to a write enable from the sender, the address input means Write holding means for sequentially taking in and holding data corresponding to the address fetched by the input means for the delivery; and using the order of the address fetched by the address input means to make use of the edge of the write enable. And a control signal for determining whether the signal can be used for the write data held by the write holding means. And control means having a JK flip-flop for sending to the receiver side. 2. The address input means individually takes in first and second addresses corresponding to the data of one word length in this order, and the JK flip-flop is taken in by the address input means. When the address is the first-order address, a signal that falls at the rising edge of the write enable is generated as the unusable control signal, while the address captured by the address input unit is the second control signal. 2. The interface according to claim 1, wherein when the address is a position address, a signal which rises at a rising point of the write enable is generated as the usable control signal. 3. The interface according to claim 2, wherein said control means synchronizes the control signal with a clock of the receiver.