JPH11242629A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a high-speed access without being affected by the worst- performance memory cell an even when poor performance memories are included. SOLUTION: A memory system 100 is provided with a memory 2 equipped with plural memory areas R1-R4 so as to be operated based on the same principle and with an address translation control circuit 1 for translating a logical address to a physical address based on the corresponding relation between address spaces AS1-AS4 in the memory 2 and the plural memory areas R1-R4. In this case, the above correspondent relation is specified based on intrinsic conditions concerning the performance of the memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory system including an address conversion control circuit, and more particularly to a memory system including a plurality of memory areas and having a storage unit operating on the same principle.

[0002]

2. Description of the Related Art Normally, when accessing a memory composed of memory cells operating on the same principle, a CPU sends an address of the memory and a control signal designating an operation such as read / write to the memory. Send out. The memory receives an address sent by the CPU and accesses a memory cell corresponding to the address. At this time, all the memory cells in the memory are used on the assumption that they operate with the same performance.

For example, in a dynamic random access memory having a capacity of 64 megabits (hereinafter referred to as DRAM), all memory cells in the memory are accessed in the same access time and the same data holding time is used. , The refresh operation is performed.

[0004]

However, focusing on the performance of individual memory cells in a memory, the performance of individual memory cells has a wide range. Therefore, in order to satisfy the specifications of the entire memory with all memory cells,
The specification of the entire memory is determined according to the worst-performing memory cell. As a result, there is a problem that even if a high-performance memory cell exists in the memory, the high-performance memory cell cannot be effectively used. This will be specifically described below.

For example, in a 256 megabit DRAM,
It is known that the performance of individual memory cells in a memory, such as access speed and data retention time, has a large range.

With respect to the access speed, the wiring resistance and the wiring length increase with the thinning of the signal wiring, so that the memory cell arranged closest to the input / output circuit and the memory cell arranged farthest from the input / output circuit are arranged. Since a distance difference occurs between the arranged memory cell and the memory cell itself, even if the access speed of the memory cell itself is the same, the memory cell arranged closest to the input / output circuit and the farthest from the input / output circuit It is known that there is a difference of several nanoseconds in the actual access speed including the distance difference between a memory cell arranged at a position and the memory speed.

When the memory is composed of a plurality of memory chips, the distance between the memory chip mounted closest to the memory control circuit and the memory chip mounted farthest from the memory control circuit is 10 cm. Since the above distance difference occurs, even if the access speed of the memory cell itself is the same, it is mounted at the position farthest from the memory cell and the memory control circuit in the memory chip mounted closest to the memory control circuit. The ability of the access speed including the distance difference between the memory cell and the memory cell in the memory chip is reduced to 0
It is known that a difference of 5 nanoseconds or more occurs.

As described above, when there is a difference in the ability of the access speed of each memory cell in the memory, the specification of the access speed of the entire memory is determined according to the memory cell of the worst access speed.

Regarding the data retention time, a paper by ISSC in 1995 (ISSCC)
As shown in FIG. 2 on page 45, it is known that there is a difference of about 50 times in data retention time between a memory cell having a short data retention time and a memory cell having a long data retention time. I have. When there is a difference in the data holding time of each memory cell in the memory, the specification of the data holding time of the entire memory is determined according to the memory cell having a long data holding time. As the data retention time of the memory cell increases, the power consumption of the memory cell increases.

As described above, the access speed and data retention time of each memory cell in the memory have a wide range from good to bad, so that the operation can be guaranteed even for the memory cell with the worst performance. The specification of the entire memory is determined according to the worst-performing memory cell. As a result, even if a memory cell with a high access speed or a memory cell with a short data retention time exists in the memory, there is a problem that these memory cells cannot be effectively used.

In the future, as the demand for the specification regarding the access speed for the memory further increases, the difference between the width of the variation in the access speed including the influence of the distance difference between the individual memory cells and the access speed required for the memory will increase. It is getting smaller.

For example, a case where a memory which must operate at 1 GHz is to be designed will be described as an example. The access time required when a memory operates at a frequency of 1 GHz is 1 nanosecond. As described above, even if the access speed of the memory cell itself is the same, the memory cell in the memory chip mounted closest to the memory control circuit and the memory cell in the memory chip mounted farthest from the memory control circuit There is a difference of 0.5 nanosecond or more in the ability of the access speed including the distance difference between the two. Therefore, in order for the access speed including the influence of the distance difference between the memory cell having the worst access speed, that is, the memory cell in the memory chip mounted farthest from the memory control circuit, to be 1 nanosecond or less, The access speed of the cell itself must be 1 ns-0.5 ns = 0.5 ns or less. Since it is difficult to manufacture a memory chip having an access speed of the memory cell itself of 0.5 nanoseconds or less at a high yield, the cost of the memory chip increases.

[0013] In the future, as the demand for the specifications of the memory increases, and the width of the variation in the performance ability of each memory cell cannot be ignored with respect to the required specifications,
It is considered that it becomes difficult to satisfy the high required specifications in all the memory cells in the memory.

When the total capacity of the memory increases, a memory cell located far from the input / output circuit and the memory control circuit and a memory cell located closer to the input / output circuit and the memory control circuit become It is thought that it becomes increasingly difficult to satisfy the required specifications in all the memory cells because the difference in the access speed between them becomes even greater.

On the other hand, as the total memory capacity increases, it is unlikely that all memory cells are used for the same purpose. For example, it is considered that a memory cell area where high-speed access is required and a memory cell area where low-speed but long data retention time is required are mixed in the memory area. Furthermore, among the access speeds, it is considered that a memory cell region where random access is required to be fast and a memory cell region where serial access is required to be fast are mixed in the memory region.

It is considered that it becomes increasingly difficult for all the memory cells in the memory to satisfy these various requirements at a high level.

The present invention has been made in view of such problems of the prior art.

An object of the present invention is to provide a memory system capable of operating at a high required specification without being affected by a memory cell having the worst performance.

Another object of the present invention is to provide a memory system capable of high-speed access without being affected by a memory cell having the worst access speed.

Still another object of the present invention is to provide a memory system capable of reducing power consumption without being affected by a memory cell having large power consumption.

[0021]

A memory system according to the present invention includes a plurality of memory areas, and operates according to the same principle. The memory means includes an address space of the memory means and the plurality of memory areas. Address conversion means for converting a logical address to a physical address based on a correspondence between the storage means, and the correspondence is defined based on a unique condition relating to the performance of the storage means. This achieves the above object.

The correspondence may define that a continuous area included in the address space is allocated to one of the plurality of memory areas.

[0023] The storage means may include a plurality of memory chips, and the plurality of memory areas may be formed by the plurality of memory chips.

[0024] The storage means may include a single memory chip, and the plurality of memory areas may be formed by the single memory chip.

The address conversion means selects one of the plurality of correspondences between the address space and the plurality of memory areas according to selection information, and the selected correspondence corresponds to the selected correspondence. Conversion means for converting the logical address into the physical address based on the relationship.

[0026] The selecting means includes an associative memory for storing the plurality of correspondences, and an output means for outputting one of the plurality of correspondences stored in the associative memory according to the selection information. May be included.

[0027] The address conversion means may include a compiler for converting a logical address input from an application program into a physical address based on the correspondence.

[0028] The unique condition may include a first unique condition relating to an access speed of the memory and a second unique condition relating to power consumption of the memory.

The first specific conditions include a specific condition relating to a distance difference between the input / output circuit or the address conversion means and the memory cell, a specific condition relating to the level of the operating frequency of the bus, and a specific condition relating to the operating voltage of the bus. The second specific condition may include a specific condition relating to the level of the threshold voltage of the transistor and a specific condition relating to the data retention time during standby.

According to the memory system of the present invention, the address conversion means converts a logical address into a physical address based on the correspondence between the address space of the storage means and the plurality of memory areas. The correspondence is defined based on a unique condition regarding the performance of the storage unit.

Therefore, the memory system can operate with high required specifications without being affected by the memory cell having the worst performance.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the memory system according to the present invention will be described.

With reference to Table 1, specific conditions regarding the performance of the memory in the memory system according to the embodiment of the present invention will be described. The specific conditions regarding the performance of the memory include a specific condition regarding the access speed of the memory and a specific condition regarding the power consumption of the memory. The specific conditions relating to the memory access speed include the specific conditions relating to the distance difference between the input / output circuit or the memory control circuit and the memory cell, the specific conditions relating to the level of the operating frequency of the bus, and the specific conditions relating to the level of the operating voltage of the bus. And The specific conditions regarding the power consumption of the memory include a specific condition regarding the level of the threshold voltage of the transistor and a specific condition regarding the data holding time during standby.

The memory systems according to the first to sixth embodiments relate to specific conditions relating to memory access speed, and the memory systems according to the seventh to eighth embodiments relate to specific conditions relating to memory power consumption.

[0035]

[Table 1] (Embodiment 1) FIG. 1A shows Embodiment 1 of the present invention.
1 shows a configuration of a memory system 100 according to the first embodiment. FIG. 1 (b)
Indicates a state of address conversion by the memory system 100 according to the first embodiment.

Referring to FIG. 1A, memory system 1
00 denotes the CPU 3, the address conversion control circuit 1, and the memory 2.
And The memory 2 includes an input / output circuit 201 and memory regions R1, R2, R3, and R4. The memory cells in the memory regions R1 and R4 are larger than the memory cells in the memory regions R2 and R3 in the input / output circuit 201.
It is located far from

As described above, between the memory cells arranged in the memory regions R2 and R3 near the input / output circuit 201 and the memory cells arranged in the memory regions R1 and R4 far from the input / output circuit 201, Since the distance difference from the output circuit 201 occurs, the memory cells arranged in the memory regions R2 and R3 close to the input / output circuit 201 and the input / output circuit 20 have the same access speed of the memory cell itself.
There is a difference in the ability of the access speed including the distance difference between the memory cells arranged in the memory regions R1 and R4 far from 1. That is, the access speed of the memory cells arranged in the memory regions R1 and R4 is equal to that of the memory regions R2 and R3.
Slower than the access speed of the memory cell arranged in the memory cell.

Referring to FIG. 1 (b), address space 6 of memory 2 includes continuous areas AS1, AS2, AS3 and AS4. The areas AS1 to AS4 and the memory areas R1 to R4 are associated with each other by a correspondence indicated by four arrows. This correspondence is based on the input / output circuit 20.
1 and the memory cells arranged in each of the memory areas R1 to R4. The areas AS1 and AS2 used for high-speed access are arranged at positions close to the input / output circuit 201, and are allocated to memory areas R2 and R3 including memory cells with a high access speed. Areas AS3 and AS4 used for low-speed access are arranged at positions far from input / output circuit 201, and include memory areas R including memory cells having a low access speed.
1 and R4.

The CPU 3 and the address conversion control circuit 1 previously determine a high-speed access area and a low-speed access area in the address space 6 in advance. In the example shown in FIG. 1B, the area AS1 (logical address: 0000-4444) or AS2 (logical address: 4445-8888) is used for high-speed access, and the area AS3 (logical address:
8889 to CCCC) or AS4 (logical address: C
(CCD to FFFF) is determined in advance between the CPU 3 and the address conversion control circuit 1.

When a request for high-speed access is made, the CPU 3 outputs the logical address (0000-8888) corresponding to the area AS1 or AS2 to the address conversion circuit 1 together with a control signal designating a read operation / write operation. When making a request for low-speed access, the CPU 3 outputs a logical address (8889 to FFFF) corresponding to the area AS3 or AS4 to the address conversion circuit 1 together with a control signal designating a read operation / write operation.

The address conversion control circuit 1 converts the logical address output from the CPU 3 into a physical address based on the correspondence shown in FIG.

The address conversion control circuit 1 stores a logical address (0000 to 444) corresponding to the area AS1 or AS2.
4, 4445-8888) from the CPU 3,
The CPU 3 determines that high-speed access is requested, and
The logical address received from U3 is converted into a physical address corresponding to the memory area R2 or R3 including a memory cell with a high access speed.

The address conversion control circuit 1 calculates a logical address (8889 to CCC) corresponding to the area AS3 or AS4.
C, CCCD to FFFF) from the CPU 3,
The CPU 3 determines that low-speed access is requested, and
The logical address received from U3 is converted into a physical address corresponding to the memory area R1 or R4 including a memory cell having a low access speed.

This address conversion is executed based on the algorithm shown in (Equation 1).

[0045]

(Equation 1)

(Embodiment 2) Referring to FIGS.
A memory system 200 according to the second embodiment will be described.

FIG. 2A shows a configuration of a memory system 200 according to the second embodiment. FIG. 2B shows a state of address conversion by the memory system 200. The same elements as those described in FIG. 1 are denoted by the same reference numerals. A detailed description of these will be omitted.

The CPU 3 outputs a mode signal indicating the type of the high-speed access request and the low-speed access request and a logical address to the address conversion circuit 21.

When the CPU 3 makes a request for high-speed access, the mode signal (mode) indicating the high-speed access request
= Mode 1) and any logical address (0000-FFF)
F) are output to the address conversion circuit 21 together with a control signal designating a read operation / write operation. CPU3
When a request for low-speed access is made, a mode signal (mode = mode 2) indicating a low-speed access request and an arbitrary logical address (0000 to FFFF) are read with an address conversion circuit together with a control signal for designating a read operation / write operation. 21.

The address conversion control circuit 21 outputs a mode signal (mode = mode 1) indicating a high-speed access request to the CP.
When received from U3, it converts the logical address received from CPU3 into a physical address corresponding to memory area R2 or R3 containing a memory cell with a high access speed. When receiving a mode signal (mode = mode 2) indicating a low-speed access request from the CPU 3, the address conversion control circuit 21 converts the logical address received from the CPU 3 into a memory region R1 or R4 including a memory cell with a low access speed.
To a physical address corresponding to

This address conversion is executed based on the algorithm shown in (Equation 2).

[0052]

(Equation 2)

The CPU 3 and the address conversion control circuit 21 do not previously determine the high-speed access area and the low-speed access area in the address space 6. C
The address conversion control circuit 21 determines whether the access request from the PU 3 is for high-speed access or low-speed access based on a mode signal output from the CPU 3.

FIG. 2B shows that the CPU 3 makes a low-speed access request to a logical address in the area AS1 and a logical address in the area AS3, and makes a high-speed access request to a logical address in the area AS2 and a logical address in the area AS4. As an example, the areas AS1 to AS4 and the memory area R1
6 shows the correspondence with R4.

Referring to FIGS. 3 and 4, the inside of address conversion control circuit 21 in memory system 200 will be described in detail. FIG. 3 shows a configuration of the address conversion control circuit 21 of the memory system 200. FIG. 4 shows a state of the address conversion by the address conversion circuit 21.

The address conversion control circuit 21 includes a selector 17
And a conversion unit 13. The selecting unit 17 includes the associative memory 10 and the output units 11 and 12. The associative memory 10 includes a mode table 10A for storing performance types (called mode) such as a high-speed access request and a low-speed access request, a head address storage memory 10B for storing a head address Ahead, and a tail address Atai.
and an end address storage memory 10C for storing 1. The conversion unit 13 includes a differentiator 14, a physical address calculator 15, and a tail area determination calculator 16.

The address conversion circuit 21 receives the mode signal output from the CPU 3 and the logical address Alogic. The selecting unit 17 selects a mode corresponding to the input mode signal from the mode table 10A. The selection unit 17 calculates the start address Ah corresponding to the selected mode.
"ead" is selected from the head address storage memory 10B.
The selecting unit 17 outputs the selected head address Ahead to the converting unit 13 via the output unit 11.

The differentiator 14 calculates the difference SAB between the logical address Alogic received from the CPU 3 and the start address Ahead output via the output unit 11. The physical address calculator 15 subtracts the difference SAB from the logical address Alogic, converts the difference SAB into a physical address Add, and outputs the result.

Referring to FIG. 4, address conversion control circuit 2
The details of the address conversion will be described in detail by taking as an example a case where 1 receives a mode signal (mode = mode 1) indicating a high-speed access request and a logical address Alogic (CCCD) from the CPU 3. The difference SAB is calculated from the logical address Alogic (CCCD) to the start address Ahe.
It is obtained by subtracting ad (8888). That is, the difference SAB is obtained by (Equation 3).

[0060]

(Equation 3)

The conversion unit 13 has a logical address Alogic.
The difference SAB (= 4444) is subtracted from (CCCD) and converted to a physical address (8888). Hereafter, CPU3
Until there is a change in the content of the mode signal input to the address conversion control circuit 1 from the logical address Alogic received from the CPU 3, the conversion unit 13 calculates the difference SAB (= 4
444) is repeated, and the operation of converting into a physical address is repeated.

The tail address Atail corresponding to the head address Ahead is output from the tail address storage memory 10C to the conversion unit 13 via the output unit 12. The end address determination operation unit 16 generates and outputs an end address determination signal SG based on the physical address Add output from the physical address operation unit 15 and the end address Atail output via the output unit 12. The end address determination signal SG indicates whether or not the value of the converted physical address Add exceeds the value of the end address Atail, that is, whether or not the memory area corresponding to the input logical address is insufficient. When the memory area runs short (when the end address determination signal SG is no longer 0),
A swap operation must be performed on a hard disk or another memory (or a DRAM). The end address determination signal SG can be used as information for controlling the swap operation.

The start address Ahead and the end address A
The tail may be set when the memory 2 is set up, or may be set each time the power is turned on.

Memory system 2 with added mode signal
00 is particularly effective when the CPU 3 executes many programs at the same time. In the memory system 100 shown in FIG. 1, the logical addresses output when the CPU 3 requests high-speed access are limited to the logical addresses (0000-8888) corresponding to the areas AS1 and AS2.
Logical addresses output when the CPU 3 requests low-speed access are limited to logical addresses (8888 to FFFF) corresponding to the areas AS3 and AS4.

Memory system 2 with added mode signal
00, the CPU 3 can request high-speed access in any of the areas AS1 to AS4,
Slow access can also be requested. When receiving the mode signal indicating the high-speed access request, the address conversion control circuit 21 converts the logical address to a physical address corresponding to the memory area R2 or R3 including the memory cell with a high access speed regardless of the area to which the logical address belongs. Convert. When receiving the mode signal indicating the low-speed access request from the CPU 3, the address conversion control circuit 21 converts the logical address to the physical area corresponding to the memory area R1 or R4 including the memory cell having the slow access speed regardless of the area to which the logical address belongs. Convert to address.

(Embodiment 3) The inside of the memory 2 will be described in detail with reference to FIGS. The memory 2 is composed of a single memory chip. FIG. 5 shows the configuration of the memory 2. FIG. 6 shows a detailed configuration of a peripheral circuit of a memory cell in the memory 2.

The memory 2 has a short data bus 92 and a long data bus 93. As described above, between the memory cells arranged in the memory regions R2 and R3 near the input / output circuit 201 and the memory cells arranged in the memory regions R1 and R4 far from the input / output circuit 201, Since a distance difference from the circuit 201 occurs, the memory cell 9
1 has the same access speed, but the memory cells 91 arranged in the memory areas R2 and R3 near the input / output circuit 201 and the memory area R far from the input / output circuit 201.
1, there is a difference in the ability of the access speed including the distance difference between the memory cell 91 arranged in R4. That is, the access speed of the memory cells 91 arranged in the memory regions R1 and R4 is lower than the access speed of the memory cells 91 arranged in the memory regions R2 and R3.

The short data bus 92 is connected to the memory cells 91 arranged in the areas R2 and R3, which are high-speed access areas. The long data bus 93 is connected to memory cells 91 arranged in regions R1 and R4, which are low-speed access regions. The memory cell 91 is divided into a high-speed access group and a low-speed access group by a short data bus 92 and a long data bus 93 connected thereto.

Since the number of the transistor switches Y0 and Y1 connected to the short data bus 92 is small, the short data bus 92 has a short wiring and a junction of the transistor switches Y0 and Y1 connected to the wiring. The capacity can also be kept small. Therefore, the memory cells 91 connected to the short data bus 92 can be accessed at higher speed. By providing the short data bus 92 and the long data bus 93, a memory cell that needs to execute high-speed access via the short data bus 92 and a memory cell that only needs to execute low-speed access via the long data bus 93 It becomes possible to divide into groups.

Conventionally, since it is difficult to achieve both high capacity and high-speed operation access, a memory system can be designed only at a compromise point. According to the present invention, instead of reducing the number of memory cells 91 connected to the short data bus 92, the memory cells 9 connected to the long data bus 93 are reduced.
The capacity can be increased by increasing the number of 1s. The short data bus 92 has a short wiring and can reduce the junction capacitance, and can create a memory address space that can be accessed at high speed. For this reason, it is possible to achieve both high capacity and high-speed access.

(Embodiment 4) A memory 32 including a plurality of memory chips will be described with reference to FIG.

The memory 32 includes memory chips DRAM0,
It has DRAM1, DRAM2 and DRAM3. Each of the memory chips DRAM0 to DRAM3 is connected to the address conversion control circuit 21 via a common bus 32A. The memory chip DRAM0 is mounted at a position closest to the address conversion control circuit 21. The memory chip DRAM 3 is mounted at a position farthest from the address conversion control circuit 21.

Memory 32 has a plurality of memory chip DRAMs
0 to the DRAM 3, the memory chip DRA mounted closest to the address conversion control circuit 21.
Since a distance difference occurs between M0 and the memory chip DRAM 3 mounted at the position farthest from the address conversion control circuit 21, even if the access speed of the memory cell itself is the same, the distance from the address conversion control circuit 21 is the highest. There is a difference in the ability of the access speed including the distance difference between the memory cell in the memory chip DRAM0 mounted at the closest position and the memory cell in the memory chip DRAM3 mounted at the position farthest from the address conversion control circuit 21. Occurs. The memory chip DRAM0 has the highest access speed. The memory chip DRAM 3 has the slowest access speed.

The memory area corresponding to the memory chip DRAM0 mounted closest to the address conversion control circuit 21 is used for high-speed access. Memory areas corresponding to the memory chips DRAM1 and DRAM2 are used for data retention. Address conversion control circuit 21
Memory chip DRAM3 mounted at the farthest position from
Are used for low-speed access.

The address conversion control circuit 21 outputs a mode signal (mode = mode 1) indicating a high-speed access request to the CP.
When receiving from the U3, the logical address received from the CPU3 is transferred to the memory chip DRAM0 having the highest access speed.
Is converted to a physical address corresponding to the memory area R1.
When receiving a mode signal (mode = mode 2) indicating a low-speed access request from the CPU 3, the address conversion control circuit 21 converts the logical address received from the CPU 3 into a physical address corresponding to the memory area R4 of the memory chip DRAM 3 having the slowest access speed. Convert to When receiving a mode signal (mode = mode 0) indicating a data holding mode request from the CPU 3, the address conversion control circuit 21
The logical addresses received from the CPU 3 are converted into physical addresses corresponding to the memory areas R2 and R3 of the memory chips DRAM2 and DRAM3 used for data retention.

As described above, when a high-speed access request is made, the memory chip DRAM0 which is mounted closest to the address conversion control circuit 21 and has the fastest access speed is used, so that it is mounted farthest from the address conversion control circuit 21. Memory chip DRA with the slowest access speed
The memory access time can be reduced as compared with the case where the specification of the access speed of the entire memory is determined according to M3.

In DRAM 0 mounted closest to address conversion control circuit 21, FIG.
When the memory area is hierarchized into a high-speed access area and a low-speed access area as shown in (1), the categorization of performance such as high-speed access and low-speed access can be performed more finely.

(Embodiment 5) A memory system 500 including a compiler will be described with reference to FIG. 1 and 2 are denoted by the same reference numerals. A detailed description of these will be omitted.

The memory system 500 includes an operating system 4 including a compiler 5, a CPU 3, and a memory 2.
And The program 7 input to the compiler 5 describes the type and logical address of a mode signal indicating a high-speed access request or a low-speed access request.

When a request for high-speed access is made to the program 7, a mode signal (mode = mode 1) indicating a high-speed access request and an arbitrary logical address (000) are set.
0 to FFFF). To make a request for low-speed access, a mode signal (mode = mode 2) indicating a low-speed access request and an arbitrary logical address (000)
0 to FFFF). The mode signal and the logical address described in the program 7 are input to the compiler 5.

When the compiler 5 receives a mode signal (mode = mode 1) indicating a high-speed access request from the program 7, the compiler 5 converts the logical address received from the program 7 into a memory area R including a memory cell with a high access speed.
2 or R3 converted to a physical address corresponding to
Output to 3. When the compiler 5 receives a mode signal (mode = mode 2) indicating a low-speed access request from the program 7, the compiler 5 converts the logical address received from the program 7 into a memory area R including a memory cell with a low access speed.
After converting to a physical address corresponding to 1 or R4, the CPU
Output to 3.

Since the CPU 3 receives the address converted from the logical address to the physical address by the compiler 5, there is no need to provide an address conversion circuit for converting the logical address into the physical address between the CPU 3 and the memory 2. Therefore, the control between the CPU 3 and the memory 2 is simplified, so that the access speed of the memory 2 can be further increased.

Here, what the user describes in the program 7 is the type and logical address of the mode signal indicating the high-speed access request or the low-speed access request. Since the user understands which processing is performed most frequently to access the memory 2 or needs to access the memory at high speed, the user writes the program. It is extremely easy and effective to describe information on the type of mode signal indicating a request.

For example, in a process of only inputting data from a keyboard, a low-speed access is considered to be sufficient.
It is considered that the process of periodically refreshing the memory 2 in the sleep mode requires only very low-speed access.
The user who writes the program also understands that it is necessary to back up data for the resume function using a memory cell having a long data retention time. Further, when performing three-dimensional graphic processing, the user describes information on the type of mode signal indicating a high-speed access request.

If the user obtains information of the physical address corresponding to the performance type such as the high-speed access request or the low-speed access request from the data book or the like, the request relating to the performance type such as the high-speed access request or the low-speed access request is made. It can also be specified directly by calculating the absolute value of the physical address. Even if it is difficult to calculate the absolute value of the physical address of the memory, at least the processing of accessing the memory of the same performance type such as a high-speed access request or a low-speed access request is grouped in an address space as adjacent as possible, By combining with the memory system 100 shown in FIG. 1 or the memory system 200 shown in FIG. 2, it is considered that the absolute value of the physical address of the memory can be obtained by a relatively simple address conversion control circuit.

As described above, according to Embodiments 1 to 5,
When the CPU 3 requests a high-speed access, the address conversion control circuits 1 and 21 store the logical address output by the CPU 3 in the memory area R2 containing the memory cell with a high access speed.
Alternatively, it is converted to a physical address corresponding to R3.

Therefore, it is not necessary to match the access speed of the entire memory to the memory cells of low access speed in the memory regions R 1 and R 4, and the memory cells of high access speed can be changed according to the level of the access request from the CPU 3. A memory cell with a low speed can be used properly.

As a result, the ability of a memory cell having a good access speed can be brought out without being affected by a memory cell having the worst access speed, thereby enabling high-speed access.

When the memory 2 includes a plurality of chips,
Similar effects can be obtained. It is not necessary to match the access speed of the entire memory system with the memory chip having the slowest access speed, and the memory chip having the fast access speed and the memory chip having the slow access speed can be selectively used according to the level of the access request. As a result, the ability of a memory chip having a good access speed can be brought out without being affected by a memory chip having the worst access speed, so that high-speed access is possible.

Further, since the memory chip having the worst access speed can be used for low-speed access, it is not necessary to treat the memory chip as defective. Therefore, the yield of memory chips can be increased while guaranteeing a high access speed level.

Furthermore, the present invention can be applied to a plurality of memory areas in one of the plurality of memory chips.

Here, an example has been described in which the CPU 3 executes an access request to the address conversion control circuits 1 and 21, but the present invention is not limited to this. An access request to the address conversion control circuits 1 and 21 may be executed by a memory controller that controls a cache memory and a main memory, or may be executed by a graphic control LSI and a DSP that performs signal processing.

FIGS. 1 and 2 show an example in which the address conversion control circuits 1 and 21, the CPU 3 and the memory 2 are constituted by separate chips, but the present invention is not limited to this. The address conversion control circuits 1 and 21 may be the same chip as the CPU 3. Address conversion control circuits 1, 21
May be the same chip as the memory 2.

Further, the address conversion algorithms shown in (Equation 1) and (Equation 2) may be realized by dedicated hardware using an ASIC or an FPGA, or may be realized by a general-purpose CPU.
Alternatively, it may be realized by software using a flash memory, a ROM, or the like.

(Embodiment 6) In the example of the memory system described above with reference to FIG. 1 to FIG. 8, the unique condition relating to the access speed indicates that the connection between the input / output circuit (or the address conversion control circuit) and the memory cell is different. Regarding the eigen condition of the distance difference.

With reference to FIG. 9 to FIG. 11, a memory system relating to the unique condition regarding the operating frequency of the bus among the unique conditions regarding the access speed will be described. FIG. 9 shows an example where the memory 2 includes a plurality of memory chips. FIG.
0 and FIG. 11 show an example where the memory 2 consists of a single memory chip.

Referring to FIG. 9, memory 52 includes memory chips DRAM0, DRAM1, DRAM2 and DRA.
M3 is provided. Memory chips DRAM0 to DRAM
Bus 52B connecting the address conversion control circuit 3 to the address conversion control circuit 21
And 52C are provided. Memory chip DRAM
0 is connected to the address conversion control circuit 21 via a bus 52B. The memory chips DRAM1 to DRAM3 are connected to the address conversion control circuit 21 via a common bus 52C. The bus 52B operates at a high frequency.
The bus 52C operates at a low frequency.

The memory chips DRAM0 to DRAM3 are
Depending on whether it is connected to the bus 52A operating at a high frequency or the bus 52B operating at a low frequency,
Uses are defined. Bus 52 operating at high frequency
The memory chip DRAM0 connected to B is used for high-speed access. Bus 52 operating at low frequency
Memory chips DRAM1 to DRAM connected to C
Reference numeral 3 is used for low-speed access or data holding mode.

Referring to FIGS. 10 and 11, memory 6
2 includes a short data bus selection circuit 141A and a long data bus selection circuit 141B. The short data bus selection circuit 141A is connected to the address conversion control circuit 21 via a bus 62B. The long data bus selection circuit 141B is connected to the address conversion control circuit 21 via a bus 62C. The bus 62B operates at a high frequency. The bus 62C operates at a low frequency.

The memory 62 is provided with a short data bus 92 and a long data bus 93. Short data bus 92
Are connected to memory cells 91 arranged in regions R2 and R3, which are high-speed access regions. Long data bus 93
Are connected to memory cells 91 arranged in regions R1 and R4, which are low-speed access regions. The memory cells 91 are divided into a high-speed access group and a low-speed access group depending on which of the short data bus 92 and the long data bus 93 is connected.

The short data bus selection circuit 141A connects the bus 62B operating at a high frequency to the memory cells 91 arranged in the regions R2 and R3 connected to the short data bus 92. The long data bus selection circuit 141B connects the bus 62C operating at a low frequency to the memory cells 91 arranged in the regions R1 and R4 connected to the long data bus 93.

The application of the memory cell is determined depending on whether it is connected to a bus 62B operating at a high frequency or a bus 62C operating at a low frequency. A region R2 connected to a bus 62B operating at a high frequency,
The memory cell 91 arranged in R3 is used for high-speed access. Memory cells 91 arranged in regions R1 and R4 connected to bus 62C operating at a low frequency
Are used for low-speed access.

Referring to FIG. 12, a description will be given of the memory system 690 relating to the unique condition relating to the level of the operating voltage of the bus among the unique conditions relating to the access speed. The memory system 690 is connected to a plurality of devices via buses having different operating voltages.

The address conversion control circuit 21 has a 3V amplitude,
The printer 132 and the hard disk 133 are connected via a bus 135 of 20 MHz. The memory 72 is used as a buffer memory of the printer 132 and the hard disk 133. Since many LSIs manufactured using relatively old generation device technologies remain in printers and hard disks, the operating voltage of the bus must be 3 V or more.

The address conversion control circuit 21 has a 1 V amplitude,
It is connected to the graphic accelerator 131 via a 200 MHz bus 134. Since high-speed graphic accelerators and cache memories are manufactured using advanced device technologies, the operating voltage of the bus is 1
If the voltage is not as low as about V, reliability cannot be guaranteed.

Since the operating voltages of the buses 134 and 135 connected to each other differ depending on the memory area of the memory 72, the interface voltages of the input / output circuits 136 and 137 of the address conversion control circuit 21 need to be different.

The interface voltage of the input / output circuit 136 is set to be compatible with the operating voltage 1 V of the bus 134. The interface voltage of the input / output circuit 137 is set so as to conform to the operating voltage 3V of the bus 135.

The address conversion control circuit 21 operates at the operating voltage 1
V indicates a mode signal indicating a request to access the bus 134
When received from the PU3, the logical address received from the CPU3 is converted into a physical address corresponding to a memory area including a memory cell connected to the bus 134 having an operating voltage of 1V. When receiving from the CPU 3 a mode signal indicating a request for access to the bus 135 having an operation voltage of 3 V, the address conversion control circuit 21 converts the logical address received from the CPU 3 into a memory area including a memory cell connected to the bus 135 having an operation voltage of 3 V. To a physical address corresponding to

Therefore, the memories 72 can be connected separately or simultaneously to the buses 134 and 135 having different operating voltages even if they are constituted by the same chip.

(Embodiment 7) The memory systems according to Embodiments 7 and 8 relate to specific conditions relating to power consumption of a memory.

Referring to FIG. 13, a description will be given of a memory system relating to the unique condition regarding the level of the threshold voltage of the transistor among the unique conditions regarding the power consumption.

The memory 82 includes regions R21 and R31 in which the threshold voltage of the transistor is low (0.1 V),
It includes regions R11 and R41 where the threshold voltage of the transistor is high (0.6 V).

Address conversion control circuit 21 (not shown)
Transmits a mode signal indicating a high threshold voltage operation to the CPU 3.
(Not shown), the logical address received from the CPU 3 is converted into a physical address corresponding to the memory region R11 or R41 where the threshold voltage of the transistor is high (0.6 V). The address conversion control circuit 21 outputs a mode signal indicating a low threshold voltage operation to the CPU.
3, the logical address received from the CPU 3 is converted to the low threshold voltage (0.1 V) of the transistor.
Is converted to a physical address corresponding to the memory area R21 or R31.

When an application program that prioritizes power saving is executed, a memory access area can be designated as an area where the threshold voltage of a transistor is low (0.1 V).

As described above, according to the seventh embodiment, when the CPU 3 requests the low threshold voltage operation, the address conversion control circuit 21 converts the logical address output by the CPU 3 into a transistor having a low threshold voltage. Is converted to a physical address corresponding to the memory area R21 or R31 in which is located.

For this reason, it is not necessary to match the operation of the entire memory to the transistor having a high threshold voltage in the memory regions R11 and R41, and the transistor having a high threshold voltage is used in accordance with the level of an access request from the CPU 3. A transistor having a low threshold voltage can be used properly.

As a result, the capability of the transistor having a low threshold voltage can be brought out without being affected by the transistor having a high threshold voltage, so that the power consumption of the memory can be reduced.

(Embodiment 8) Referring to FIG. 14, a description will be given of a memory system relating to a unique condition for data holding time during standby among unique conditions for power consumption.

FIG. 14A shows the configuration of the memory 92 provided in the memory system regarding the unique conditions for the data retention time during standby. FIG. 14B shows the on / off state of the switch provided in the memory 92 at the time of activation and at the time of standby.

In the memory 92, regions R121 and R121 in which the power supply to the memory cells is turned off during standby.
131 and regions R111 and R141 to which power is supplied to the memory cells even during standby.

DRAMs and SRAMs lose data if the power is turned off. Therefore, when holding data, it is necessary to supply power to the memory cells even during standby. D
In the case of a RAM, a refresh operation is further required, and power consumption during standby is inevitably increased. In memory systems used for devices that run on batteries,
It is necessary to reduce this power consumption. There is no need to hold data in all the memory cells. For example, when it is sufficient to hold only half or one-third of the memory cell data, there is no need to hold the data. When the power supply switch is turned off for the memory area in which the memory cells are arranged, the power consumption during standby can be reduced accordingly.

Address conversion control circuit 21 (not shown)
Converts a logical address received from the CPU 3 into a physical address corresponding to the memory area R111 or R141 to which power is supplied even during standby, when a mode signal indicating an operation based on a long data holding time is received from the CPU 3 (not shown). I do. The address conversion control circuit 21 outputs a mode signal indicating operation with a short data holding time to the CPU.
3, the logical address received from the CPU 3 is converted into a physical address corresponding to the memory area R121 or R131 to which power is not supplied to the memory cell in standby mode.

As described above, according to the present embodiment, address conversion control circuit 21 supplies a logical address output by CPU 3 when CPU 3 requests an operation with a short data holding time, and supplies power to a memory cell during standby. It is converted to a physical address corresponding to the memory area R121 or R131 that is not supplied.

For this reason, the memory regions R111, R141
There is no need to match the operation of the entire memory to the memory cells to which power is supplied even during standby, and according to the level of an access request from the CPU 3, power is also supplied to memory cells to which power is not supplied during standby and to memory cells to which power is supplied during standby. Memory cells can be used properly.

As a result, memory cells to which power is not supplied at the time of standby can be utilized without being affected by the memory cells to which power is supplied at the time of standby, so that power consumption of the memory can be reduced.

This concept has been described in the description of the memory system relating to the intrinsic condition of the high and low threshold voltage of the transistor shown in FIG. 13, but the leakage of the transistor between the region where the low threshold voltage is used and the region where the low threshold voltage is not used is described. The present invention can also be applied to the fact that the standby current accompanying the current differs. In a memory area using a low threshold voltage, the power supply is stopped during standby to prevent the problem of leakage current, and a power supply area is also provided during standby to respond to performance type requirements. it can.

Although FIGS. 13 and 14 have been described by taking as an example the case where the memory is a single memory chip,
The present invention is not limited to this. Similar effects can be obtained when the memory includes a plurality of memory chips. The plurality of memory chips only need to operate based on the same principle. For example, a plurality of memory chips can be configured from among DRAM, SRAM, flash memory, ROM, ferroelectric memory, and the like.

[0128]

As described above, according to the memory system of the present invention, it is allowed to have different performances in the memory space in response to the request of the performance type. The operation can be performed by designating an address space of a memory cell having poor performance.

Therefore, there is an effect that it is possible to operate with a high required specification without being affected by the memory cell having the worst performance.

[Brief description of the drawings]

FIG. 1A is a configuration diagram of a memory system 100 according to a first embodiment of the present invention. FIG. 3B is a diagram illustrating a state of address conversion by the memory system 100.

FIG. 2A shows a memory system 20 according to a second embodiment;
FIG. FIG. 3B is a diagram illustrating a state of address conversion by the memory system 200.

FIG. 3 is a configuration diagram of an address conversion control circuit 21 of the memory system according to the second embodiment.

FIG. 4 is a diagram showing a state of address conversion by an address conversion control circuit 21 of FIG. 3;

FIG. 5 is a configuration diagram of a memory 2 according to a third embodiment.

FIG. 6 is a configuration diagram of a peripheral circuit of a memory cell in a memory 2 according to a third embodiment;

FIG. 7A is an explanatory diagram of a memory system 400 including a memory 32 including a plurality of memory chips according to a fourth embodiment. 8B is a diagram showing a state of address conversion by the address conversion control circuit 21 of FIG.

FIG. 8A is a configuration diagram of a memory system 500 including a compiler according to a fifth embodiment. FIG. 6B is a diagram showing a state of address conversion by the memory system 500.

FIG. 9A shows a memory system 600 according to the sixth embodiment, in which the memory 2 includes a plurality of memory chips in the memory system relating to the unique condition regarding the operating frequency of the bus.
FIG. FIG. 6B is a diagram showing a state of address conversion by the memory system 600.

FIG. 10 shows a memory 2 of a memory system according to the sixth embodiment relating to a unique condition for an operating frequency of a bus.
Is an explanatory diagram of a memory system 650 composed of a single memory chip.

FIG. 11 is an explanatory diagram of a memory 62 in a memory system relating to a unique condition regarding an operating frequency of a bus according to a sixth embodiment.

FIG. 12 is an explanatory diagram of a memory system 690 relating to a unique condition regarding an operating voltage of a bus according to a sixth embodiment.

FIG. 13 is a configuration diagram of a memory 82 provided in a memory system relating to a unique condition regarding a threshold voltage of a transistor according to a seventh embodiment.

FIG. 14A is a configuration diagram of a memory 92 provided in a memory system relating to a unique condition for a data holding time during standby according to an eighth embodiment. FIG. 15B is a diagram showing ON / OFF states of the switches provided in the memory 92 of FIG.

[Explanation of symbols]

1, 21 Address conversion control circuit 2, 32, 52, 62, 72, 82, 92 Memory 32A, 52B, 52C, 62B, 62C, 134, 1
35 bus 3 CPU 4 operating system 5 compiler 7 program 10 associative memory 10A mode table 10B start address storage memory 10C end address storage memory 11 output unit 12 output unit 13 conversion unit 17 selection unit

Claims (9)

[Claims] A storage unit including a plurality of memory areas and operating on the same principle; and a logical address being physically stored on the basis of a correspondence between an address space of the storage means and the plurality of memory areas. A memory system, comprising: an address conversion unit configured to convert an address into an address, wherein the correspondence is defined based on a unique condition regarding performance of the storage unit. 2. The correspondence relationship is that a continuous area included in the address space is one of the plurality of memory areas.
The memory system according to claim 1, wherein the memory system defines that the memory is allocated to one. 3. The memory system according to claim 1, wherein the storage unit includes a plurality of memory chips, and the plurality of memory areas are formed by the plurality of memory chips. 4. The memory system according to claim 1, wherein the storage unit includes a single memory chip, and the plurality of memory areas are formed by the single memory chip. 5. An address conversion unit, comprising: a selection unit that selects one of a plurality of correspondences between the address space and the plurality of memory areas according to selection information; 2. The memory system according to claim 1, further comprising: a conversion unit configured to convert the logical address into the physical address based on the correspondence. 6. The associative memory for storing the plurality of correspondences, and the output means for outputting one of the plurality of correspondences stored in the associative memory in accordance with the selection information. 6. The memory system according to claim 5, comprising: 7. The memory system according to claim 1, wherein said address conversion means includes a compiler for converting a logical address input from an application program into a physical address based on said correspondence. 8. The memory system according to claim 1, wherein the unique condition includes a first unique condition relating to an access speed of the memory and a second unique condition relating to power consumption of the memory. 9. The first unique condition includes a unique condition relating to a distance difference between an input / output circuit or the address conversion means and a memory cell, a unique condition relating to a level of an operating frequency of a bus, and an operation of the bus. Specific conditions relating to the level of the voltage, and the second specific conditions include a specific condition relating to the level of the threshold voltage of the transistor and a specific condition relating to the data retention time during standby.
The memory system according to claim 8.