JPH11242598A - Compiling method and device, object program executing method and device and program storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the vector arithmetic processing speed with mask data following a single loop or a merged loop that is formed in a compiling mode. SOLUTION: A mask generation instruction vgsm(vector generate subarray mask) is outputted when a source program part corresponding to the vector arithmetic with mask data is compiled. The instruction vgsm is a machine instruction which can be directly executed by hardware. That is, the instruction vgsm sets a series part equivalent to the vector length (length of an accessed range) starting at a position that is shown by the value of a gr3 (general-purpose register) at a mask register mr among the series which repeated a basic pattern 1 consisting of the total number of value of gr2 (general-purpose register) after the false value (0) equivalent to the number of value of a gr1 (general-purpose register) continues and then the true value (1) continues. The pattern 1 can also use a series that consists of a prescribed number of truth value and a prescribed number of false value following the truth value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing for outputting a mask generation instruction by compiling a specific portion in a source program corresponding to a vector operation with mask data, and an object. In the data processing for executing a vector operation with mask data based on a mask generation instruction in a program, a mask data generation instruction for shortening a mask data creation processing time is used.

[0002] In this specification, a mask data generation instruction is abbreviated as a "mask generation instruction", and the term "instruction" is used to mean an instruction sequence including a plurality of instructions.

[0003] In a computer of the vector processing system, a vector operation with mask data is executed in the case of, for example, unification of multiple loops or fusion of parallel loops. In order to ensure the effectiveness of this vector operation, it is necessary that no time is required for mask data preparation processing, and the present invention meets such a demand.

[0004]

2. Description of the Related Art FIG. 14 is an explanatory diagram showing an outline of a conventional compile process of unification with a mask. (A) is a prerequisite source program format, and (b) is a compile content (source).
S. image).

The source program is (100 × 100)
Array A, B consisting of a total of 10,000 elements of (2, 2) to (99, 99)
In some cases, 604 elements are multiplied by each other.

FIG. 15 is an explanatory diagram showing a processing procedure corresponding to the compile contents of FIG. 14 (b), and the contents are as follows. (61) Create an array "mask" indicating the mask data. (62) Make a single loop with the rotation speed of (100 × 100),
Outputs an instruction to set a false value (0) to all elements of array mask. (63) Create a double loop having the same structure as the original double loop, and output an instruction to set a true value (1) only to necessary elements of the array mask in the double loop. (64) The original double loop is converted into a single loop structure. The rotation speed at this time is (100 × 100). (65) Insert an IF statement so that the original executable statement in the double loop is executed only when the value of the array mask corresponding to each array element is a true value (1). I do.

FIG. 16 is an explanatory diagram showing an instruction image corresponding to the compile contents of FIG. 14 (b). 71 corresponds to steps (61) and (62), and 72 corresponds to step (63). ), And 73 corresponds to steps (64) and (65).

[0008]

As described above, in the case of the conventional vector processing method with mask data, since the mask data is prepared by executing the loop processing, the mask data is not prepared. Therefore, there is a problem that the vector processing with mask data cannot be efficiently performed due to a long processing time.

Accordingly, in the present invention, there is provided a machine instruction for creating mask data which can be directly executed by hardware, compiling using the mask creating instruction, and executing a mask creating instruction in an object program. Mask data associated with loop integration and loop fusion
It is an object of the present invention to speed up vector arithmetic processing with data.

When the mask creation instruction is applied to loop fusion, the vector computer can be optimized by deleting common formulas in the program after loop fusion and optimizing instruction scheduling. It is intended to further improve the effective performance of the.

[0011]

Means for Solving the Problems In order to achieve this,
In the present invention, a first data portion in which one of a false value and a true value is continued by a predetermined number is followed by a second data portion in which the other of the false value or the true value is continued by a predetermined number. And a compiling method for outputting a mask generation instruction vgsm (see FIG. 1) for setting a predetermined range in the data sequence consisting of the basic patterns as mask data when compiling the source program. And compiling equipment.

The mask generation instruction vgsm is output at the time of compiling a vector operation part with, for example, unification processing of multiple loops and fusion processing of parallel loops.

The compiling apparatus for outputting the mask generation instruction vgsm includes at least a vectorizing unit for outputting a vector operation instruction, and a mask generation instruction output unit. The multi-loop processing includes a single loop with mask data. Single unit with mask that outputs loop operation instructions in the form changed to loop processing.-Fusion unit with mask that outputs loop operation instructions in the form optimized by integrating parallel loop processing. Also has such.

In the present invention, the mask generation instruction vgs
m, a method of executing an object program for generating mask data by executing m, and a mask data generating unit which is an execution subject of an execution mask generating instruction vgsm, and having a mask data based on a mask generating instruction in the object program. Is used.

Further, in the present invention, the following is used: data processing for outputting a mask generation instruction by compiling a specific portion corresponding to a vector operation with mask data in a source program;
A computer-readable program storage medium storing a program for realizing a function of outputting vgsm as a mask generation instruction in a computer. A mask data is stored based on a mask generation instruction in an object program. A computer-readable program storage medium, which is used for data processing for executing a vector operation with data and stores a program for realizing the function of executing vgsm on the computer, is also used. ing.

Since such a mask generation instruction vgsm is used, for example, when executing a program that has been subjected to processing such as unification with masking and fusion with masking by compiling, the time for creating mask data is reduced. ,
The processing time of the entire program is shortened.

When the mask generation instruction vgsm is applied to loop fusion, not only is the vector length increased, but also the instruction scheduling range is expanded, and loading from the same array is shared. Further optimization, such as reducing relatively slow memory accesses, can be expected.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. In the following embodiment, the head position of the target number sequence is expressed as “1” for convenience of explanation.

FIG. 1 is an explanatory diagram showing a mask generation instruction. Mask generation instruction vgsm (vector generate subarr
ay mask) is a machine instruction that can be directly executed by hardware. A number of false values (eg, 0) of the number of values of gr1 (general purpose register) are consecutive, followed by a true value (eg, 1). In a sequence of repeating the basic pattern 1 consisting of the total number of values of gr2 (general purpose register); vector length starting from the position indicated by the value of gr3 (general purpose register) (length of the range to be accessed) ) Is set in the mask register mr as the instruction content. The basic pattern 1 may be a sequence of a predetermined number of true values followed by a predetermined number of false values.

FIG. 2 is an explanatory diagram showing the concept of a mask generation instruction in loop loop unification, and assumes a source program format similar to that of FIG.

Array A is composed of (M * N) elements, and 2
The hatched portion is the loop processing target portion (I2-I1 + 1).
It consists of * (J2-J1 + 1) elements. Also,
3 is an element corresponding to the start position of the basic pattern 1, and 4 is gr.
1 is an element corresponding to the designated position, 5 is an element corresponding to the designated position of gr3, 6 is a designated position of gr2 and the element basic pattern.
The element corresponding to the final position of the element 1 and the element 7 are the elements following the element 5 by the vector length.

In the case of the mask generation instruction vgsm shown in FIG. 2, the vector length is from element 5 (I1, J1) to element 7 (I
2, the number of elements in the solid line portion up to J2) [M * (J2-J1
+1)-(I1-1)-(M-I2)] The value of gr1 is the number of elements from element 3 (I2 + 1, J1-1) to element 4 (I1-1, J1) [(M-I2) +
(I1-1)] The value of gr2 is the number M of elements from element 3 (I2 + 1, J1-1) to element 6 (I2, J1). The value of gr3 is the value of element 3 (I2 + 1, J1-1). The number of elements up to element 5 (I1, J1) [(M−I2) + I
1].

That is, from the element 5 to the element 7 in the sequence of repeating a basic pattern consisting of a false value corresponding to the element 3 to the element 4 and a subsequent true value corresponding to the element 5 to the element 6 This is an instruction to generate the corresponding sequence portion as mask data.

FIG. 3 is an explanatory diagram showing an outline of a compiling procedure for the double loop shown in FIG. 2, and the contents are as follows. (11) Set the vector length to [M * (J2-J1 + 1)-(I1-
1)-(M-I2)]. (12) For the gr1 of the vgsm instruction, [(M-I2) +
(I1-1)] is output. (13) An instruction to set M for gr2 of the vgsm instruction is output. (14) For the gr3 of the vgsm instruction, [(M-I2) + I
1] is output. (15) Output the vgsm instruction. (16) mr (value) is assigned to all operands of the instructions in the loop
Add. This is because mr (the value) generated by the vgsm instruction is used as mask data. (17) Convert a double loop structure into a single loop structure. The processing start position of the one-dimensional array after the conversion is the position of the original element 5, and the loop structure after the conversion corresponds to a form in which the following IF statement is inserted (see FIG. 4). (18) Output a vector instruction by vectorization.

(Equation 1)

FIGS. 4A and 4B are explanatory diagrams showing examples of loop unification using the vgsm instruction. FIG. 4A shows a prerequisite source program format, and FIG. 4B shows a compile output of an instruction image. Is shown.

This is the case where in FIG. 2, M = 100, N = 100, I1 = 2, 12 = 99, J1 = 2, J2 = 99.

FIG. 5 is a block diagram of a compiler when loops are unified, 11 is a source program, 12 is a compiler (compiler), 13 is an object program, 14 is a source program analysis unit, Reference numeral 15 denotes a loop unification unit, 16 denotes a masked unification recognition unit, 17 denotes a mask generation instruction output unit, 18 denotes a masked singletoning execution unit, 19 denotes a vectorization unit, and 20 denotes an object program generation unit. ing.

The source program analysis unit 14 converts the source program 11 into an intermediate text, and the unification with masking recognition unit 16 can perform unification with masking by looking at the type of instructions and the form of operands therein. The loop is taken out.

The mask generation command output unit 17 executes the processing of steps (11) to (15) in FIG. 3, and the unification implementing unit with mask 18 executes the processing of steps (16) and (17) in FIG. Running. The operations of the vectorization unit 19 and the object program generation unit 20 are the same as those of the related art.

FIG. 6 is an explanatory diagram showing an outline of a compiling procedure relating to loop unification, and the contents are as follows. (21) Take out the loop to be compiled and proceed to the next step. (22) judge whether it has the structure of multiple loops,
If “YES”, proceed to the next step; if “NO”, proceed to step (25). (23) Determine whether unification with mask is possible,
If “YES”, proceed to the next step; if “NO”, proceed to step (25). (24) After outputting the mask generation instruction, the unification with the mask is executed, and the process proceeds to the next step. (25) Perform normal vectorization and proceed to the next step. (26) It is determined whether or not the processing for all loops has been completed. If "YES", a series of processing is completed, and "N
If "O", the process returns to step (21).

FIG. 7 is an explanatory diagram showing a source program format used as a premise for explaining loop fusion. For convenience of explanation, the processing element range of each loop is not completely included in the processing element range of another loop, that is, "I3
<I1 <I4 <I2 "or" I1 <I3 <I2 <I
4 ”holds.

The example of the source program is as follows. For each array A and B consisting of 1000 elements, a loop for executing multiplication of each element of 101 to 1000 (I1 to I2). 1 to 900 (I3 To I4) to perform addition of each element.

FIG. 8 is an explanatory diagram showing an outline of a compiling procedure for the parallel loop shown in FIG. 7, and the contents are as follows. (31) Perform normal vectorization. (32) Set the vector length VL to [MAX (I2, I4) -MIN
(I1, I3) +1]. (33) With respect to gr1 of the vgsm instruction, [VL- (I2-I
1 + 1)] is output. (34) An instruction to set VL is output to gr2 of the vgsm instruction. (35) For gr3 of the vgsm instruction, [1: (I1> I3
)] Or [(I4-12 + 1): (I1 <I3
)] Is output. (36) Output the vgsm instruction. (37) For the gr1 of the vgsm instruction, [VL- (I4-I
3 + 1)] is output. (38) An instruction to set VL is output to gr2 of the vgsm instruction. (39) For the gr3 of the vgsm instruction, [(I2-14 +
1): (when I1> I3)] or [1: (I1 <I3
3) is output. (40) Output the vgsm instruction. (41) The value of mr1 (value) generated by the vgsm instruction in step (36) is added to all the operands in the instruction in the first loop.
Add. This is because mr1 is used as mask data. (42) The value of mr2 (value) generated by the vgsm instruction in step (40) is added to all the operands in the instruction in the second loop.
Add. This is because mr2 is used as mask data. (43) Convert the parallel loop structure into a single loop structure. The initial value of the new loop is MIN (I1, I3) and the final value is MA.
X (I2, I4), and the loop structure after the conversion is represented by the following I
It corresponds to the form in which the F sentence was inserted. (44) Perform optimization such as elimination of common expressions and instruction scheduling.

(Equation 2)

FIG. 9 is an explanatory diagram showing an example of loop fusion using the vgsm instruction.
The compile output of the instruction image is shown in each case after loop fusion using the sm instruction and after optimization. The contents of each instruction are the same as those in FIG.

Here, for the multiplication loop of each element of 101 to 1000, "gr1 = 100, gr2 = 1000, gr3 =
Vgsm instruction (mr1) of "1", and "gr1 = 100, gr2 = 1000, gr3 = 10" for the addition processing loop of each element of 1 to 900
The vgsm instruction (mr2) of “1” is used.

In this case, the respective gr1 and gr2 are also optimized at the stage of outputting the vgsm instruction of mr1 and mr2.

In the optimization after the loop fusion, two VLs storing the array B in the vector register vr
One of the oad instructions is deleted, and two vl that store the array C in the vector register vr
One of the oad instructions has been deleted, and the order of the multiplication instruction vmult, the addition instruction vadd, and the multiplication result holding instruction vstore has been changed.

When mr is added to the holding instruction vstore to make it an instruction with mask data, it is optional whether or not to add this to the preceding multiplication instruction vmultit or addition instruction vadd.

FIG. 10 is a configuration diagram of a compiler at the time of loop fusion, wherein 21 is a source program, 22 is a compiler (compiler), 23 is an object program, 24 is a source program analysis unit, 25 is a vectorization unit, 26 is a loop fusion unit, 27 is a fusion recognition unit with mask, 28 is a mask generation instruction output unit, 29 is a fusion execution unit with mask, 30 is an optimization unit, and 31 is an object. Each shows a program generation unit.

The source program analysis unit 24 converts the source program 21 into an intermediate text, and the fusion-with-masking recognizing unit 27 is capable of performing fusion with a mask by looking at the type of instructions and the form of operands in the instruction. The loop is taken out.

The mask generation command output unit 28 executes the processing of steps (33) to (40) in FIG. 8, and the fusion unit with mask 29 executes the processing of steps (41) to (43) of FIG. And
The optimizing unit 30 performs the process of step (44) in FIG. The operations of the vectorizing unit 25 and the object program generating unit 31 are the same as those of the conventional one.

FIG. 11 is an explanatory diagram showing an outline of a compiling procedure relating to loop fusion, and the contents are as follows. (51) Take out the loop to be compiled and proceed to the next step. (52) Perform vectorization and proceed to the next step. (53) Judge whether it has a parallel loop structure,
If “YES”, proceed to the next step; if “NO”, proceed to step (57). (54) Judge whether fusion with mask is possible,
If “YES”, proceed to the next step; if “NO”, proceed to step (57). (55) After outputting a mask generation instruction, fusion with mask is executed, and the process proceeds to the next step. (56) Optimization such as elimination of common expressions after loop fusion and instruction scheduling is performed, and the process proceeds to the next step. (57) It is determined whether or not processing for all loops has been completed. If "YES", a series of processing is completed and "N
If "O", the process returns to step (51).

FIG. 12 is an explanatory diagram showing an object program execution device for executing a mask generation instruction.
Is an object program, 42 is an object program execution device, 43 is a storage unit for holding various instructions and operation data, and 44 is mask data generation for executing a mask generation instruction (vgsm) and outputting mask data. Part 4,
Reference numeral 5 denotes a vector operation unit for executing a vector operation with mask data, and reference numeral 46 denotes a vector operation result holding unit such as a register.

FIG. 13 shows a computer which reads a program from a computer-readable recording medium and executes the program.
51 is an explanatory diagram showing an outline of a computer system, 51 is a computer system, 52 is a main unit incorporating a CPU and a disk drive, etc., 53 is a display for displaying an image according to an instruction from the main unit 52, 54 is a display screen, 55
Is a keyboard for inputting various information to the computer system 51, 56 is a mouse for specifying an arbitrary position on the display screen 54, 57 is an external database (DASD).
And 58, an external database 57.
And 59, a portable storage medium such as a CD-ROM or a floppy disk.

The storage medium for storing the program may be any one of: a database 57 on the program provider side (line destination memory); a portable storage medium 59; and a memory on the main body 52 side. Is loaded into the main unit 52 and executed on its main memory.

[0046]

According to the present invention, such a mask generation instruction v
Compiling using gsm and executing a mask creation instruction in an object program can speed up vector arithmetic processing with mask data accompanying loop unification and loop fusion. it can.

When this mask creation instruction is applied to loop fusion, the vector computer is optimized by deleting common formulas in the program after loop fusion and optimizing instruction scheduling and the like. Can be further improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a mask generation instruction according to the present invention.

FIG. 2 is an explanatory diagram showing the concept of a mask generation instruction in loop unification according to the present invention.

FIG. 3 is an explanatory diagram showing an outline of a compilation procedure for the double loop in FIG. 2;

FIG. 4 is an explanatory diagram showing an example of loop unification using a vgsm instruction according to the present invention.

FIG. 5 is a configuration diagram of a compiler when loops are unified according to the present invention.

FIG. 6 is an explanatory diagram showing an outline of a compiling procedure relating to loop unification of the present invention.

FIG. 7 is an explanatory diagram showing a source program format used as a premise for explaining loop fusion according to the present invention.

FIG. 8 is an explanatory diagram showing an outline of a compiling procedure for the parallel loop shown in FIG. 7;

FIG. 9 is an explanatory diagram showing an example of loop fusion using a vgsm instruction according to the present invention.

FIG. 10 is a configuration diagram of a compiler at the time of loop fusion according to the present invention.

FIG. 11 is an explanatory diagram showing an outline of a compiling procedure relating to loop fusion according to the present invention.

FIG. 12 is an explanatory diagram illustrating an object program execution device that executes a mask generation instruction according to the present invention.

FIG. 13 is an explanatory diagram showing an outline of a computer system for reading and executing a program from a computer-readable recording medium according to the present invention.

FIG. 14 is an explanatory diagram showing an outline of a conventional compile process of unification with a mask.

FIG. 15 is an explanatory diagram showing a processing procedure corresponding to the compile contents of FIG. 14 (b).

FIG. 16 is an explanatory diagram showing an instruction image corresponding to the compile contents of FIG. 14 (b).

[Explanation of symbols]

In FIGS. 1 and 2, 1: a basic pattern gr1: a value (register) for specifying the number of false values (0) of the basic pattern gr2: a value (register) for specifying the total number of basic patterns gr3: value (register) for specifying the start position of mask data 2: part to be subjected to loop processing 3: element corresponding to the start position of basic pattern 4: element corresponding to the specified position of gr1 5: gr3 Element 6 corresponding to the specified position 6: Element corresponding to the specified position of gr2 and the final position of the element basic pattern 7: Element following vector 5 from element 5

Claims (10)

[Claims] 1. A data processing method for outputting a mask generation instruction by compiling a specific portion corresponding to a vector operation with mask data in a source program, the method comprising: The first data in which one of the value or the true value is continued by a predetermined number
A predetermined range in a data sequence consisting of a basic pattern of a data portion and a second data portion in which the other of a false value or a true value is continued by a predetermined number is used as mask data. A compiling method using an instruction for setting. 2. The compiling method according to claim 1, wherein said vector operation is related to a single loop processing of multiple loops. 3. The compiling method according to claim 1, wherein said vector operation is related to parallel loop fusion processing. 4. A data processing apparatus for outputting a mask generation instruction by compiling a specific portion corresponding to a vector operation with mask data in a source program, wherein the vector operation instruction of the specific portion is provided. And a first data in which one of a false value and a true value is continued for a predetermined number of times.
A predetermined range in a data sequence consisting of a basic pattern of a data portion and a second data portion in which the other of a false value or a true value is continued by a predetermined number is used as mask data. And a mask generation command output unit for outputting the mask generation command for setting. 5. A masked unification executing unit for outputting a loop operation instruction in a form in which the multiple loop processing is changed to a single loop processing with mask data. 4. The compiling device according to 4. 6. The compiling device according to claim 4, further comprising a fusion execution unit with a mask for outputting a loop operation instruction in a form optimized by fusing the parallel loop processing. 7. A data processing for outputting a mask generation instruction by compiling a specific portion corresponding to a vector operation with mask data in a source program, wherein the mask generation instruction includes: A first data in which one of a false value and a true value is continued by a predetermined number.
A predetermined range in a data sequence consisting of a basic pattern of a data portion and a second data portion in which the other of a false value or a true value is continued by a predetermined number is used as mask data. A computer readable program storage medium, which stores a program for outputting a setting instruction and for realizing a function in the computer. 8. A data processing method for executing a vector operation with mask data based on a mask generation instruction in an object program, wherein the mask generation instruction causes one of a false value and a true value to continue in a predetermined number. The first date
A predetermined range in a data sequence consisting of a basic pattern of a data portion and a second data portion in which the other of a false value or a true value is continued by a predetermined number is used as mask data. An object program execution method, which is an instruction for setting. 9. A data processing apparatus for executing a vector operation with mask data based on a mask generation instruction in an object program, comprising: a first data in which one of a false value and a true value is continued by a predetermined number;
A predetermined range in a data sequence consisting of a basic pattern of a data portion and a second data portion in which the other of a false value or a true value is continued by a predetermined number is used as mask data. An object program execution device, comprising at least a mask data creation unit for executing the mask generation instruction for setting. 10. A first data which is used for data processing for executing a vector operation with mask data based on a mask generation instruction in an object program, wherein one of a false value and a true value is continued by a predetermined number. −
A predetermined range in a data sequence consisting of a basic pattern of a data portion and a second data portion in which the other of a false value or a true value is continued by a predetermined number is used as mask data. A computer-readable program storage medium, which stores a program for executing the mask generation command for setting and for realizing a function on the computer.