JP2019012324A - compiler - Google Patents

Abstract

To eliminate the limitations on an increase in speed of a method for vectorizing a loop control statement by using a work array.SOLUTION: A computer which generates an object program to a vector computer from a source program comprises: a loop analysis unit which recognizes a loop control statement which repeatedly processes list structure data by analyzing the source program; and a vectorization execution unit which vectorizes the loop control statement. The vectorization execution unit inserts a first program portion and a second program portion into the object program. The first program portion writes the initial address of each node of the list structure data in a vector register, and writes the number of nodes of the list structure data in a scalar register. The second program portion vectorizes the loop control statement, by using the initial address of each node of the list structure data written in the vector register and the number of nodes of the list structure data written in the scalar register.SELECTED DRAWING: Figure 15

Description

  The present invention relates to a compiler, a computer, and a computer code generation method.

  The list structure data is data having a pointer to a structure of the same type as itself as a member, and is also called a self-reference structure. The list structure data is suitable for processing a large amount of data that is frequently added and deleted.

  FIG. 1 is a diagram showing a structure of a list formed by list structure data struct A on a memory. In FIG. 1, one rectangle represents one structure 1-1. Structures are also called nodes. The structure of this example has double type data x, y, z and a pointer next as members. “first” represents the head address of the section of the list structure data “struct A”. addr1,..., addrN represent the head addresses of the respective structures. “last” represents the end address of the section of the list structure data “struct A”.

  FIG. 2 is a diagram illustrating an example of a C language source program having a loop control statement for processing the list structure data struct A. A statement 2-1 is a data declaration statement of the list structure data struct A. The list structure data struct A points to itself recursively. A statement 4-2 is a loop control statement for repeatedly processing the list structure data struct A by following the list.

  For example, Patent Document 1 discloses a compiler that can speed up a program including a loop control statement that processes list structure data struct A as shown in FIG. FIG. 13 is a diagram illustrating a modification result of the loop control statement by the compiler described in Patent Document 1. In FIG. Referring to FIG. 13, the compiler described in Patent Document 1 vectorizes a loop including list structure data by transforming the loop control statement 13-1 into statements 13-2 to 13-5. Here, the sentence 13-2 is a control sentence that counts the number of nodes of the list structure data struct A. A statement 13-3 is a declaration statement that secures a work array on the memory. A statement 13-4 is a control statement for registering the head address of each node of the list structure data struct A in the secured work array. The statement 13-5 is a loop control statement that performs processing equivalent to the original loop control statement 13-1 using a subscript for referring to the array element of the work array.

JP 2003-337707 A

  The compiler described in Patent Document 1 vectorizes a loop control statement that repeatedly processes list structure data by assigning the head address of the list structure data to a work array on the memory. However, since access to the work array on the memory is performed when the program is executed, there is a limit to increasing the execution speed.

  An object of the present invention is to provide a compiler that solves the above-mentioned problem, that is, the problem that the method of vectorizing a loop control statement using a work array has a limitation in speeding up.

A compiler according to one aspect of the present invention
To a computer that generates an object program for a vector computer from a source program,
Processing for recognizing a loop control statement for repeatedly processing list structure data by analyzing the source program;
Let the loop control statement be vectorized,
In the process of vectorization,
During the object program,
A first program part for writing a head address of each node of the list structure data to a vector register, and writing a number of nodes of the list structure data to a scalar register;
A second program part in which the loop control statement is vectorized using the start address of each node of the list structure data written to the vector register and the number of nodes of the list structure data written to the scalar register And
insert.

A computer according to another embodiment of the present invention is also provided.
A computer that generates an object program for a vector computer from a source program,
A loop analysis unit that recognizes a loop control statement that analyzes the source program and repeatedly processes the list structure data;
A vectorization execution unit for vectorizing the loop control statement;
Including
The vectorization execution unit includes the object program,
A first program part for writing a head address of each node of the list structure data to a vector register, and writing a number of nodes of the list structure data to a scalar register;
A second program part in which the loop control statement is vectorized using the start address of each node of the list structure data written to the vector register and the number of nodes of the list structure data written to the scalar register And
Configured to insert.

A computer code generation method according to another aspect of the present invention includes:
A code generation method executed by a computer that generates an object program for a vector computer from a source program,
Recognizing a loop control statement that repeatedly processes list structure data by analyzing the source program,
Vectorize the loop control statement;
In the vectorization,
During the object program,
A first program part for writing a head address of each node of the list structure data to a vector register, and writing a number of nodes of the list structure data to a scalar register;
A second program part in which the loop control statement is vectorized using the start address of each node of the list structure data written to the vector register and the number of nodes of the list structure data written to the scalar register And
insert.

  Since the present invention has the above-described configuration, it is possible to increase the execution speed of the loop control statement as compared with the case where the loop control statement is vectorized using the work arrangement.

It is a figure which shows the structure on the memory of the list | wrist formed by list structure data struct A. FIG. It is a figure which shows an example of the C language source program which has a loop control statement which processes list structure data struct A. FIG. It is explanatory drawing of the process of the vector register which stores each head address of the list structure data to vectorize, and a vector collection command. It is explanatory drawing of the process of the vector register which stores each head address of the list structure data to vectorize, and a vector spread instruction. It is a figure which shows the structural example of the compiler which concerns on the 1st Embodiment of this invention. The figure which shows the structure on the memory of the list | wrist formed by the list structure data which the object of the VLIST2 instruction in the 1st Embodiment of this invention determines the last of the area as NULL (terminal character), and the content of the vector register It is. It is a figure which shows the structure on the memory of the list | wrist formed by list structure data used as the object of the VLIST2 instruction | indication in the 1st Embodiment of this invention, and the content of a vector register. It is a figure which shows the example of the command sequence produced | generated from the source program in the 1st Embodiment of this invention. It is a figure which shows the example of the other instruction sequence produced | generated from the source program in the 1st Embodiment of this invention. It is a figure which shows the example of another instruction sequence produced | generated from the source program in the 1st Embodiment of this invention. It is explanatory drawing of a process of the mask production | generation instruction | indication and mask leading zero count instruction | indication used in the 1st Embodiment of this invention. It is a figure which shows the example of another instruction sequence produced | generated from the source program in the 1st Embodiment of this invention. It is a figure which shows the example of the instruction sequence produced | generated from the source program by the compiler relevant to this invention. It is a figure which shows an example of the hardware constitutions of the computer which implement | achieves the compiler which concerns on the 1st Embodiment of this invention. It is a block diagram of the compiler which concerns on the 2nd Embodiment of this invention.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
[First embodiment]
Referring to FIG. 5, the compiler 5 according to the first embodiment of the present invention translates the source program 5-3 to generate an object code 5-4. The generated object code is executed by a vector computer. Thus, the compiler 5 generates an object program for the vector computer.

  The compiler 5 includes a loop analysis unit 5-1 and a vectorization execution unit 5-2.

  The loop analysis unit 5-1 analyzes the source program 5-3 and determines whether or not the loop including the list structure data can be vectorized. The loop analysis unit 5-1 includes a loop recognizing unit (hereinafter referred to as a recognizing unit) 5-1-1 including list structure data, and a structure analyzing unit for list structure data (hereinafter referred to as a structural analyzing unit) 5-1. -2 and vectorization determination means 5-1-3.

  The recognition unit 5-1-1 detects a loop including the list structure data in the source program 5-3. The structure analysis unit 5-1-2 analyzes the list structure included in the loop detected by the recognition unit 5-1-1. The vectorization determination unit 5-1-3 determines whether the loop detected by the recognition unit 5-1-1 can be vectorized.

  The vectorization execution unit 5-2 vectorizes the loop based on the analysis result of the loop analysis unit 5-1. The vectorization execution unit 5-2 includes a list structure start address / list structure node number acquisition instruction generation unit (hereinafter referred to as a VLIST instruction generation unit) 5-2-1, a vector length load instruction generation unit 5-2-2, A vector collection instruction generation unit 5-2-3, a vector operation instruction generation unit 5-2-4, and a vector diffusion instruction generation unit 5-2-5 are included.

  The VLIST instruction generation means 5-2-1 is a list structure start address / list structure node number acquisition instruction (hereinafter referred to as a VLIST instruction) which is a vector instruction for acquiring the list of list structure start addresses and the number of nodes of list structure data. ) Is generated. The vector length load instruction generating unit 5-2-2 generates a vector length load instruction for setting the number of nodes acquired by the VLIST instruction as a vector length. The vector collection instruction generation unit 5-2-3 generates a vector collection instruction for loading the list structure data on the memory into the vector register. The vector operation instruction generation unit 5-2-4 performs an operation on the data loaded in the vector register, and generates a vector operation instruction for storing the operation result in the vector register. The vector spread instruction generating unit 5-2-5 generates a vector spread instruction for storing the operation result stored in the vector register in the list structure data on the memory.

  The compiler 5 can be realized by an information processing device 14-1 such as a personal computer and a program 14-2 as shown in FIG. The information processing apparatus 14-1 includes an operation input unit 14-1-1 such as a keyboard and a mouse, a screen display unit 14-1-2 such as a liquid crystal display, a communication interface unit 14-1-3, a memory and a hard disk. Storage unit 14-1-4 and the like, and an arithmetic processing unit 14-1-5 such as one or more microprocessors. The program 14-2 is read from an external computer-readable storage medium into the storage unit 14-1-4 when the information processing apparatus 14-1 is started up, and controls the operation of the arithmetic processing unit 14-1-5. Thus, the compiler 5 is realized on the arithmetic processing unit 14-1-5.

<Description of this embodiment>
Next, the operation of the compiler 5 will be described with reference to FIGS.

  FIG. 2 is a C language source program having a loop including list structure data as described above. The loop analysis unit 5-1 of the compiler 5 analyzes the source program 5-3 having such a loop.

  First, the recognition unit 5-1-1 detects a loop having list structure data in the loop, such as the loop control statement 2-2 in FIG. 2, from the source program 5-3.

  Next, the structure analysis unit 5-1-2 analyzes the list structure data included in the detected loop. In the analysis of the list structure data, the position in the list structure data where the pointer pointing to the next node in the list structure data is analyzed is analyzed. In the list structure data shown in FIG. 2, when double type data is 8 bytes, the next located after x, y, z is located at the 24th byte from the head address of the node. That is, in the list structure data shown in FIG. 2, the position of the pointer pointing to the next node is the 24th byte from the head of the node.

  Next, the vectorization determination unit 5-1-3 of the compiler 5 determines whether or not the detected loop can be vectorized. As a condition that can be vectorized, the list structure data, the array, and the definition / reference relationship of the variables in the loop have no dependency that inhibits vectorization.

  When the processing of the loop analysis unit 5-1 ends, the processing by the vectorization execution unit 5-2 is performed. The vectorization execution unit 5-2 vectorizes the loop including the list structure data determined to be vectorizable by the loop analysis unit 5-1, as follows.

  First, the VLIST instruction generation means 5-2-1 generates a VLIST instruction for loading a list of each top address of the list structure data to be vectorized and the number of nodes of the list structure data into a register. By executing this VLIST instruction, each head address of the list structure data to be vectorized is stored in the vector register. For example, when the VLIST instruction is executed on the list structure data in the section from first to last shown in FIG. 3, a list of each head address of the list structure data is stored in the vector register 3-1, as shown in FIG. Stored. Further, the number of nodes of the list structure data is stored in a scalar register (not shown) by the VLIST instruction. Details of the VLIST instruction will be described later.

  Next, the vector length load instruction generation unit 5-2-2 sets the number of nodes obtained by the VLIST instruction as the vector length.

  Next, the vector collection command generation unit 5-2-3 generates a vector collection command. The vector collection instruction is to load data from the memory so that the memory data at the address stored in each element of the vector register is stored in the corresponding element of another vector register. The vector collection instruction generation unit 5-2-3 generates a vector collection instruction designating the vector register 3-1 for storing the list of the top addresses of the list structure data obtained by the VLIST instruction. As a result, as shown in FIG. 3, a vector collection instruction for loading the memory data at the address stored in each element of the vector register 3-1 from the memory 3-2 to the vector register 3-3 is generated.

  Next, the vector operation instruction generation means 5-2-4 executes the vector operation by designating the data loaded to the vector register 3-3 by the vector collection instruction, and stores the result in another vector register. Generate instructions.

  Next, the vector spread instruction generating unit 5-2-5 generates a vector spread instruction. The vector spread instruction stores data in the memory so that the data of the corresponding element of another vector register is stored in the memory area of the address stored in each element of the vector register. The vector diffusion instruction generating means 5-2-5 generates a vector diffusion instruction specifying a vector register for storing the operation result obtained by the vector operation instruction and a vector register for storing the list of the top addresses of the list structure data. As a result, as shown in FIG. 4, the operation result obtained by the vector operation stored in the vector register 4-3 is stored in the memory 4-4 at the head address of the list structure data stored in the vector register 4-1. A vector spread instruction to store in the two areas is generated.

  Next, an example of the VLIST instruction will be described in detail.

<Example 1 of VLIST instruction>
The VLIST instruction (hereinafter referred to as the VLIST1 instruction) of the first example has a total of five registers of% v0,% s0,% s1,% s2, and% s3 in a predetermined field of the operand as follows. It is configured to specify.
VLIST1 instruction% v0,% s0,% s1,% s2,% s3

  % V0 is a vector register for writing the head address of each node of the list structure data. % S0 is a scalar register for writing the number of nodes of list structure data. % S1 is a scalar register indicating the head address (first in FIG. 1) of the section of the list structure data that is the target of the instruction. % S2 is a scalar register that points to the last address (last in FIG. 1) of the section of the list structure data that is the target of the instruction. % S3 is a scalar register indicating the position of the pointer (next in FIG. 1) of the next data in the list structure acquired by the structure analysis unit 5-1-2 of the list structure data to be instructed.

  In the vector computer including the VLIST1 instruction in the instruction set, when the VLIST1 instruction is issued, each node of the list structure data specified by the first, last, and next specified by the scalar registers% s1,% s2, and% s3 The process of acquiring the start address and storing it in the vector register% v0 and the process of counting the number of nodes and storing it in the scalar register% s0 are performed as processes related to one instruction.

<Example 2 of VLIST instruction>
The VLIST instruction (hereinafter referred to as the VLIST2 instruction) of the second example specifies a total of four registers of% v0,% s0,% s1, and% s2 in a predetermined field of the operand as follows: It is configured.
VLIST2 instruction% v0,% s0,% s1,% s2

  % V0 is a vector register for writing the head address of each node of the list structure data. % S0 is a scalar register for writing the number of nodes of list structure data. % S1 is a scalar register indicating the head address (first in FIG. 1) of the section of the risk structure data that is the target of the instruction. % S2 is a scalar register indicating the position (next in FIG. 1) of the pointer of the next data in the list structure acquired by the structure analysis unit 5-1-2 of the list structure data to be instructed. Unlike the VLIST1 instruction in the first example, the VLIST2 instruction does not have an operand indicating the end address (last in FIG. 1) of the section of the list structure data that is the target of the instruction. The reason is that the VLIST2 instruction determines that the end of the section is NULL (terminal character) as indicated by NULL of 6-1 in FIG. As described above, the VLIST2 instruction reduces the number of operands by reducing the number of scalar registers indicating the end address of the section.

  In a vector computer including the VLIST2 instruction in the instruction set, when the VLIST2 instruction is issued, the head address of each node of the list structure data specified by the first and next specified by the scalar registers% s1 and% s2 is obtained. Processing for storing in the vector register% v0 and processing for counting the number of nodes and storing in the scalar register% s0 are performed as processing related to one instruction.

<Example 3 of VLIST instruction>
The VLIST instruction of the third example (hereinafter referred to as VLIST3 instruction) specifies a total of four registers of% v0,% s0,% s1, and% s2 in a predetermined field of the operand as follows: It is configured.
VLIST3 instruction% v0,% s0,% s1,% s2

  % V0 is a vector register for writing the head address of each node of the list structure data. % S0 is a scalar register indicating the head address (first in FIG. 1) of the section of the list structure data. % S1 is a scalar register indicating the end address (last in FIG. 1) of the section of the list structure data. % S2 is a scalar register indicating the position of the next data pointer (next in FIG. 1) in the list structure acquired by the structure analysis means 5-1-2 of the list structure data. Unlike VLIST1 and VLIST2, VLIST3 does not have an operand that specifies a scalar register for writing the number of nodes of list structure data.

  In the vector computer including the VLIST3 instruction in the instruction set, when the VLIST3 instruction is issued, each node of the list structure data specified by the first, last, and next specified by the scalar registers% s0,% s1, and% s2 The process of acquiring the start address and storing it in the vector register% v0 (7-1) as shown in FIG. 7 and the process of making the next element of the end address NULL (terminal character) are in one instruction. This process is performed. Here, the reason why the element next to the end address of the vector register 7-1 is NULL (termination character) is that it is possible to grasp up to which element of the vector register 7-1 the address has been stored. It is to make it. The calculation of the number of nodes is performed by another instruction subsequent to the VLIST3 instruction (details will be described later with reference to FIG. 10).

<Example 4 of VLIST instruction>
The VLIST instruction of the fourth example (hereinafter referred to as VLIST4) is configured to specify a total of three registers of% v0,% s0, and% s1 in a predetermined field of the operand as follows. Yes.
VLIST4 instruction% v0,% s0,% s1

  % V0 is a vector register for writing each head address of the list structure data. % S0 is a scalar register indicating the head address (first in FIG. 1) of the section of the list structure data. % S1 is a scalar register indicating the position of the next data pointer (next in FIG. 1) in the list structure acquired by the structure analysis unit 5-1-2 of the list structure data. The VLIST4 instruction is an example in which the operand of the scalar register indicating the last address of the section (last in FIG. 1) is eliminated from the VLIST3 instruction of the third example. Similarly to the VLIST2 instruction in the second example, the VLIST4 instruction determines the end of the section as NULL (terminal character) and reduces the number of operands.

  In a vector computer including the VLIST4 instruction in the instruction set, when the VLIST4 instruction is issued, the head address of each node of the list structure data specified by the first and next specified by the scalar registers% s0 and% s1 is obtained. The process of storing in the vector register% v0 and the process of setting the element next to the end address to NULL (termination character) are performed as processes related to one instruction. Further, the calculation of the number of nodes is performed by another instruction subsequent to the VLIST4 instruction, similarly to the VLIST3 instruction.

  Next, examples of instruction sequences generated when the source program shown in FIG. 2 is compiled will be described with reference to FIGS. 8 to 10 and FIG.

<Example of instruction sequence 1>
FIG. 8 shows an instruction sequence generated when the VLIST1 instruction is used. The first VLIST1 instruction loads a list of head addresses of each node of the list structure data into the vector register vreg1, and loads the number of the nodes into the scalar register sreg1. The next LVL instruction (vector length load instruction) loads the vector length by specifying the number of nodes by the scalar register sreg1. The next VGT instruction (vector collection instruction) designates the vector register vreg1 and loads the data of x from the memory into the vector register vreg2. The next VADD instruction (vector addition instruction) stores a list of addresses of y in the vector register vreg3. That is, since the data of y is positioned next to x, assuming that the double type is 8 bytes, y is positioned at the 8th byte from the beginning of struct A. For this reason, the operation result obtained by adding 8 to the list (vreg1) of the top address by the VADD instruction is stored in the vector register vreg3. The next VGT instruction specifies the vector register vreg3 and loads y data from the memory into the vector register vreg4. The next VMUL instruction (vector multiplication instruction) multiplies x and y loaded in the vector registers vreg2 and vreg4, and stores the operation result in the vector register vreg5. The next VADD instruction stores a list of z addresses in the vector register vreg6. That is, since the data of z is located at the 16th byte from the head of struct A, the operation result obtained by adding 16 to the list of head addresses is stored in the vector register vreg6. The next VSC instruction (vector spread instruction) designates the vector register vreg6 and stores the multiplication result of the vector register vreg5 in the position of z of each node.

<Example 2 of instruction sequence>
FIG. 9 shows an instruction sequence generated when the VLIST2 instruction is used. Since the end of the list structure data is determined to be NULL (terminal character), the VLIST2 instruction is used. Other than that, it is not different from FIG.

<Example 3 of instruction sequence>
FIG. 10 shows an instruction sequence generated when the VLIST3 instruction is used. As described above, in the VLIST3 instruction, when the list of the top address of the list structure data is loaded into the vector register, the element next to the end address is set to NULL (terminal character). That is, the vector register when the head address of the list structure data is loaded with the VLIST3 instruction is the vector register 11-1 in FIG. 11, and the last element is NULL. Therefore, in the instruction sequence of FIG. An EQ instruction (mask generation instruction) generates a mask in the vector register 11-2 as shown in FIG. VFMK. In the case of the EQ instruction, a mask that is 1 when the element of the vector register vreg1 (11-1) specified in the predetermined field of the operand is equal to NULL, and 0 that is otherwise, is specified by the predetermined field of the operand. Generate to register. Then, the LZVM instruction (mask leading zero count instruction) specifying the generated mask is continued. The LZVM instruction counts how many zeros continue from the beginning of the mask of the vector register 11-2 specified in the predetermined field of the operand, and the number of nodes as the count result is determined in the predetermined field of the operand. The data is stored in the designated scalar register 11-3 (sreg1) in FIG. The subsequent steps are the same as those shown in FIGS.

<Example 4 of instruction sequence>
FIG. 12 shows an instruction sequence generated when the VLIST4 instruction is used. Since the end of the list structure data is determined to be NULL (terminal character), the VLIST4 instruction is used. Other than that, it is not different from FIG.

<Effect of this embodiment>
As described above, according to the present embodiment, it is possible to vectorize a loop control statement including list structure data. The program execution performance can be improved by loop vectorization.

  Further, in Patent Document 1, a work array memory is secured as in sentences 13-3 and 13-4 in FIG. 13, and the head address of each node of list structure data is stored. On the other hand, in the present embodiment, the head address of each node of the list structure data is directly loaded into the vector register. Therefore, it is not necessary to secure memory. Further, since the memory as the work array is replaced with a vector register, data transfer is also performed at high speed.

  In Patent Document 1, the list structure is traced in a loop twice as shown in sentences 13-2 and 13-4 in FIG. 13 for counting the number of nodes in the list structure data and storing the head address. On the other hand, in the present embodiment, the processing can be reduced only by following the list structure once by the VLIST instruction.

  In the present embodiment, various additions and changes can be made based on the above configuration and operation. For example, when the vector length exceeds the maximum vector length (the number of elements of the vector register), the compiler 5 processes the number of nodes of the maximum vector length, and then the tail end of the vector register loaded with the top address of the list structure data. A loop exceeding the maximum vector length is processed by resuming the processing from the node next to the current node.

[Second Embodiment]
Referring to FIG. 15, the computer 15 according to the second embodiment of the present invention performs vectorization execution with the loop analysis unit 15-1 in order to generate an object program 15-4 for the vector computer from the source program 15-3. Part 15-2.

  The loop analysis unit 15-1 analyzes the source program 15-3 and recognizes a loop control statement that repeatedly processes the list structure data. The loop analysis unit 15-1 can be configured in the same manner as the loop analysis unit 5-1, for example, in FIG. 5, but is not limited thereto. The vectorization execution unit 15-2 vectorizes the loop control statement recognized by the loop analysis unit 15-1. The vectorization execution unit 15-2 can be configured, for example, in the same manner as the vectorization execution unit 5-2 in FIG. 5, but is not limited thereto.

  The vectorization execution unit 15-2 is configured to insert a first program part 15-5 and a second program part 15-6 into the object program 15-4. The first program part 15-5 includes an instruction for writing the head address of each node of the list structure data into the vector register and writing the number of nodes of the list structure data into the scalar register. The second program portion 15-6 vectorizes the loop control statement using the head address of each node of the list structure data written in the vector register and the number of nodes of the list structure data written in the scalar register. Yes.

  Next, a code generation method by the computer 15 according to the present embodiment will be described.

  First, the loop analysis unit 15-1 analyzes the source program 15-3 and recognizes a loop control statement that repeatedly processes the list structure data. Next, the vectorization execution unit 15-2 generates an object program 15-4 in which the loop control statement is vectorized. In the vectorization, the first program part 15-5 and the second program part 15-6 are inserted into the object program 15-4.

  As described above, according to the present embodiment, it is possible to increase the execution speed of the loop control statement that repeatedly processes the list structure data, compared to vectorizing the loop control statement using the work array.

  The reason is that the object program 15-4 has a first program part 15-5 for writing the start address of each node of the list structure data to the vector register, and the start address of each node of the list structure data written to the vector register. This is because it includes the second program portion 15-6 that vectorizes the loop control statement using.

  The present invention can be used in the field of HPC (High-Performance-Computing), a computer having a vector processor, and particularly in the field of generating an object program by compiling a source program including a loop control statement for repeatedly processing list structure data. it can.

1-1 ... Structure (node)
2-1 ... link structure data declaration statement 2-2 ... loop control statement 3-1 ... vector register 3-2 ... memory 3-3 ... vector register 4-1 ... vector register 4-2 ... memory 4-3 ... Vector register 5... Compiler 5-1. Loop analysis section 5-1-1... Loop recognition means including list structure data 5-1-2. Structure analysis means for list structure data 5-1-3. 5-2 ... Vectorization execution unit 5-2-1 ... List structure start address / list structure node number acquisition instruction generation means 5-2-2 ... Vector length load instruction generation means 5-2-3 ... Vector collection instruction generation means 5-2-4 Vector calculation instruction generation means 5-2-5 Vector diffusion instruction generation means 5-3 Source program 5-4 Object code 6-1 NULL (Terminal character)
7-1 ... Vector register 11-1 ... Vector register 11-2 ... Mask register 11-3 ... Scalar register 13-1 ... Loop control statements 13-2 to 13-5 ... Statement 14-1 ... Information processing device 14-2 ... Program 14-1-1 ... Operation input unit 14-1-2 ... Screen display unit 14-1-3 ... Communication interface unit 14-1-4 ... Storage unit 14-1-5 ... Operation processing unit 15 ... Computer 15 -1 ... Loop analysis unit 15-2 ... Vectorization execution unit 15-3 ... Source program 15-4 ... Object program 15-5 ... First program part 15-6 ... Second program part

Claims (7)

To a computer that generates an object program for a vector computer from a source program,
Processing for recognizing a loop control statement for repeatedly processing list structure data by analyzing the source program;
Let the loop control statement be vectorized,
In the process of vectorization,
During the object program,
A first program part for writing a head address of each node of the list structure data to a vector register, and writing a number of nodes of the list structure data to a scalar register;
A second program part in which the loop control statement is vectorized using the start address of each node of the list structure data written to the vector register and the number of nodes of the list structure data written to the scalar register And
insert,
compiler. The first program portion includes a first vector instruction;
The first vector instruction is a predetermined field of an operand, a vector register% v0 for writing the head address of each node of list structure data, a scalar register% s0 for writing the number of nodes of list structure data, and list structure data A structure for designating a scalar register% s1 that points to the start address of a section of data, a scalar register% s2 that points to the end address of the section of list structure data, and a scalar register% s3 that points to the position of the pointer of the next data in the list structure It is said that
The compiler according to claim 1. The first program portion includes a second vector instruction;
The second vector instruction is a predetermined field of an operand, a vector register% v0 for writing the head address of each node of list structure data, a scalar register% s0 for writing the number of nodes of list structure data, and risk structure data A scalar register% s1 that points to the head address of the section of, and a scalar register% s2 that points to the position of the next data pointer in the list structure.
The compiler according to claim 1. The first program part includes a third vector instruction, a mask generation instruction, and a mask leading zero count instruction;
The third vector instruction is a predetermined field of the operand, a vector register% v0 for writing the start address and end character indicating the end of each node of the list structure data, and a scalar indicating the start address of the section of the list structure data. The register% s0, the scalar register% s1 indicating the end address of the list structure data section, and the scalar register% s2 indicating the position of the pointer of the next data in the list structure are designated.
The mask generation instruction is configured to designate the vector register% v0 and a register mreg1 for generating a mask in a predetermined field of an operand.
The mask leading zero count instruction is configured to designate a scalar register that stores, as a number of nodes, the register mreg1, a number of consecutive zeros from the top of the mask, in a predetermined field of an operand.
The compiler according to claim 1. The first program part includes a fourth vector instruction, a mask generation instruction, and a mask leading zero count instruction;
The fourth vector instruction is a predetermined field of the operand, a vector register% v0 for writing each head address of the list structure data and a terminal character indicating the end, and a scalar register% indicating the head address of the section of the list structure data s0, and is configured to designate a scalar register% s1 that points to the position of the next data pointer in the list structure (next in FIG. 1).
The mask generation instruction is configured to designate the vector register% v0 and a register mreg1 for generating a mask in a predetermined field of an operand.
The mask leading zero count instruction is configured to designate a scalar register that stores, as a number of nodes, the register mreg1, a number of consecutive zeros from the top of the mask, in a predetermined field of an operand.
The compiler according to claim 1. A computer that generates an object program for a vector computer from a source program,
A loop analysis unit that recognizes a loop control statement that analyzes the source program and repeatedly processes the list structure data;
A vectorization execution unit for vectorizing the loop control statement;
Including
The vectorization execution unit includes the object program,
A first program part for writing a head address of each node of the list structure data to a vector register, and writing a number of nodes of the list structure data to a scalar register;
A second program part in which the loop control statement is vectorized using the start address of each node of the list structure data written to the vector register and the number of nodes of the list structure data written to the scalar register And
Configured to insert,
Computer. A code generation method executed by a computer that generates an object program for a vector computer from a source program,
Recognizing a loop control statement that repeatedly processes list structure data by analyzing the source program,
Vectorize the loop control statement;
In the vectorization,
During the object program,
A first program part for writing a head address of each node of the list structure data to a vector register, and writing a number of nodes of the list structure data to a scalar register;
A second program part in which the loop control statement is vectorized using the start address of each node of the list structure data written to the vector register and the number of nodes of the list structure data written to the scalar register And
insert,
Computer code generation method.

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