JPH11239044A - Duty control circuit - Google Patents
Duty control circuitInfo
- Publication number
- JPH11239044A JPH11239044A JP4058098A JP4058098A JPH11239044A JP H11239044 A JPH11239044 A JP H11239044A JP 4058098 A JP4058098 A JP 4058098A JP 4058098 A JP4058098 A JP 4058098A JP H11239044 A JPH11239044 A JP H11239044A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- triangular wave
- potential
- amplitude center
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、入力信号のデュー
ティを制御するデューティ制御回路に関する。The present invention relates to a duty control circuit for controlling the duty of an input signal.
【０００２】[0002]
【従来の技術】図４に、従来のデューティ制御回路を示
す。入力端子１０１を介して、デューティが５０％でな
い第１の入力クロック信号ＩＮが、バッファ１０５に入
力される。入力端子１０３を介して、第１の入力クロッ
ク信号ＩＮに対し相補的な差動入力である第２の入力ク
ロック信号ＩＮＢが、バッファ１０５に入力される。2. Description of the Related Art FIG. 4 shows a conventional duty control circuit. A first input clock signal IN whose duty is not 50% is input to the buffer 105 via the input terminal 101. A second input clock signal INB, which is a differential input complementary to the first input clock signal IN, is input to the buffer 105 via the input terminal 103.
【０００３】バッファ１０５は、後述する位相差積分回
路１１１からの相互に相補関係にある２個の位相差積分
値に応じて、第１と第２の入力クロック信号ＩＮ、ＩＮ
Ｂのデューティを、ほぼ５０％に補正し、それぞれ第１
の出力信号ＯＵＴと第２の出力信号ＯＵＴＢとして、出
力端子１０７と１０９に出力される。第２の出力信号Ｏ
ＵＴＢは、第１の出力信号ＯＵＴに対し、相補の関係に
ある。The buffer 105 has first and second input clock signals IN and IN in accordance with two mutually complementary phase difference integrated values from a phase difference integration circuit 111 described later.
The duty of B is corrected to approximately 50%,
Are output to the output terminals 107 and 109 as the output signal OUT and the second output signal OUTB. Second output signal O
The UTB has a complementary relationship with the first output signal OUT.
【０００４】位相差積分回路１１１は、第１と第２の出
力信号ＯＵＴ、ＯＵＴＢにより、ハイの期間とローの期
間の差を積分し、相補関係にある２個の位相差積分値
を、バッファ１０５に供給する。A phase difference integration circuit 111 integrates a difference between a high period and a low period based on the first and second output signals OUT and OUTB, and stores two complementary phase difference integrated values in a buffer. 105.
【０００５】[0005]
【発明が解決しようとする課題】従来のデューティ制御
回路では、制御対象となる入力クロック信号のデューテ
ィが一定の場合に効力を発揮し、ほぼ正確に５０％のデ
ューティを持った出力信号が得られる。The conventional duty control circuit is effective when the duty of the input clock signal to be controlled is constant, and an output signal having a duty of approximately 50% can be obtained almost exactly. .
【０００６】しかしながら、この積分型デューティ制御
回路では、制御対象となる入力クロック信号のデューテ
ィが変化する場合には、対処できない。正しい安定動作
点に到達するまでの時間が、一般的に非常に長くなるか
らである。それゆえ、デューティがノイズ等の影響で、
短い期間で変化するような場合（位相差積分回路１１１
の位相差積分にかかる時間より短い場合）、回路自体が
正帰還動作をし、かえってデューティのずれを増幅する
こともあり得る。その結果、システムとして動作マージ
ンをなくしていく結果になる。However, the integral duty control circuit cannot cope with a case where the duty of the input clock signal to be controlled changes. This is because the time required to reach the correct stable operating point is generally very long. Therefore, the duty is affected by noise, etc.
When the phase difference changes in a short period (phase difference integration circuit 111
If the time is shorter than the time required for integrating the phase difference), the circuit itself may perform a positive feedback operation to amplify the duty deviation. As a result, the operation margin of the system is eliminated.
【０００７】そこで本発明は、入力信号のデューティが
短い期間で変化する場合にもデューティ補正を可能にす
るデューティ制御回路を提供することを目的とする。It is an object of the present invention to provide a duty control circuit which enables duty correction even when the duty of an input signal changes in a short period.
【０００８】[0008]
【課題を解決するための手段】任意のデューティを有す
る第１の入力信号と、この第１の入力信号に対し相補的
な差動入力である第２の入力信号とから、前記第１の入
力信号に対応する第１の三角波信号と、前記第２の入力
信号に対応し前記第１の三角波信号に対して相補的な第
２の三角波信号を生成する三角波生成手段と、前記第１
の三角波信号の第１の振幅中心電位を抽出する第１の振
幅中心電位抽出手段と、前記第２の三角波信号の第２の
振幅中心電位を抽出する第２に振幅中心電位抽出手段
と、前記第１と第２の三角波信号の差動増幅を行い、前
記第１の入力信号に対応する第３の三角波信号と、この
第３の三角波信号と相補的な第４の三角波信号を生成
し、前記第３と第４の三角波信号の同相電位が前記第１
の振幅中心電位により調整される第１の差動増幅手段
と、前記第１と第２の三角波信号の差動増幅を行い、前
記第１の入力信号に対応する第５の三角波信号と、この
第５の三角波信号と相補的な第６の三角波信号を生成
し、前記第５と第６の三角波信号の同相電位が前記第２
の振幅中心電位により調整される第２の差動増幅手段と
を具備し、デューティ制御回路の第１と第２の出力端子
から出力される第１と第２の出力三角波信号の組み合わ
せは、所望のデューティに対する前記第１の入力信号の
デューティのずれが、負帰還がかかって低減された前記
第１と第２の差動増幅手段からの前記三角波信号の組み
合わせであることを特徴とする。According to the present invention, a first input signal having an arbitrary duty and a second input signal which is a differential input complementary to the first input signal are obtained from the first input signal. A first triangular wave signal corresponding to a signal, a second triangular wave signal corresponding to the second input signal, and a second triangular wave signal complementary to the first triangular wave signal;
A first amplitude center potential extracting means for extracting a first amplitude center potential of the triangular wave signal; a second amplitude center potential extracting means for extracting a second amplitude center potential of the second triangular wave signal; Differentially amplifying the first and second triangular wave signals to generate a third triangular wave signal corresponding to the first input signal and a fourth triangular wave signal complementary to the third triangular wave signal; The in-phase potential of the third and fourth triangular wave signals is the first
A first differential amplifying means adjusted by the amplitude center potential of the first and second triangular wave signals, and a fifth triangular wave signal corresponding to the first input signal. A sixth triangular wave signal complementary to the fifth triangular wave signal is generated, and the in-phase potential of the fifth and sixth triangular wave signals is changed to the second triangular wave signal.
And a second differential amplifying means adjusted by the amplitude center potential of the first and second output triangular wave signals output from the first and second output terminals of the duty control circuit. Wherein the deviation of the duty of the first input signal with respect to the duty is a combination of the triangular wave signals from the first and second differential amplifying means reduced by negative feedback.
【０００９】[0009]
【発明の実施の形態】図１に、本発明のデューティ制御
回路の第１の実施の形態の構成を示す。図３に、第１の
実施の形態と後述する第２の実施の形態の各構成要素の
出力の波形を示す。FIG. 1 shows the configuration of a first embodiment of a duty control circuit according to the present invention. FIG. 3 shows an output waveform of each component of the first embodiment and a second embodiment to be described later.
【００１０】入力端子１を介して、デューティが５０％
でない第１の入力クロック信号ＩＮが、三角波生成回路
７に供給される。入力端子３を介して、第１の入力クロ
ック信号ＩＮに対し相補的な差動入力である第２の入力
クロック信号ＩＮＢが、三角波生成回路７に供給され
る。The duty is 50% through the input terminal 1.
Is not supplied to the triangular wave generation circuit 7. A second input clock signal INB, which is a differential input complementary to the first input clock signal IN, is supplied to the triangular wave generation circuit 7 via the input terminal 3.
【００１１】三角波生成回路７は、第１の入力クロック
信号ＩＮに対応する第１の三角波信号Ｔを生成して、差
動増幅回路１９の第１の入力端子１３と、差動増幅回路
２７の第３の入力端子２１と、振幅中心電位抽出回路９
に供給する。三角波生成回路７は、また第２の入力クロ
ック信号ＩＮＢに対応し、第１の三角波信号Ｔに対し相
補的な第２の三角波信号ＴＢを生成し、差動増幅回路１
９の第２の入力端子１５と、差動増幅回路２７の第４の
入力端子２３と、振幅中心電位抽出回路１１に供給す
る。The triangular wave generation circuit 7 generates a first triangular wave signal T corresponding to the first input clock signal IN, and outputs the first input terminal 13 of the differential amplifier circuit 19 and the first input terminal 13 of the differential amplifier circuit 27. Third input terminal 21 and amplitude center potential extracting circuit 9
To supply. The triangular-wave generating circuit 7 generates a second triangular-wave signal TB corresponding to the second input clock signal INB and complementary to the first triangular-wave signal T.
9, the fourth input terminal 23 of the differential amplifier circuit 27, and the amplitude center potential extraction circuit 11.
【００１２】振幅中心電位抽出回路９は、低ゲイン増幅
回路であり、第１の三角波信号Ｔの第１の振幅中心電位
Ａを抽出し、差動増幅回路１９の第１の制御端子１７に
供給する。The amplitude center potential extracting circuit 9 is a low gain amplifying circuit, extracts the first amplitude center potential A of the first triangular wave signal T, and supplies the same to the first control terminal 17 of the differential amplifying circuit 19. I do.
【００１３】振幅中心電位抽出回路１１は、低ゲイン増
幅回路であり、第２の三角波信号ＴＢの第２の振幅中心
電位ＡＢを抽出し、差動増幅回路２７の第２の制御端子
２５に供給する。第２の振幅中心電位ＡＢは、第１の振
幅中心電位Ａと相補の関係にある。The amplitude center potential extracting circuit 11 is a low gain amplifying circuit, extracts the second amplitude center potential AB of the second triangular wave signal TB, and supplies the same to the second control terminal 25 of the differential amplifying circuit 27. I do. The second amplitude center potential AB has a complementary relationship with the first amplitude center potential A.
【００１４】差動増幅回路１９は、第１と第２の入力端
子１３、１５から入力された第１と第２の三角波信号
Ｔ、ＴＢの差動増幅を行い、第１の入力クロック信号Ｉ
Ｎに対応するデューティが５０％の第３の三角波信号Ｃ
と、第２の入力クロック信号ＩＮＢに対応し、第１の三
角波信号Ｃに対し相補的でデューティが５０％の第４の
三角波信号ＣＢを出力する。第３と第４の三角波信号
Ｃ、ＣＢの同相電位（振幅中心電位）は、第１の制御端
子１７から供給される第１の振幅中心電位Ａによって、
調整される。第１の出力端子２９には、第１の三角波信
号Ｃが供給される。A differential amplifier circuit 19 performs differential amplification of the first and second triangular wave signals T and TB input from the first and second input terminals 13 and 15, and generates a first input clock signal I.
A third triangular wave signal C having a duty of 50% corresponding to N
And a fourth triangular wave signal CB having a duty ratio of 50%, which is complementary to the first triangular wave signal C and corresponds to the second input clock signal INB. The common-mode potential (amplitude center potential) of the third and fourth triangular wave signals C and CB is determined by the first amplitude center potential A supplied from the first control terminal 17.
Adjusted. The first output terminal 29 is supplied with a first triangular wave signal C.
【００１５】差動増幅回路２７は、第３と第４の入力端
子２１、２３から入力された第１と第２の三角波信号
Ｔ、ＴＢの差動増幅を行い、第１の入力クロック信号Ｉ
Ｎに対応するデューティが５０％の第５の三角波信号Ｅ
と、第２の入力クロック信号ＩＮＢに対応し、第５の三
角波信号Ｅに対し相補的でデューティが５０％の第６の
三角波信号ＥＢを出力しする。第５と第６の三角波信号
Ｅ、ＥＢの同相電位（振幅中心電位）は、制御端子２５
から供給される第２の振幅中心電位ＡＢによって、調整
される。第２の出力端子３１には、第６の三角波信号Ｅ
Ｂが供給される。The differential amplifier circuit 27 performs differential amplification of the first and second triangular wave signals T and TB input from the third and fourth input terminals 21 and 23, and outputs a first input clock signal I.
A fifth triangular wave signal E corresponding to N and having a duty of 50%
And outputs a sixth triangular wave signal EB having a duty of 50%, which is complementary to the fifth triangular wave signal E and corresponds to the second input clock signal INB. The in-phase potential (amplitude center potential) of the fifth and sixth triangular wave signals E and EB is supplied to the control terminal 25
Is adjusted by the second amplitude center potential AB supplied from the controller. The second output terminal 31 has a sixth triangular wave signal E
B is supplied.
【００１６】第１の振幅中心電位Ａが第２の振幅中心電
位ＡＢより高い場合、第３と第４の三角波信号Ｃ、ＣＢ
の同相電位は、第２の振幅中心電位ＡＢが入力されると
仮定した場合に比べて、小さくなる。When the first amplitude center potential A is higher than the second amplitude center potential AB, the third and fourth triangular wave signals C and CB
Are lower than when it is assumed that the second amplitude center potential AB is input.
【００１７】第２の振幅中心電位ＡＢが第１の振幅中心
電位Ａより高い場合、第５と第６の三角波信号Ｅ、ＥＢ
の同相電位は、第１の振幅中心電位Ａが入力されると仮
定した場合に比べて、小さくなる。When the second amplitude center potential AB is higher than the first amplitude center potential A, the fifth and sixth triangular wave signals E, EB
Are smaller than when it is assumed that the first amplitude center potential A is input.
【００１８】第１と第２の出力端子２９、３１から出力
される第３の三角波信号Ｃと第６の三角波信号ＥＢの組
み合わせは、５０％のデューティに対する入力信号のデ
ューティのずれが、負帰還がかかって低減された第１と
第２の差動増幅回路１９、２７の出力信号の組み合わせ
といえる。In the combination of the third triangular wave signal C and the sixth triangular wave signal EB output from the first and second output terminals 29 and 31, the difference between the duty of the input signal and the duty of 50% is negative feedback. Can be said to be a combination of the output signals of the first and second differential amplifier circuits 19 and 27 which are reduced by the application.
【００１９】本実施の形態では、完全な負帰還ループを
形成してはいないので、点線で囲まれたデューティ制御
回路５の１段では、５０％のデューティを保証すること
が出来ない場合がある。In this embodiment, since a complete negative feedback loop is not formed, one stage of the duty control circuit 5 surrounded by a dotted line may not be able to guarantee a duty of 50%. .
【００２０】その場合、デューティ制御回路５を何段か
カスケード接続すれば、５０％のデューティを保証出来
る。In this case, if the duty control circuit 5 is cascaded in several stages, a duty of 50% can be guaranteed.
【００２１】本実施の形態のデューティ制御回路５によ
れば、１サイクル毎のデューティの変化にも追従し得
る。高周波のカップリングノイズなどがのった短い周期
でデューティが変化している信号も、本実施の形態のデ
ューティ制御回路５に通せば、デューティが５０％に補
正出来ることになり、フィルタの役割を果たすことが出
来る。According to the duty control circuit 5 of the present embodiment, it is possible to follow a change in duty for each cycle. If a signal whose duty changes in a short cycle with high-frequency coupling noise or the like is passed through the duty control circuit 5 of the present embodiment, the duty can be corrected to 50%. Can do it.
【００２２】図２に、本発明のデューティ制御回路の第
２の実施の形態の構成を示す。図１と同一構成要素に
は、同一参照符号を付し詳細な説明は省略する。図３
に、各構成要素の出力の波形を示す。FIG. 2 shows the configuration of a second embodiment of the duty control circuit of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. FIG.
Shows the output waveform of each component.
【００２３】第１と第２の入力端子１３、１５の前段
に、レベルシフト回路４１を設ける。レベルシフト回路
４１は、第１と第２の三角波信号Ｔ、ＴＢを、差動増幅
回路１９の入力範囲にマッチさせ、かつ第１の振幅中心
電位Ａとタイミングを合わせる。A level shift circuit 41 is provided before the first and second input terminals 13 and 15. The level shift circuit 41 matches the first and second triangular wave signals T and TB with the input range of the differential amplifier circuit 19 and matches the timing with the first amplitude center potential A.
【００２４】第３と第４の入力端子２１、２３の前段
に、レベルシフト回路４３を設ける。レベルシフト回路
４３は、第１と第２の三角波信号Ｔ、ＴＢを、差動増幅
回路２７の入力範囲にマッチさせ、かつ第２の振幅中心
電位ＡＢとタイミングを合わせる。A level shift circuit 43 is provided in a stage preceding the third and fourth input terminals 21 and 23. The level shift circuit 43 matches the first and second triangular wave signals T and TB with the input range of the differential amplifier circuit 27, and adjusts the timing with the second amplitude center potential AB.
【００２５】第１の出力端子２９からの第３の三角波信
号Ｃと、第２の出力端子３１からの第６の三角波信号Ｅ
Ｂとを、差動増幅回路４５に供給する。差動増幅回路４
５は、第３と第６の三角波信号Ｃ、ＥＢを差動増幅し、
第３の出力端子４７に第１の出力三角信号ＯＵＴを、第
４の出力端子４９に第２の出力三角信号ＯＵＴＢを、そ
れぞれ供給する。The third triangular wave signal C from the first output terminal 29 and the sixth triangular wave signal E from the second output terminal 31
B is supplied to the differential amplifier circuit 45. Differential amplifier circuit 4
5 differentially amplifies the third and sixth triangular wave signals C and EB,
A first output triangular signal OUT is supplied to a third output terminal 47, and a second output triangular signal OUTB is supplied to a fourth output terminal 49.
【００２６】本実施の形態によれば、第１の実施の形態
にくらべ、第１と第２の入力クロック信号のデューティ
を、より５０％に補正可能である。According to the present embodiment, the duties of the first and second input clock signals can be further corrected to 50% as compared with the first embodiment.
【００２７】それでも、本実施の形態も、完全な負帰還
ループを形成してはいないので、点線で囲まれたデュー
ティ制御回路６の１段では、５０％のデューティを保証
することが出来ない場合がある。Nevertheless, also in the present embodiment, since a complete negative feedback loop is not formed, one stage of the duty control circuit 6 surrounded by a dotted line cannot guarantee a 50% duty. There is.
【００２８】その場合、デューティ制御回路５を何段か
カスケード接続すれば、５０％のデューティを保証出来
る。In this case, if the duty control circuit 5 is cascaded in several stages, a duty of 50% can be guaranteed.
【００２９】本実施の形態のデューティ制御回路５によ
れば、１サイクル毎のデューティの変化にも追従し得
る。高周波のカップリングノイズなどがのった短い周期
でデューティが変化している信号も、本実施の形態のデ
ューティ制御回路５に通せば、デューティが５０％に補
正出来ることになり、ある種のフィルタの役割を果たす
ことが出来る。According to the duty control circuit 5 of the present embodiment, it is possible to follow a change in duty for each cycle. A signal whose duty is changed in a short cycle with high frequency coupling noise or the like can be corrected to 50% by passing the signal through the duty control circuit 5 of the present embodiment. Can play a role.
【００３０】[0030]
【発明の効果】以上本発明によれば、入力信号のデュー
ティが短い期間で変化する場合にもデューティ補正が可
能となる。As described above, according to the present invention, duty correction can be performed even when the duty of an input signal changes in a short period.
【図１】本発明のデューティ制御回路の第１の実施の形
態の構成を示す図である。FIG. 1 is a diagram showing a configuration of a first embodiment of a duty control circuit of the present invention.
【図２】本発明のデューティ制御回路の第２の実施の形
態の構成を示す図である。FIG. 2 is a diagram showing a configuration of a second embodiment of the duty control circuit of the present invention.
【図３】図１と図２の各構成要素の出力の信号波形を示
す図である。FIG. 3 is a diagram showing signal waveforms of outputs of respective components of FIGS. 1 and 2;
【図４】従来のデューティ制御回路の構成を示す図であ
る。FIG. 4 is a diagram showing a configuration of a conventional duty control circuit.
５、６・・・デューティ制御回路、７・・・三角波生成
回路、９、１１・・・振幅中心電位抽出回路、１９、２
７、４５・・・差動増幅回路、４１、４３・・・レベル
シフト回路。5, 6: duty control circuit, 7: triangular wave generation circuit, 9, 11: amplitude center potential extraction circuit, 19, 2
7, 45... A differential amplifier circuit, 41, 43... A level shift circuit.
Claims (13)
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成する三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位を抽出する
第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位を抽出する
第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の三角波信号と、この第３
の三角波信号と相補的な第４の三角波信号を生成し、前
記第３と第４の三角波信号の同相電位が前記第１の振幅
中心電位により調整される第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の三角波信号と、この第５
の三角波信号と相補的な第６の三角波信号を生成し、前
記第５と第６の三角波信号の同相電位が前記第２の振幅
中心電位により調整される第２の差動増幅手段とを具備
し、 デューティ制御回路の第１と第２の出力端子から出力さ
れる第１と第２の出力三角波信号の組み合わせは、所望
のデューティに対する前記第１の入力信号のデューティ
のずれが、負帰還がかかって低減された前記第１と第２
の差動増幅手段からの前記三角波信号の組み合わせであ
ることを特徴とするデューティ制御回路。1. A first input signal having an arbitrary duty and a second input signal that is a differential input complementary to the first input signal correspond to the first input signal. A first triangular wave signal, a triangular wave generating means for generating a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal, and a first triangular wave signal of the first triangular wave signal A first amplitude center potential extracting means for extracting a second amplitude center potential of the second triangular wave signal; a first amplitude center potential extracting means for extracting a second amplitude center potential of the second triangular wave signal; A differential amplification of the triangular wave signal is performed, and a third triangular wave signal corresponding to the first input signal and
A first differential amplifying means for generating a fourth triangular wave signal complementary to the first triangular wave signal, wherein an in-phase potential of the third and fourth triangular wave signals is adjusted by the first amplitude center potential; A differential amplification of the first and second triangular wave signals is performed, and a fifth triangular wave signal corresponding to the first input signal and
And a second differential amplifying means for generating a sixth triangular wave signal complementary to the third triangular wave signal and adjusting an in-phase potential of the fifth and sixth triangular wave signals by the second amplitude center potential. The combination of the first and second output triangular wave signals output from the first and second output terminals of the duty control circuit is determined by the difference between the duty of the first input signal with respect to the desired duty and the negative feedback. Said first and second reduced
And a combination of the triangular wave signals from the differential amplifying means.
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成し、前記第１と第２の入力信号のデューティが５
０パーセントを超える場合は、前記第１の三角波信号の
振幅中心電位は前記第２の三角波信号の振幅中心電位よ
り高くなり、前記第１と第２の入力信号のデューティが
５０パーセントに等しい時は、前記第１の三角波信号の
振幅中心電位と前記第２の三角波信号の振幅中心電位が
等しくなることを特徴とする三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位に比例した
電位を出力する第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位に比例した
電位を出力する第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の信号と、この第３の信号
と相補的な第４の信号を生成し、制御端子に入力される
前記第１の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第３と第４の信号の同相電位は前記第１の振幅
中心電位が低い場合より下がる第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の信号と、この第５の信号
と相補的な第６の信号を生成し、制御端子に入力される
前記第２の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第５と第６の信号の同相電位は前記第２の振幅
中心電位が低い場合より下がる第２の差動増幅手段とを
具備し、 前記第３の信号を第１の出力端子に出力する第１の出力
信号とし、前記第６の信号を第２の出力端子に出力する
第２の出力信号とすることを特徴とするデューティ制御
回路。2. A first input signal having an arbitrary duty and a second input signal which is a differential input complementary to the first input signal correspond to the first input signal. A first triangular wave signal and a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal are generated, and the duty of the first and second input signals is 5
When it exceeds 0%, the amplitude center potential of the first triangular wave signal becomes higher than the amplitude center potential of the second triangular wave signal, and when the duty of the first and second input signals is equal to 50%, A triangular wave generating means wherein an amplitude center potential of the first triangular wave signal is equal to an amplitude center potential of the second triangular wave signal; and a proportional to the first amplitude center potential of the first triangular wave signal. A first amplitude center potential extracting means for outputting the obtained potential; a second amplitude center potential extracting means for outputting a potential proportional to a second amplitude center potential of the second triangular wave signal; 2 to generate a third signal corresponding to the first input signal and a fourth signal complementary to the third signal, and input to a control terminal. The first amplitude center potential extracting means If the force potential is high, the in-phase potential of the third and fourth signals is lower than when the first amplitude center potential is low; and the difference between the first and second triangular wave signals. Dynamic amplification to generate a fifth signal corresponding to the first input signal and a sixth signal complementary to the fifth signal, and the second amplitude center potential input to a control terminal A second differential amplifying unit that, when an output potential of the extracting unit is high, an in-phase potential of the fifth and sixth signals is lower than when the second amplitude center potential is low; Is a first output signal output to a first output terminal, and the sixth signal is a second output signal output to a second output terminal.
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成し、前記第１と第２の入力信号のデューティが５
０パーセントを超える場合は、前記第１の三角波信号の
振幅中心電位は前記第２の三角波信号の振幅中心電位よ
り低くなり、前記第１と第２の入力信号のデューティが
５０パーセントに等しい時は、前記第１の三角波信号の
振幅中心電位と前記第２の三角波信号の振幅中心電位が
等しくなることを特徴とする三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位に比例した
電位を出力する第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位に比例した
電位を出力する第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の信号と、この第３の信号
と相補的な第４の信号を生成し、制御端子に入力される
前記第１の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第３と第４の信号の同相電位は前記第１の振幅
中心電位が低い場合より下がる第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の信号と、この第５の信号
と相補的な第６の信号を生成し、制御端子に入力される
前記第２の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第５と第６の信号の同相電位は前記第２の振幅
中心電位が低い場合より下がる第２の差動増幅手段とを
具備し、 前記第４の信号を第１の出力端子に出力する第１の出力
信号とし、前記第５の信号を第２の出力端子に出力する
第２の出力信号とすることを特徴とするデューティ制御
回路。3. A signal corresponding to the first input signal from a first input signal having an arbitrary duty and a second input signal which is a differential input complementary to the first input signal. A first triangular wave signal and a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal are generated, and the duty of the first and second input signals is 5
When it exceeds 0%, the amplitude center potential of the first triangular wave signal is lower than the amplitude center potential of the second triangular wave signal, and when the duty of the first and second input signals is equal to 50%, A triangular wave generating means wherein an amplitude center potential of the first triangular wave signal is equal to an amplitude center potential of the second triangular wave signal; and a proportional to the first amplitude center potential of the first triangular wave signal. A first amplitude center potential extracting means for outputting the obtained potential; a second amplitude center potential extracting means for outputting a potential proportional to a second amplitude center potential of the second triangular wave signal; 2 to generate a third signal corresponding to the first input signal and a fourth signal complementary to the third signal, and input to a control terminal. The first amplitude center potential extracting means If the force potential is high, the in-phase potential of the third and fourth signals is lower than when the first amplitude center potential is low; and the difference between the first and second triangular wave signals. Dynamic amplification to generate a fifth signal corresponding to the first input signal and a sixth signal complementary to the fifth signal, and the second amplitude center potential input to a control terminal A second differential amplifying unit that, when an output potential of the extracting unit is high, an in-phase potential of the fifth and sixth signals is lower than when the second amplitude center potential is low; Is a first output signal output to a first output terminal, and the fifth signal is a second output signal output to a second output terminal.
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成し、前記第１と第２の入力信号のデューティが５
０パーセントを超える場合は、前記第１の三角波信号の
振幅中心電位は前記第２の三角波信号の振幅中心電位よ
り高くなり、前記第１と第２の入力信号のデューティが
５０パーセントに等しい時は、前記第１の三角波信号の
振幅中心電位と前記第２の三角波信号の振幅中心電位が
等しくなることを特徴とする三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位に逆比例し
た電位を出力する第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位に逆比例し
た電位を出力する第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の信号と、この第３の信号
と相補的な第４の信号を生成し、制御端子に入力される
前記第１の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第３と第４の信号の同相電位は前記第１の振幅
中心電位が低い場合より下がる第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の信号と、この第５の信号
と相補的な第６の信号を生成し、制御端子に入力される
前記第２の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第５と第６の信号の同相電位は前記第２の振幅
中心電位が低い場合より下がる第２の差動増幅手段とを
具備し、 前記第４の信号を第１の出力端子に出力する第１の出力
信号とし、前記第５の信号を第２の出力端子に出力する
第２の出力信号とすることを特徴とするデューティ制御
回路。4. A signal corresponding to the first input signal from a first input signal having an arbitrary duty and a second input signal that is a differential input complementary to the first input signal. A first triangular wave signal and a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal are generated, and the duty of the first and second input signals is 5
When it exceeds 0%, the amplitude center potential of the first triangular wave signal becomes higher than the amplitude center potential of the second triangular wave signal, and when the duty of the first and second input signals is equal to 50%, A triangular wave generating means, wherein an amplitude center potential of the first triangular wave signal is equal to an amplitude center potential of the second triangular wave signal; and an inverse of a first amplitude center potential of the first triangular wave signal. A first amplitude center potential extracting unit that outputs a proportional potential; a second amplitude center potential extracting unit that outputs a potential that is inversely proportional to a second amplitude center potential of the second triangular wave signal; And a second triangular signal are differentially amplified to generate a third signal corresponding to the first input signal and a fourth signal complementary to the third signal, which are input to the control terminal. The first amplitude center potential extracting means Is higher, the in-phase potential of the third and fourth signals is lower than when the first amplitude center potential is lower; and the first and second triangular wave signals Differential amplification is performed to generate a fifth signal corresponding to the first input signal and a sixth signal complementary to the fifth signal, and the second amplitude center input to a control terminal is generated. A second differential amplifying unit that, when the output potential of the potential extracting unit is high, the in-phase potential of the fifth and sixth signals is lower than when the second amplitude center potential is low; A duty control circuit comprising: a first output signal for outputting a signal to a first output terminal; and a second output signal for outputting the fifth signal to a second output terminal.
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成し、前記第１と第２の入力信号のデューティが５
０パーセントを超える場合は、前記第１の三角波信号の
振幅中心電位は前記第２の三角波信号の振幅中心電位よ
り高くなり、前記第１と第２の入力信号のデューティが
５０パーセントに等しい時は、前記第１の三角波信号の
振幅中心電位と前記第２の三角波信号の振幅中心電位が
等しくなることを特徴とする三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位に比例した
電位を出力する第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位に比例した
電位を出力する第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の信号と、この第３の信号
と相補的な第４の信号を生成し、制御端子に入力される
前記第１の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第３と第４の信号の同相電位は前記第１の振幅
中心電位が低い場合より上がる第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の信号と、この第５の信号
と相補的な第６の信号を生成し、制御端子に入力される
前記第２の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第５と第６の信号の同相電位は前記第２の振幅
中心電位が低い場合より上がる第２の差動増幅手段とを
具備し、 前記第４の信号を第１の出力端子に出力する第１の出力
信号とし、前記第５の信号を第２の出力端子に出力する
第２の出力三角波信号とすることを特徴とするデューテ
ィ制御回路。5. A first input signal having an arbitrary duty and a second input signal which is a differential input complementary to the first input signal, correspond to the first input signal. A first triangular wave signal and a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal are generated, and the duty of the first and second input signals is 5
When it exceeds 0%, the amplitude center potential of the first triangular wave signal becomes higher than the amplitude center potential of the second triangular wave signal, and when the duty of the first and second input signals is equal to 50%, A triangular wave generating means wherein an amplitude center potential of the first triangular wave signal is equal to an amplitude center potential of the second triangular wave signal; and a proportional to the first amplitude center potential of the first triangular wave signal. A first amplitude center potential extracting means for outputting the obtained potential; a second amplitude center potential extracting means for outputting a potential proportional to a second amplitude center potential of the second triangular wave signal; 2 to generate a third signal corresponding to the first input signal and a fourth signal complementary to the third signal, and input to a control terminal. The first amplitude center potential extracting means When the force potential is high, the in-phase potential of the third and fourth signals is higher than when the first amplitude center potential is low, and the difference between the first and second triangular wave signals. Dynamic amplification to generate a fifth signal corresponding to the first input signal and a sixth signal complementary to the fifth signal, and the second amplitude center potential input to a control terminal A second differential amplifying means for increasing the in-phase potential of the fifth and sixth signals when the output potential of the extracting means is higher than when the second amplitude center potential is low; Is a first output signal output to a first output terminal, and the fifth output signal is a second output triangular wave signal output to a second output terminal.
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成し、前記第１と第２の入力信号のデューティが５
０パーセントを超える場合は、前記第１の三角波信号の
振幅中心電位は前記第２の三角波信号の振幅中心電位よ
り低くなり、前記第１と第２の入力信号のデューティが
５０パーセントに等しい時は、前記第１の三角波信号の
振幅中心電位と前記第２の三角波信号の振幅中心電位が
等しくなることを特徴とする三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位に逆比例し
た電位を出力する第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位に逆比例し
た電位を出力する第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の信号と、この第３の信号
と相補的な第４の信号を生成し、制御端子に入力される
前記第１の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第３と第４の信号の同相電位は前記第１の振幅
中心電位が低い場合より下がる第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の信号と、この第５の信号
と相補的な第６の信号を生成し、制御端子に入力される
前記第２の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第５と第６の信号の同相電位は前記第２の振幅
中心電位が低い場合より下がる第２の差動増幅手段とを
具備し、 前記第３の信号を第１の出力端子に出力する第１の出力
信号とし、前記第６の信号を第２の出力端子に出力する
第２の出力信号とすることを特徴とするデューティ制御
回路。6. A signal corresponding to the first input signal from a first input signal having an arbitrary duty and a second input signal that is a differential input complementary to the first input signal. A first triangular wave signal and a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal are generated, and the duty of the first and second input signals is 5
When it exceeds 0%, the amplitude center potential of the first triangular wave signal is lower than the amplitude center potential of the second triangular wave signal, and when the duty of the first and second input signals is equal to 50%, A triangular wave generating means, wherein an amplitude center potential of the first triangular wave signal is equal to an amplitude center potential of the second triangular wave signal; and an inverse of a first amplitude center potential of the first triangular wave signal. A first amplitude center potential extracting unit that outputs a proportional potential; a second amplitude center potential extracting unit that outputs a potential that is inversely proportional to a second amplitude center potential of the second triangular wave signal; And a second triangular signal are differentially amplified to generate a third signal corresponding to the first input signal and a fourth signal complementary to the third signal, which are input to the control terminal. The first amplitude center potential extracting means Is higher, the in-phase potential of the third and fourth signals is lower than when the first amplitude center potential is lower; and the first and second triangular wave signals Differential amplification is performed to generate a fifth signal corresponding to the first input signal and a sixth signal complementary to the fifth signal, and the second amplitude center input to a control terminal is generated. A second differential amplifying unit that, when the output potential of the potential extracting unit is high, the in-phase potential of the fifth and sixth signals is lower than when the second amplitude center potential is low; A duty control circuit comprising: a first output signal that outputs a signal to a first output terminal; and a second output signal that outputs the sixth signal to a second output terminal.
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成し、前記第１と第２の入力信号のデューティが５
０パーセントを超える場合は、前記第１の三角波信号の
振幅中心電位は前記第２の三角波信号の振幅中心電位よ
り低くなり、前記第１と第２の入力信号のデューティが
５０パーセントに等しい時は、前記第１の三角波信号の
振幅中心電位と前記第２の三角波信号の振幅中心電位が
等しくなることを特徴とする三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位に比例した
電位を出力する第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位に比例した
電位を出力する第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の信号と、この第３の信号
と相補的な第４の信号を生成し、制御端子に入力される
前記第１の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第３と第４の信号の同相電位は前記第１の振幅
中心電位が低い場合より上がる第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の信号と、この第５の信号
と相補的な第６の信号を生成し、制御端子に入力される
前記第２の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第５と第６の信号の同相電位は前記第２の振幅
中心電位が低い場合より上がる第２の差動増幅手段とを
具備し、 前記第３の信号を第１の出力端子に出力する第１の出力
信号とし、前記第６の信号を第２の出力端子に出力する
第２の出力信号とすることを特徴とするデューティ制御
回路。7. A signal corresponding to the first input signal from a first input signal having an arbitrary duty and a second input signal that is a differential input complementary to the first input signal. A first triangular wave signal and a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal are generated, and the duty of the first and second input signals is 5
When it exceeds 0%, the amplitude center potential of the first triangular wave signal is lower than the amplitude center potential of the second triangular wave signal, and when the duty of the first and second input signals is equal to 50%, A triangular wave generating means wherein an amplitude center potential of the first triangular wave signal is equal to an amplitude center potential of the second triangular wave signal; and a proportional to the first amplitude center potential of the first triangular wave signal. A first amplitude center potential extracting means for outputting the obtained potential; a second amplitude center potential extracting means for outputting a potential proportional to a second amplitude center potential of the second triangular wave signal; 2 to generate a third signal corresponding to the first input signal and a fourth signal complementary to the third signal, and input to a control terminal. The first amplitude center potential extracting means When the force potential is high, the in-phase potential of the third and fourth signals is higher than when the first amplitude center potential is low, and the difference between the first and second triangular wave signals. Dynamic amplification to generate a fifth signal corresponding to the first input signal and a sixth signal complementary to the fifth signal, and the second amplitude center potential input to a control terminal A second differential amplifying means for increasing the in-phase potential of the fifth and sixth signals when the output potential of the extracting means is higher than when the second amplitude center potential is low; Is a first output signal output to a first output terminal, and the sixth signal is a second output signal output to a second output terminal.
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成し、前記第１と第２の入力信号のデューティが５
０パーセントを超える場合は、前記第１の三角波信号の
振幅中心電位は前記第２の三角波信号の振幅中心電位よ
り高くなり、前記第１と第２の入力信号のデューティが
５０パーセントに等しい時は、前記第１の三角波信号の
振幅中心電位と前記第２の三角波信号の振幅中心電位が
等しくなることを特徴とする三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位に逆比例し
た電位を出力する第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位に逆比例し
た電位を出力する第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の信号と、この第３の信号
と相補的な第４の信号を生成し、制御端子に入力される
前記第１の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第３と第４の信号の同相電位は前記第１の振幅
中心電位が低い場合より上がる第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の信号と、この第５の信号
と相補的な第６の信号を生成し、制御端子に入力される
前記第２の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第５と第６の信号の同相電位は前記第２の振幅
中心電位が低い場合より上がる第２の差動増幅手段とを
具備し、 前記第３の信号を第１の出力端子に出力する第１の出力
信号とし、前記第６の信号を第２の出力端子に出力する
第２の出力信号とすることを特徴とするデューティ制御
回路。8. A first input signal having an arbitrary duty and a second input signal which is a differential input complementary to the first input signal, correspond to the first input signal. A first triangular wave signal and a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal are generated, and the duty of the first and second input signals is 5
When it exceeds 0%, the amplitude center potential of the first triangular wave signal becomes higher than the amplitude center potential of the second triangular wave signal, and when the duty of the first and second input signals is equal to 50%, A triangular wave generating means, wherein an amplitude center potential of the first triangular wave signal is equal to an amplitude center potential of the second triangular wave signal; and an inverse of a first amplitude center potential of the first triangular wave signal. A first amplitude center potential extracting unit that outputs a proportional potential; a second amplitude center potential extracting unit that outputs a potential that is inversely proportional to a second amplitude center potential of the second triangular wave signal; And a second triangular signal are differentially amplified to generate a third signal corresponding to the first input signal and a fourth signal complementary to the third signal, which are input to the control terminal. The first amplitude center potential extracting means If the output potential of the first and second triangular wave signals is higher, the in-phase potential of the third and fourth signals is higher than when the first amplitude center potential is lower. Differential amplification is performed to generate a fifth signal corresponding to the first input signal and a sixth signal complementary to the fifth signal, and the second amplitude center input to a control terminal is generated. A second differential amplifying means for increasing the in-phase potential of the fifth and sixth signals when the output potential of the potential extracting means is higher than when the second amplitude center potential is low; A duty control circuit comprising: a first output signal that outputs a signal to a first output terminal; and a second output signal that outputs the sixth signal to a second output terminal.
号と、この第１の入力信号に対し相補的な差動入力であ
る第２の入力信号とから、前記第１の入力信号に対応す
る第１の三角波信号と、前記第２の入力信号に対応し前
記第１の三角波信号に対して相補的な第２の三角波信号
を生成し、前記第１と第２の入力信号のデューティが５
０パーセントを超える場合は、前記第１の三角波信号の
振幅中心電位は前記第２の三角波信号の振幅中心電位よ
り低くなり、前記第１と第２の入力信号のデューティが
５０パーセントに等しい時は、前記第１の三角波信号の
振幅中心電位と前記第２の三角波信号の振幅中心電位が
等しくなることを特徴とする三角波生成手段と、 前記第１の三角波信号の第１の振幅中心電位に逆比例し
た電位を出力する第１の振幅中心電位抽出手段と、 前記第２の三角波信号の第２の振幅中心電位に逆比例し
た電位を出力する第２の振幅中心電位抽出手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第３の信号と、この第３の信号
と相補的な第４の信号を生成し、制御端子に入力される
前記第１の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第３と第４の信号の同相電位は前記第１の振幅
中心電位が低い場合より上がる第１の差動増幅手段と、 前記第１と第２の三角波信号の差動増幅を行い、前記第
１の入力信号に対応する第５の信号と、この第５の信号
と相補的な第６の信号を生成し、制御端子に入力される
前記第２の振幅中心電位抽出手段の出力電位が高けれ
ば、前記第５と第６の信号の同相電位は前記第２の振幅
中心電位が低い場合より上がる第２の差動増幅手段とを
具備し、 前記第４の信号を第１の出力端子に出力する第１の出力
信号とし、前記第５の信号を第２の出力端子に出力する
第２の出力信号とすることを特徴とするデューティ制御
回路。9. A signal corresponding to the first input signal from a first input signal having an arbitrary duty and a second input signal that is a differential input complementary to the first input signal. A first triangular wave signal and a second triangular wave signal corresponding to the second input signal and complementary to the first triangular wave signal are generated, and the duty of the first and second input signals is 5
When it exceeds 0%, the amplitude center potential of the first triangular wave signal is lower than the amplitude center potential of the second triangular wave signal, and when the duty of the first and second input signals is equal to 50%, A triangular wave generating means, wherein an amplitude center potential of the first triangular wave signal is equal to an amplitude center potential of the second triangular wave signal; and an inverse of a first amplitude center potential of the first triangular wave signal. A first amplitude center potential extracting unit that outputs a proportional potential; a second amplitude center potential extracting unit that outputs a potential that is inversely proportional to a second amplitude center potential of the second triangular wave signal; And a second triangular signal are differentially amplified to generate a third signal corresponding to the first input signal and a fourth signal complementary to the third signal, which are input to the control terminal. The first amplitude center potential extracting means If the output potential of the first and second triangular wave signals is higher, the in-phase potential of the third and fourth signals is higher than when the first amplitude center potential is lower. Differential amplification is performed to generate a fifth signal corresponding to the first input signal and a sixth signal complementary to the fifth signal, and the second amplitude center input to a control terminal is generated. A second differential amplifying unit that increases an in-phase potential of the fifth and sixth signals when an output potential of the potential extracting unit is high, as compared with a case where the second amplitude center potential is low; A duty control circuit comprising: a first output signal for outputting a signal to a first output terminal; and a second output signal for outputting the fifth signal to a second output terminal.
ューティ制御回路を、２以上カスケード接続したことを
特徴とする請求項１乃至９の中のいずれか１つに記載の
デューティ制御回路。10. The duty control circuit according to claim 1, wherein two or more duty control circuits each including a combination of the constituent elements are cascaded.
増幅手段の間に配置され、前記第第１と第２の三角波信
号を、前記第１の差動増幅手段の入力範囲にマッチさ
せ、かつ前記第１の振幅中心電位とタイミングを合わせ
る第１のシフトレベル手段と、 前記三角波生成手段と前記第２の差動増幅手段の間に配
置され、前記第１と第２の三角波信号を、前記第２の差
動増幅手段の入力範囲にマッチさせ、かつ前記第２の振
幅中心電位とタイミングを合わせる第２のレベルシフト
手段とを具備したことを特徴とする請求項１乃至９の中
のいずれか１つに記載のデューティ制御回路。11. The signal processing apparatus according to claim 1, wherein the first and second triangular wave signals are arranged between the triangular wave generating means and the first differential amplifying means so as to match an input range of the first differential amplifying means. And first shift level means for adjusting the timing with the first amplitude center potential, and disposed between the triangular wave generating means and the second differential amplifying means, and providing the first and second triangular wave signals. And a second level shift means for matching the input range of the second differential amplifying means and for adjusting the timing with the second amplitude center potential. The duty control circuit according to any one of the above.
信号を差動増幅し、第７の信号と、この第７の信号と相
補的な第８の信号を生成する第３の差動増幅手段を具備
したことを特徴とする請求項１１に記載のデューティ制
御回路。12. The third signal for differentially amplifying the signal from the first and second output terminals to generate a seventh signal and an eighth signal complementary to the seventh signal. The duty control circuit according to claim 11, further comprising dynamic amplification means.
ューティ制御回路を、２以上カスケード接続したことを
特徴とする請求項１１または１２のいずれかに記載のデ
ューティ制御回路。13. The duty control circuit according to claim 11, wherein two or more duty control circuits each including a combination of the constituent elements are cascaded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04058098A JP3544115B2 (en) | 1998-02-23 | 1998-02-23 | Duty control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04058098A JP3544115B2 (en) | 1998-02-23 | 1998-02-23 | Duty control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11239044A true JPH11239044A (en) | 1999-08-31 |
| JP3544115B2 JP3544115B2 (en) | 2004-07-21 |
Family
ID=12584440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04058098A Expired - Fee Related JP3544115B2 (en) | 1998-02-23 | 1998-02-23 | Duty control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3544115B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841308A (en) * | 2010-05-24 | 2010-09-22 | 无锡汉咏微电子有限公司 | Structure of high performance operational amplifier |
| US7913536B2 (en) * | 2005-07-29 | 2011-03-29 | Sensata Technologies Holland B.V. | Compensation arrangement and method for operation thereof |
-
1998
- 1998-02-23 JP JP04058098A patent/JP3544115B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7913536B2 (en) * | 2005-07-29 | 2011-03-29 | Sensata Technologies Holland B.V. | Compensation arrangement and method for operation thereof |
| CN101841308A (en) * | 2010-05-24 | 2010-09-22 | 无锡汉咏微电子有限公司 | Structure of high performance operational amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3544115B2 (en) | 2004-07-21 |
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