JPH11238045A - Mutual exclusion element control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inactivate stages contiguous to an active stage without imposing undesirable stiffness on a pipeline by allowing a mutual exclusion element linked between stages to inactivate stages adjacent to some active stage or inhibit the operation in an adjacent stage when the stage is active. SOLUTION: A mutual exclusion element chain 70 is coupled with a chain of processor stations 80 to 84. The mutual exclusion chain 70 communicates with the processor stage 80, etc., by making use of 'request', 'permission', and 'completion' signals. As data items move through the chain of the processors, a request to transfer information to a next processor stage is made and the 'permission' signal is supplied in response. After the 'permission' signal is generated, the part of the chain does not generate another 'permission' signal until the 'completion' signal is received from the processor stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a control circuit using a linear mutual exclusion chain, and more particularly, to a circuit for controlling a pipeline stage in an asynchronous system.

[0002]

BACKGROUND OF THE INVENTION Chains provide an asynchronous "turn" to a group of counterflow pipeline stages. A chain of mutual exclusion elements allows operation at either stage to eliminate operation at two neighboring stages. In some cases, the stage takes two turns in succession and prohibits their neighbors from operating for a longer interval than required for the two operations. The control circuit described above allows such an asynchronous system to operate at very high speeds, for example, on the order of about 700 MHz or more. Counterflow pipeline processors are known. A counterflow pipeline processor is a computer system processor in which instructions and results flow backwards through the pipeline and interact as they pass. In a counterflow pipeline processor, the pipeline is formed of a plurality of stages, each stage including an instruction portion and a result portion. Instructions flow through the pipeline in one direction,
The result flows in the other direction. In these systems, the operation of the various stages relative to each other must be controlled so that the instructions and results are forwarded at the appropriate time when the destination receives the instructions and results and can act on them. No.

For a more detailed discussion of the prior art work on counterflow pipeline processors, see the report SMLI from Sun Microsystems, the assignee of the present invention.
"Counterflow Pipeline Pr published as TR-94-25
ocessor Architecture "and U.S. Patent No. 5,187,800" Asynchronous Pipelained Data Proc.
It is also the subject of the "essing System". In these systems, it is important that the instructions and results interact properly within each stage, and that no more data is supplied to each stage during the interaction process. is there.
Therefore, there is a need for a suitable control system that allows the stages to communicate properly. The circuit of the present invention provides such a mechanism. Circuits that mutually eliminate two competitors are also known. These circuits are, for example, Mead published by Addison Wesley in 1980.
And Conway, Chapter 7, "System Timing," in the Introduction to VLSI Systems, section 7.8.6 (pages 260-261) and elsewhere. As described therein, these circuits are based on flip-flops and threshold detectors. 2 for service
Each of the two competitors tries to put the flip-flop in a state that favors its service. The problem in this case is that two competitors request service at the same time and the flip-flop
That is, to remain in a "metastable" state without flips or flops. The threshold detector is designed to make a successful selection and ensure a flip or flop only when the flip-flop remains in the metastable region.

[0004]

SUMMARY OF THE INVENTION If the two stages adjacent to the active stage are idle and cannot change state during periods when the intermediate stage is active, controlling the operation of the stages in the counterflow pipeline is straightforward. become. One way to enforce the behavior in this way is to combine all odd stages together, combine all even stages together, and alternately activate all odd stages and all even stages. . The drawback of this scheme is that it imposes undesirable rigidity on the pipeline. The mutual exclusion chain circuit described below also deactivates stages adjacent to the active stage, but does not do so in a more rigid manner. Instead of tying the odd and even stages together, the circuit of the present invention uses a mutual exclusion element linked between the stages. These linked mutual exclusion elements deactivate the neighborhood of any active stage. Alternatively, if any of its neighbors are active, the operation in that stage is prohibited.

One embodiment of a system according to the present invention includes a control circuit having a series of stages coupled together. Each stage includes circuitry for determining whether an adjacent stage is active and, if so, blocking activity in the stage so determined. The system includes an execution circuit for performing a desired activity in each unit of the series, and a control circuit connected to prohibit the performance of the desired activity in a unit when an adjacent unit of the unit is active. And a series of interconnects with the execution circuit. In one embodiment,
The circuit according to the present invention provides a mechanism to ensure that activity at a given stage in a series of stages excludes activity at adjacent stages. This circuit is
It includes a series of stages coupled between a high potential source and a low potential source. Each stage includes an output node, first and second input nodes, a gate electrode coupled to the first input node, a drain electrode coupled to the output node, and a source electrode coupled to a low potential. A first transistor having a gate electrode coupled to a second input node, a drain electrode coupled to an output node, and a source electrode coupled to a low potential. Contains. Each stage further includes a third transistor having a drain electrode coupled to the output node, a source electrode coupled to a low potential, and a gate electrode coupled to receive a "done" signal. Including. Each stage further includes a fourth transistor having a gate electrode coupled to receive the request signal, a drain electrode coupled to the output node, and a source electrode coupled to a high potential. The first input node of each stage is coupled to the output node of the immediately preceding stage, and the second input node of each stage is coupled to the output node of each immediately following stage. When a stage adjacent to the selected stage is active, its output node is high. This high potential is applied to the gate electrode of either the first or second transistor of the selected stage and pulls the output node low, preventing activity in that selected stage. On the other hand, when the selected stage is active, its output node goes high. This high potential is applied to the gate of the second transistor of the preceding stage and the gate of the first transistor of the following stage, so that activity in the preceding and subsequent stages is blocked. In this way, each stage is prevented from operating when the adjacent stage is operating.

[0006]

FIG. 1 is a block diagram of a mutual exclusion element according to an embodiment of the present invention.
Stages 10, 20, 30, connected by children
It is a figure showing 40 chains. Each mutual exclusion element
As shown by the cross connection in FIG.
Page. Each in the chain of mutual exclusion elements
The stage includes four transistors. less than
The operation of the stage 20 will be described.
Obviously, the operations of 0, 30, and 40 are identical.
Would. The stage 20 has first and second parallel-connected
NMOS transistors 21 and 24 are included. Commonly connected
Drains 22 and 25 are connected to node 23.
You. Commonly connected sources 26 and 27 are at a low potential, eg,
If it is connected to ground. The gate of the transistor 21
Connected to the node 13 of the preceding stage 10,
The gates 29 of the registers 24 correspond to the following stages 30.
Connected to node 33. Node 23 also
Switchable connection to the same low potential through transistor 51
Have been. The drain 52 of the transistor 51 is connected to the node
23, source 53 is grounded, and its gate
Port 54 is connected to receive a "done" signal.
You. Stage 20 further includes a PMOS transistor 60.
No. The source 61 of the transistor 60 has a high potential V _DDConnect to
The drain 62 is connected to the node 23 and
Port 63 is connected to receive a "request" signal.
You.

Each stage in the chain receives a signal from an external circuit described later. In summary, each stage receives a "request" signal and a "done" signal and provides a "grant" signal. The "request", "grant", and "done" signals are coupled to a counterflow pipeline stage, as described below with reference to FIG. Each stage 1
0, 20, 30, and 40 are common "decisions" as shown.
Three wide NMOS transistors (eg, transistors 21, 24 and 5) connected to node 23
1) and one narrow PMOS transistor (eg,
Transistor 60). The two NMOS transistors 21 and 24 are driven by the "decision" node of the adjacent stage. If a stage decides
If the voltage at the node exceeds a certain threshold, gate 90 drives the "grant" node high, giving the stage "order". The stage having a certain order is the neighborhood NM
By turning on one of the OS transistors and lowering the voltage of its neighboring "decision" node below the threshold level, the two neighbors are prevented from gaining order.
The third NMOS transistor, which receives "Done" at its input terminal, resets output node 23 low after a certain order is completed. In some biological systems, the phenomenon that movement at one location inhibits movement at a neighboring location is known as "lateral inhibition". The circuit described provides this capability.

The narrow PMOS transistor 60 supplies current to the "decision" 23 of each stage and attempts to drive the enable node high. A "request" signal is applied to the gate of the small P-type transistor. This is a "low" activity signal. Due to the narrowness of the P-type transistor 60, the current it supplies is
If 3 is higher than the threshold for inhibiting the operation of this stage, it is too small to defeat the driving of one of the NMOS transistors 21 and 24. Therefore, even if PM
Even if the OS transistor 60 is conducting, a neighboring stage having an order prevents this stage 20 from gaining an order. If the stage does not require a turn, the circuitry connected to it will turn off the P-type transistor 60.

FIG. 2 shows the interconnection of a chain 70 of mutually exclusive elements having stages 80,..., 84 of a counterflow pipeline processor. Although only exemplary stages are shown, more or fewer stages may be used as needed, depending on the particular processor design. In the processor, the instruction is input from a path 87 and the stages 80, 81, 82
Proceed upward through the like. Each instruction is executed at one stage in the pipeline, but typically different types of instructions are executed at different stages. The result of the execution flows down path 88 through each stage. The results carry names and values, which can be combined with the appropriate instructions to generate further results. The details of this operation are known and are described in the above-mentioned literature.

Coupled to the chain of processor stages is a mutually exclusive element chain 70. The chain 70 is composed of a series of devices as shown in FIG. 1, for example. Mutual exclusion chain 70 provides a "request" signal, a "grant"
And communicate with the processor 80 and the like using the "complete" signal. As the data item moves through the chain of processors, a request is made to transfer information to the next processor, as indicated by the signal on the "request" line. When a "request" is presented to that part of the chain, a "grant" signal is provided in response. After generating a "grant" signal in response to a "request" signal, that portion of the chain does not generate any further "grant" signals until it receives a "done" signal from its processor stage. As described with respect to FIG. 1, in response to the indication, the stage is free to make the next request to pass information to the next stage in the processor chain.

Unlike the illustrated embodiment, the desired result can be achieved by using separate mutual exclusion elements between each pair of stages in the pipeline. In such a case, a stage becomes active only when it succeeds in winning the service from each of the mutually exclusive elements. However, in such a circuit, if each stage obtains service from the lower mutual exclusion element, but does not obtain service from the higher mutual exclusion element, it will stall. An important feature of the circuit being described is the use of a direct coupling between adjacent mutual exclusion elements to avoid this deadlock. This circuit has a logical A
Rather than relying on discrete decisions using digitally combined outcomes by ND, it acts like an analog circuit to eliminate contention between a stage and its adjacent stage.

A simulation was performed to demonstrate the performance advantages of the circuit shown in FIG. The circuit was split into two parts for simulation. The first part, called the "mutual exclusion sub-circuit", is shown in FIG. 3a. 12 each
In addition to the three μ-width N-type transistors 21, 24, 51, the circuit includes a threshold detection inverter 91 and a buffer 92 to drive a signal called “enable”. The size of the transistors in inverter 90 is selected to establish a threshold above the metastable voltage of the mutual exclusion chain. The threshold detecting inverter 91 avoids giving “permission” until the voltage of the output node 23 of this stage exceeds the metastable threshold. The final output of the simulation circuit is a digital signal called "permitted". A high "permission" means that the stage has successfully won the order from both its neighbors. Two input terminals "In
"A" and "InB" couple the circuit with its neighbors. The input terminal called “Complete” is the reset transistor 51
Drive. FIG. 3b shows a portion of the circuit called the "processor sub-circuit". This circuit comprises a pair of inverters 9
4, 95, simulating the user's behavior from the point of authorization in a certain order until the user declares completion. The circuits of FIGS. 3a and 3b are combined as indicated by the terminals labeled in each figure. For the simulation, a 5-stage chain was used, with dummy "mutual exclusion sub-circuits" at each end, and the last active stage loaded the same as the center stage.

Details of the interconnection between the circuits shown in FIGS. 3a and 3b are shown in FIG. 3c. As shown, the circuit of FIG. 3a constitutes a chain of exclusion elements, and the circuit of FIG. 3b constitutes a connection to a node of the mutual exclusion circuit shown in FIG. A typical result of the simulation is shown in FIG. FIG. 3d shows two traces. The tall trace is a signal called "grant". The short serrated trace is the signal labeled "decision." The decision signal is
Since it is driven only by the narrow pull-up transistor 60, the rise is slower than the enable signal. This simulation shows that the activities of the stages are strictly alternating. This simulation cycle takes about 1.5 ns for frequencies above 600 MHz.
It is.

FIG. 4 shows Y for the mutual exclusion element control circuit.
It is a schematic diagram showing a configuration. Such a configuration can be applied, for example, to a situation where the controlled processor includes a branch pipeline. As shown in FIG. 2, the processor stages 101, 102,..., 107 are shown in a schematic diagram. The stages are coupled in series with the instructions flowing up one path 110 and the results flowing down the other path 115. Above stage 103, the pipeline branches, with instructions from stage 103 being delivered to both stages 104 and 106 and results arriving at stage 103 from both stages 104 and 106. Logic in stage 103 (not shown)
Can select either or both result paths from stages 104 and 106 as activities.

Controlling the pipeline is a chain of mutually exclusive elements 100 similar to the chain shown in FIG. 2 and can be implemented using the circuit shown in FIG. Mutual exclusion element chain 100 operates as described with respect to the operations of FIGS. Each processor stage (eg, stage 103) communicates with the mutual exclusion element chain 100 using "request", "grant", and "done" signals as shown in stage 101. FIG. 5 is a detailed circuit diagram of a circuit for realizing a branch chain of the mutual exclusion elements shown in the schematic diagram as Y in FIG. FIG.
Shows four stages A in the chain,
B, C1, and E1. Stage A receives and supplies signals to it from the preceding stage at the bottom of FIG. On the other hand, the stages C1 and E1 receive signals from the uppermost stages C2 and E2 in FIG. 5 and supply signals to them. These stages are labeled corresponding to the labeling of FIG.

The circuit shown in FIG. 5 corresponds to the circuit described with reference to FIG. The main difference between the circuit shown in FIG. 5 and the circuit shown in FIG. 1 is the presence of a stage labeled B. Stage B has transistors 125 and 126. Transistor 125 is connected to receive a signal from stage C1, while transistor 126 receives a signal from stage E1. As described for the circuit of FIG. 1, when either stage C1 or E1 becomes active, operation by stage B is blocked.
This is achieved by special transistors 125 or 126 that are not present in other stages. The unidirectional chain of the mutual exclusion element (FIG. 1) and the branch chain of the mutual exclusion element (FIG. 5) have been described above.
Or it can be easily extended to higher dimensions.
For example, suppose there are black and white squares on a checkerboard with a mutual exclusion circuit between them. If any black square is active, four adjacent white squares are blocked, and if any white square is active, four adjacent black squares are blocked. A similar arrangement in three dimensions is possible, with each element inhibiting six neighboring activities. Mutual exclusion circuits can also have other types of symmetry. For example, for hexagonal symmetry in two dimensions, each element forbids six neighbors. For a hexagonal symmetry in three dimensions, such as a cannon ball in a pile, each element is 1
Prohibit 2 adjacent neighbors.

This circuit is also useful in configurations lacking symmetry. For example, if a module of one computer system must deactivate the other N designated modules in order to operate that given module, indicate the activity of each of the other N modules. It can be controlled by a mutual exclusion circuit having N inputs connected to the node. In the mutual exclusion circuit,
If any of the other N modules are active, each N input is connected to the block of FIG.
Connected to a transistor similar to 126. When a given module is active, reciprocal connections must be made to emphasize the inactivity of other modules. The circuit described above has applications in many different applications. One application shown in FIG. 2 is the control of a counterflow pipeline. In another application, the circuit can control the relaxation calculation in any number of dimensions. In the relaxation calculation, the total "energy" of the system is reduced by changing local parameters to locally reduce "energy". In the relaxation calculation, the neighborhood of the active element must be kept stable while changing the value of the active element. If two adjacent elements change at the same time, their combined energy will increase, invalidating the purpose of the calculation. The present invention provides a technique for asynchronously guaranteeing the required stability of a neighbor.

The embodiment of the present invention has been described above. Obviously, many modifications can be devised from the specific circuitry described above without departing from the spirit of the invention, which is limited by the following claims.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a chain of mutual exclusion elements.

FIG. 2 shows the coupling of a chain of mutual exclusion elements as shown in FIG. 1 with stages in a counterflow pipeline processor.

FIG. 3a is a circuit diagram of a portion of a simulated circuit.

FIG. 3b is a circuit diagram of another part of the simulated circuit.

FIG. 3c is a diagram showing the connection of stages during simulation.

FIG. 3d is a diagram showing the result of a simulation.

FIG. 4 is a diagram showing another embodiment of the control circuit.

FIG. 5 is a detailed view of the embodiment of FIG.

[Explanation of symbols]

 10, 20, 30, 40 Stage 13, 23, 33, 43 Node 21, 24 NMOS transistor 22, 25 Drain electrode 26, 27 Source electrode 28, 29 Gate electrode 51 NMOS transistor 52 Drain electrode 53 Source electrode 54 Gate electrode 60 PMOS Transistor 61 Source electrode 62 Drain electrode 63 Gate electrode 70 Chain of mutual exclusion elements 80, 81, 82, 83, 84 Stage 87 Command path 88 Result path 90 Gate 91 Inverter 92 Buffer 101-107 Processor stage 110 Command path 115 Result path 125 , 126 transistors

 ────────────────────────────────────────────────── ─── Continuation of the front page (71) Applicant 591064003 901 SAN ANTONIO ROAD PALO ALTO, CA 94303, US A. (72) Inventor Robert F. Sprawl 02158 Massachusetts, United States of America 02158 Newton Kenrick Street 239 (72) Inventor William Escorts United States of America 94063 Redwood City Scott Avenue 623

Claims (20)

[Claims] 1. A control circuit having a series of stages coupled to each other, each of said stages determining that an adjacent stage is active and, in response, blocking activity in the stage so determined. An execution circuit including a circuit for performing a desired activity in each unit of the series of units; and the control circuit connected to prohibit each unit from performing the desired activity when an adjacent unit is active. And a series of interconnections between the execution circuit and the execution circuit. 2. The system according to claim 1, wherein said execution circuit operates asynchronously. 3. Each of the stages in the control circuit includes: at least two transistors connected in parallel between a first node and a low potential source; and a stage between the first node and the high potential source. 2. The system of claim 1, comprising: a pull-up transistor connected to the first node; and a pull-down transistor connected between the first node and a low potential source. 4. The system of claim 3, wherein one of the at least two transistors is connected to a preceding stage, and the other of the at least two transistors is connected to a subsequent stage of a control circuit. 5. The pull-up transistor is controlled by a request signal from the execution circuit, the pull-down transistor is controlled by a completion signal from the execution circuit, and the first node sends an enable signal to the execution circuit. The system of claim 3 for providing. 6. The at least two transistors,
The system of claim 3, comprising a third transistor connected in parallel with them. 7. The system of claim 1 wherein said execution circuit comprises a series of execution units connected in series, each said unit being coupled to a corresponding stage of said control circuit. 8. The execution circuit comprises a series of execution units connected in series, the last execution unit being connected to a pair of execution units, and the pair of execution units being each connected to the last execution unit. One of the at least two transistors is coupled to a stage in the control circuit that is coupled to the last execution unit, and the other of the at least two transistors is coupled to a stage of the pair of execution units. 4. The control circuit of claim 3, wherein the third transistor is connected to a stage in the control circuit coupled to one of the execution units, and the third transistor is connected to a stage in the control circuit coupled to the other of the pair of execution units. System. 9. A method for controlling a system having a series of execution units to prevent adjacent units from operating simultaneously, comprising providing a series of mutually exclusive elements interconnected in a chain. Coupling each of said mutual exclusion elements to a corresponding execution unit in said series of execution units. 10. The method of claim 9, wherein each execution unit comprises one unit in a counterflow pipeline processor. 11. The series of execution units includes a branch having at least two legs, a first leg having a first series of execution units, and a second leg having a second series of execution units. Having an execution unit on a branch coupled to both the first leg and the second leg, wherein the method further comprises interconnecting each other to a corresponding execution unit in the first leg. Providing a first series of mutually exclusive elements that are coupled; providing a second series of mutually exclusive elements that are interconnected with each other and coupled to a corresponding execution unit in the second leg. A step; another one of the mutual exclusion elements interconnected to a selected one of the first and second series of mutual exclusion elements and coupled to control the execution unit at the branch. Preparing the step, The method according to claim 9. 12. The series of execution units comprises n series of execution units, all of the n series intersect at a particular execution unit, and the series of mutual exclusion elements comprises n series of mutual exclusion elements. , All of the n series intersect at a particular mutual exclusion element coupled to the particular execution unit, and wherein the n series of execution units and the n series of mutual exclusion elements comprise the particular execution unit and the 10. The method of claim 9, wherein the method is arranged symmetrically with respect to a particular mutual exclusion element. 13. A system comprising: a first source and a second source of an electrical signal; and a series of stages coupled to each other, each stage including a first output node, a first input node, A second input node; a gate electrode coupled to the first input node; a drain electrode coupled to the first output node; and a source electrode coupled to the second source of the electrical signal. The first
A second electrode having a gate electrode coupled to the second input node, a drain electrode coupled to the first output node, and a source electrode coupled to the second source of the electrical signal.
A third electrode having a drain electrode coupled to the first output node, a source electrode coupled to the second source of the electrical signal, and a gate electrode coupled to receive the completion signal. A fourth transistor having a gate electrode coupled to receive the request signal, a drain electrode coupled to the first output node, and a source electrode coupled to the first source of the electrical signal And wherein the first input node of each stage is coupled to the first output node of the immediately preceding stage, and the second input node is coupled to the first output node of each immediately following stage. Circuit. 14. The circuit of claim 13, wherein said first, second, and third transistors comprise NMOS transistors. 15. The circuit according to claim 14, wherein said fourth transistor comprises a PMOS transistor. 16. The fourth transistor, wherein the fourth transistor is connected to the third transistor.
16. The circuit of claim 15 wherein the transistor has a channel width to length ratio. 17. The circuit of claim 16, wherein the first source of the electrical signal comprises a positive potential source and the second source of the electrical signal comprises a lower potential source. 18. The apparatus of claim 1, further comprising associated circuitry coupled to and controlled by said series of stages.
3. The circuit according to 3. 19. The circuit according to claim 18, wherein said associated circuit comprises a stage in a counterflow pipeline processor. 20. The apparatus of claim 18, wherein the associated circuit is coupled to receive a signal from the first output node, providing the completion signal, and providing the request signal. Circuit.