JPH11237862A - Display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display controller by which picture quality is improved by appropriately performing conversion processing. SOLUTION: Signal converting IC chips 21 and 22 for odd number and even number are provided in parallel and converting parts 24 and 32 are provided for inputting plural data and control signals. Phase control circuits 26 and 34 are provided corresponding to clocks and the phase of a clock is relatively controlled corresponding to data to delay the phase inside the converting parts 24 and 32. An LCD control IC chip 41 is provided with parallel signal converting blocks 42 and 43 and connects them to converting parts 46 and 53. They are connected to phase control circuits 48 and 55 corresponding to clocks and the clock is outputted while relatively controlling and matching the phase corresponding to data to delay the phase inside the converting parts 46 and 53.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device in which conversion processing is appropriately performed to improve image quality.

[0002]

2. Description of the Related Art Conventionally, as a device for controlling a display on a liquid crystal panel of a liquid crystal display device, for example, a display control device having a configuration shown in FIG. 4 is known.

The display control device shown in FIG. 4 comprises a signal conversion IC chip 1 for odd signals and a signal conversion IC chip for even signals.
C chip 2 is provided in parallel, and signal conversion I for odd signals is performed.
The C chip 1 has a conversion circuit 3 for converting a differential signal into a normal signal. The conversion circuit 3 is provided with an amplifier 4 corresponding to a plurality of data corresponding to the number of data. It is connected to the unit 5. Further, an amplifier 6 is provided corresponding to the clock, and the amplifier 6 adjusts the phase (Ph
The phase adjustment circuit 7 is also connected to the conversion unit 5 and relatively adjusts the phase of the clock in accordance with the data whose phase is delayed in the conversion unit 5 and the like. The phase of the odd data and control signal after passing through the section 5 and the phase of the odd clock after passing through the phase adjustment circuit 7 are adjusted. The odd data and control signal from the conversion unit 5 and the odd clock from the phase adjustment circuit 7 are input to an LCD control IC chip 8 for controlling a liquid crystal panel (not shown).

A signal conversion IC chip 2 for even signals
Similarly, a conversion circuit 11 converts a differential signal into a normal signal.
The conversion circuit 11 includes amplifiers 12 corresponding to a plurality of data corresponding to the number of data, and these amplifiers 12 are connected to a converter 13. In addition, an amplifier 14 is provided corresponding to the clock, and the amplifier 14 adjusts the phase (Phase
Locked Loop) circuit 15 and the phase adjustment circuit 15
Is also connected to the conversion unit 13, which relatively adjusts the phase of the clock corresponding to the data whose phase is delayed in the conversion unit 13, and adjusts the phase of the even-numbered data and the control signal after passing through the conversion unit 13. The phase with the even clock after passing through the circuit 15 is adjusted. The even data and control signal from the conversion unit 13 and the even clock from the phase adjustment circuit 15 together with the odd data and control signal from the conversion unit 5 and the odd clock from the phase adjustment circuit 7 It is input to the LCD control IC chip 8 for controlling the panel.

[0005] Then, the LCD control IC chip 8
Then, the digital signal is converted.

[0006]

However, although the signal conversion IC chips 1 and 2 are provided with the phase adjustment circuits 7 and 15, respectively, the LCD control IC chip 8 has at least each of the phase adjustment circuits. Since it is not provided, it is difficult to match the phase difference between the odd data, the even data, and the control signal at the time of signal conversion to the same odd clock and even clock, respectively. Has a problem that cannot be improved.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a display control device that improves the image quality by appropriately performing conversion processing.

[0008]

According to the present invention, at least one of a data signal and a control signal inputted from the outside and a clock signal are inputted, and at least one of the data signal and the control signal is inputted. A conversion circuit provided in a plurality of stages for conversion, a phase provided for each of the plurality of stages of conversion circuits, and at least one of a data signal and a control signal converted by these conversion circuits and a phase for adjusting a phase of a clock signal And a phase adjusting means corresponding to each conversion circuit, so that a phase of the clock signal and / or at least one of the data signal and the control signal corresponding to each conversion circuit is adjusted. Thus, the phase shift of each conversion circuit can be suppressed.

The conversion circuit includes a first conversion circuit for converting a normal signal into a differential signal, and a second conversion circuit for converting the differential signal converted by the first conversion circuit into a normal signal. And a conversion circuit.

Further, the conversion circuits are provided in parallel and in pairs corresponding to the odd number signal and the even number signal, respectively.

Further, the phase adjusting means is provided commonly to a pair of conversion circuits corresponding to the odd signal and the even signal.

The pair of conversion means and the phase adjustment means provided corresponding to the conversion means are one I
It is included in the C chip.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the display control device according to the present invention will be described below with reference to the drawings.

In the display control device shown in FIG. 1, a signal conversion IC chip 21 for an odd (ODD) signal corresponding to a display signal of an odd column of the display device and a signal conversion IC chip 22 for an even (EVEN) signal are provided. The signal conversion IC chip 21 for the odd signal, which is provided in parallel, includes a conversion circuit 23 for converting data and control signals of a normal signal into differential signals.
23 is provided with a conversion unit 24 as a conversion unit to which a plurality of data and control signals are input, and the conversion unit 24 is provided with a buffer 25 corresponding to a plurality of data and control signals corresponding to the number of data. I have. Phase adjustment (Phase Locked Loop) as a phase adjustment means corresponding to the clock
A circuit 26 is provided.
Is connected. The phase adjustment circuit 26 is a conversion unit.
The phase of the clock is relatively adjusted in accordance with the data whose phase is delayed within 24 and the like, and the phase of the odd data and the control signal after passing through the conversion unit 24 and the phase of the clock after passing through the phase adjustment circuit 26 To adjust.

A signal conversion IC chip 22 for even signals
Is provided with a conversion circuit 31 for converting data and control signals of normal signals into differential signals, and the conversion circuit 31 is provided with a conversion unit 32 as a conversion unit to which a plurality of data and control signals are input, In the conversion unit 32, a buffer 33 corresponding to a plurality of data and control signals is provided corresponding to the number of data. In addition, a phase adjustment (Phase Locked Loop) circuit 34 as phase adjustment means is provided corresponding to the clock, and a buffer 35 is connected to the phase adjustment circuit 34. The phase adjustment circuit 34 relatively adjusts the phase of the clock corresponding to the data whose phase is delayed in the conversion unit 32 and the like. Adjust the phase with the clock after passing through 34.

The odd data, control signal and odd clock from the signal conversion IC chip 21 and even data, control signal and even clock from the signal conversion IC chip 22 control a liquid crystal (LCD) panel (not shown). Is input to the LCD control IC chip 41.

The LCD control IC chip 41
The signal conversion block 42 for odd signals and the signal conversion block 43 for even signals are provided in parallel, and the signal conversion block 42 for odd signals converts the differential signal into a normal signal. In the conversion circuit 44, buffers 45 corresponding to a plurality of data from the buffer 25 are provided corresponding to the number of data, and these buffers 45 are connected to a conversion unit 46 as conversion means. A buffer 47 is provided corresponding to the clock from the buffer 27.
Is a phase adjustment (Phase Locked Loop)
) Is connected to a circuit 48, and the phase adjustment circuit 48
The phase of the clock is relatively adjusted in accordance with the data whose phase is delayed in the conversion unit 46 and the like.
The phase of the odd-numbered data and control signal after passing through the phase adjustment circuit 48 and the odd-numbered clock after passing through the phase adjustment circuit 48 are adjusted.
The odd data and control signal from the converter 46 and the odd clock from the phase adjustment circuit 46 are output.

Further, a signal conversion block 43 for even-numbered signals
Similarly, a conversion circuit 51 converts a differential signal into a normal signal.
In this conversion circuit 51, buffers 52 corresponding to a plurality of data from the buffer 33 are provided corresponding to the number of data, and these buffers 52 are connected to a conversion unit 53 as conversion means. A buffer 54 is provided corresponding to the clock of the buffer 35. The buffer 54 is connected to a phase adjustment (Phase Locked Loop) circuit 55 as a phase adjustment means, and the phase adjustment circuit 55 is also connected to the conversion unit 53. The phase of the clock is relatively adjusted corresponding to the data whose phase is delayed in the conversion unit 53, and the even data after passing through the conversion unit 53 and the even signal after passing through the control signal and the phase adjustment circuit 55. And adjust the phase. Then, the even data and control signal from the conversion unit 53 and the phase adjustment circuit
The even clock from 55 is output.

Next, the operation of the above embodiment will be described.

First, the conversion unit 24 of the conversion circuit 23 of the signal conversion IC chip 21 for normal data and control signals for odd signals is used.
The normal data and control signals are converted into differential signals, and a phase delay occurs during this conversion. Therefore, the data and control signals converted to clocks by the phase adjustment circuit 26 The differential data and control signal are input to the LCD control IC chip 41 via the buffer 25, and the clock is input to the LCD control IC chip 41 via the buffer 27.

In the LCD control IC chip 41, when differential data and control signals are input to the conversion unit 46 via the buffer 45 of the signal conversion block 42,
These differential data and control signals are converted to normal signals, and a phase delay occurs at the time of this conversion, so that the phase of the clock and the converted data and control signals is adjusted by the phase adjustment circuit 48. The data and control signals are output via a buffer 45 and the clocks are output via a buffer 47 in a state where they are in phase with each other.

The conversion section 32 of the conversion circuit 31 of the signal conversion IC chip 22 for normal data and control signals for even signals.
The normal data and control signals are converted into differential signals, and a phase delay occurs during this conversion. Therefore, the data and control signals converted to clocks by the phase adjustment circuit 34 The differential data and control signal are input to the LCD control IC chip 41 via the buffer 33, and the clock is input to the LCD control IC chip 41 via the buffer 35.

In the LCD control IC chip 41, when differential data and control signals are input to the conversion unit 53 via the buffer 52 of the signal conversion block 43,
These differential data and control signals are converted into normal signals, and a phase delay occurs at the time of this conversion. Therefore, the phase of the clock and the converted data and control signal is adjusted by the phase adjusting circuit 55. Data and control signals are output via a buffer 52 and clocks are output via a buffer 54 in phase with each other.

As described above, by providing the phase adjustment circuits 26, 34, 48, and 55 for the conversion units 24, 32, 46, and 53, respectively, when converting a signal from differential to normal, In either case of converting from normal to normal, the phase can be properly adjusted to the clock, the malfunction is eliminated, the reliability is improved, the display control device with improved image quality is obtained, and the liquid crystal panel is driven and controlled In addition, the image quality can be improved.

Next, another embodiment will be described with reference to FIG.

The embodiment shown in FIG. 2 is different from the embodiment shown in FIG. 1 in that a signal conversion IC chip for odd signals is used.
Instead of 21 and the signal conversion IC chip 22 for even signals,
The PC control IC 61 is formed by forming a signal conversion block 62 in place of the signal conversion IC chip 21 and a signal conversion block 63 in place of the signal conversion IC chip 22 on the PC control IC 61.

Although the operation is the same as that of the embodiment shown in FIG. 1, the variation of the phase adjustment circuits 26 and 34 in the PC control IC 61 can be absorbed in this way, and the signal conversion block
The phase can be appropriately adjusted to the clock for each of 62 and 63, malfunctions can be eliminated, reliability can be improved, and image quality can be improved. Furthermore, even when the signal conversion block is formed by dividing the signal conversion block into odd and even numbers or more, variations in many signal conversion blocks can be absorbed.

Next, another embodiment will be described with reference to FIG.

The embodiment shown in FIG. 3 differs from the embodiment shown in FIG. 2 in that the conversion circuit 23 and the conversion circuit 31 have a common phase adjustment circuit 66 as a phase adjustment means.

The operation is the same as that of the embodiment shown in FIG. 2. However, the signal conversion circuit is formed by dividing the phase adjustment circuit 66 into an odd number and an even number or more by using a single phase adjustment circuit 66. Also in this case, since there is no deviation in timing, variations in many signal conversion circuits can be absorbed.

[0031]

According to the present invention, since the phase adjusting means is provided corresponding to each conversion circuit, at least one of the data signal and the control signal and the clock signal are provided corresponding to each conversion circuit. The phases can be matched, and the phase shift for each conversion circuit can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a display control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a display control circuit according to another embodiment of the present invention;

FIG. 3 is a block diagram showing a display control circuit according to another embodiment of the present invention;

FIG. 4 is a block diagram showing a conventional display control circuit.

[Explanation of symbols]

24, 32, 46, 53 Conversion units 26, 34, 48, 55, 66 as conversion means Phase adjustment circuit as phase adjustment means

Claims (5)

[Claims] 1. A converter provided with a plurality of stages for receiving at least one of a data signal and a control signal input from the outside and a clock signal and converting at least one of the data signal and the control signal. And a phase adjusting means provided for each of the plurality of stages of conversion circuits and adjusting the phase of the clock signal and at least one of the data signal and the control signal converted by the conversion circuits. Characteristic display control device. 2. A conversion circuit comprising: a first conversion circuit for converting a normal signal into a differential signal; and a second conversion circuit for converting the differential signal converted by the first conversion circuit into a normal signal. The display control device according to claim 1, further comprising a conversion circuit. 3. The display control device according to claim 1, wherein the conversion circuits are provided in parallel in pairs corresponding to the odd-numbered signals and the even-numbered signals, respectively. 4. The display control device according to claim 3, wherein the phase adjustment means is provided in common to a pair of conversion circuits corresponding to the odd number signal and the even number signal. 5. The display control device according to claim 4, wherein the pair of conversion means and the phase adjustment means provided corresponding to the conversion means are included in one IC chip.