JPH11234896A - Grounded output protection method for inverter device - Google Patents
Grounded output protection method for inverter deviceInfo
- Publication number
- JPH11234896A JPH11234896A JP10027489A JP2748998A JPH11234896A JP H11234896 A JPH11234896 A JP H11234896A JP 10027489 A JP10027489 A JP 10027489A JP 2748998 A JP2748998 A JP 2748998A JP H11234896 A JPH11234896 A JP H11234896A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- inverter device
- voltage
- gate drive
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Emergency Protection Circuit Devices (AREA)
- Protection Of Static Devices (AREA)
- Inverter Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、インバータ装置
の出力地絡保護方法に関する。The present invention relates to an output ground fault protection method for an inverter device.
【0002】[0002]
【従来の技術】図2は、この種のインバータ装置の従来
例を示す回路構成図であり、1はインバータ装置、2は
商用電源などの交流電源、3はインバータ装置1の負荷
を示し、このインバータ装置1は、例えばダイオード,
平滑コンデンサなどからなる整流回路11と、上アーム
の電流センス端子付のパワーデバイスとしてのIGBT
12aと下アームの電流センス端子付のパワーデバイス
としてのIGBT12bとからなる逆変換回路12と、
IGBT12aをオン・オフさせるゲート駆動回路13
と、IGBT12bをオン・オフさせるゲート駆動回路
14と、逆変換回路12の出力が所望の周波数,電圧の
交流電圧になるようにゲート駆動回路13,14へ制御
信号としてのオン・オフ信号を送信すると共に、ゲート
駆動回路13,14それぞれからの制御信号としてのエ
ラー信号を受信して処理する制御回路15と、制御回路
15とゲート駆動回路13,14との間の備えるインタ
フェース回路16とから構成されている。2. Description of the Related Art FIG. 2 is a circuit diagram showing a conventional example of this type of inverter device, wherein 1 denotes an inverter device, 2 denotes an AC power source such as a commercial power source, and 3 denotes a load of the inverter device 1. The inverter device 1 includes, for example, a diode,
A rectifier circuit 11 composed of a smoothing capacitor and the like, and an IGBT as a power device with a current sense terminal on the upper arm
An inverse conversion circuit 12 comprising an IGBT 12b as a power device with a current sense terminal on the lower arm;
Gate drive circuit 13 for turning on / off IGBT 12a
And a gate drive circuit 14 for turning on and off the IGBT 12b, and an on / off signal as a control signal to the gate drive circuits 13 and 14 so that the output of the inverting circuit 12 becomes an AC voltage having a desired frequency and voltage. And a control circuit 15 for receiving and processing an error signal as a control signal from each of the gate drive circuits 13 and 14, and an interface circuit 16 provided between the control circuit 15 and the gate drive circuits 13 and 14. Have been.
【0003】なお、このインバータ装置1では逆変換回
路12の回路構成として、出力の1相分のみを例示して
いる。また、ゲート駆動回路13はインタフェース回路
16を介して制御回路15から送出されたオン・オフ信
号をIGBT12aのゲート信号に変換する増幅回路1
3aと、IGBT12aの電流センス端子とエミッタ端
子間に接続された検出抵抗13bと、検出抵抗13bの
両端電圧が所定の値を超えたときに動作して出力する比
較器13cと、比較器13cが動作したときに増幅回路
13aの出力をオフ状態(Lowレベル)にするゲート
オフ回路13dと、ゲートオフ回路13dが動作中はエ
ラー信号をインタフェース回路16を介して制御回路1
5へ送出するエラー信号出力回路13eとから構成され
ている。同様に、ゲート駆動回路14はインタフェース
回路16を介して制御回路15から送出されたオン・オ
フ信号をIGBT12bのゲート信号に変換する増幅回
路14aと、IGBT12bの電流センス端子とエミッ
タ端子間に接続された検出抵抗14bと、検出抵抗14
bの両端電圧が所定の値を超えたときに動作して出力す
る比較器14cと、比較器14cが動作したときに増幅
回路14aの出力をオフ状態(Lowレベル)にするゲ
ートオフ回路14dと、ゲートオフ回路14dが動作中
はエラー信号をインタフェース回路16を介して制御回
路15へ送出するエラー信号出力回路14eとから構成
されている。In the inverter device 1, only one phase of the output is illustrated as the circuit configuration of the inverse conversion circuit 12. The gate drive circuit 13 converts the on / off signal sent from the control circuit 15 through the interface circuit 16 into a gate signal of the IGBT 12a.
3a, a detection resistor 13b connected between the current sense terminal and the emitter terminal of the IGBT 12a, a comparator 13c that operates and outputs when the voltage across the detection resistor 13b exceeds a predetermined value, and a comparator 13c. A gate-off circuit 13d for turning off the output of the amplifier circuit 13a (low level) when operated, and an error signal via the interface circuit 16 when the gate-off circuit 13d is operating.
5 and an error signal output circuit 13e for sending out the error signal to the control signal 5a. Similarly, the gate drive circuit 14 is connected between the current sense terminal and the emitter terminal of the IGBT 12b, and an amplifier circuit 14a that converts an on / off signal sent from the control circuit 15 through the interface circuit 16 into a gate signal of the IGBT 12b. Detection resistor 14b and detection resistor 14
a comparator 14c that operates and outputs when the voltage across the terminal b exceeds a predetermined value, and a gate-off circuit 14d that turns off the output of the amplifier circuit 14a (Low level) when the comparator 14c operates. While the gate-off circuit 14d is operating, it comprises an error signal output circuit 14e for sending an error signal to the control circuit 15 via the interface circuit 16.
【0004】[0004]
【発明が解決しようとする課題】上述のインバータ装置
1において、インバータ装置1が動作中にインバータ装
置1から負荷3への給電経路、又は負荷3の内部で地絡
が発生すると、この地絡点と交流電源2の接地点との間
にインバータ装置1を介した閉回路が形成され、逆変換
回路12のIGBT12a,12bに過大な地絡電流が
流れ、この電流によりIGBT12a,12bが破損す
る恐れがあり、何らかの保護回路を備える必要がある。In the above-described inverter device 1, if a ground fault occurs in the power supply path from the inverter device 1 to the load 3 or inside the load 3 during the operation of the inverter device 1, this ground fault point is detected. A closed circuit is formed between the inverter and the grounding point of the AC power supply 2 via the inverter device 1, and an excessive ground fault current flows through the IGBTs 12 a and 12 b of the inverter circuit 12, which may damage the IGBTs 12 a and 12 b. It is necessary to provide some kind of protection circuit.
【0005】すなわち従来のインバータ装置1では、ゲ
ート駆動回路13の検出抵抗13b,比較器13c,ゲ
ートオフ回路13d,エラー信号出力回路13eと、ゲ
ート駆動回路14の検出抵抗14b,比較器14c,ゲ
ートオフ回路14d,エラー信号出力回路14eとが上
記対策のために備え、エラー信号出力回路13e,14
eからのエラー信号を受信した制御回路15では、イン
バータ装置1の動作を停止させ、外部へこの停止を表示
するようにしている。That is, in the conventional inverter device 1, the detection resistor 13b, the comparator 13c, the gate-off circuit 13d and the error signal output circuit 13e of the gate drive circuit 13 and the detection resistor 14b, the comparator 14c and the gate-off circuit of the gate drive circuit 14 are provided. 14d and an error signal output circuit 14e are provided for the above measures, and the error signal output circuits 13e and 14e are provided.
The control circuit 15 that has received the error signal from e stops the operation of the inverter device 1 and displays this stop to the outside.
【0006】しかしながら、例えば6個の電流センス端
子付のパワーデバイスをブリッジ接続して形成される三
相出力の逆変換回路では、上アームのゲート駆動回路
(ゲート駆動回路13相当が3組)それぞれと、下アー
ムのゲート駆動回路(ゲート駆動回路14相当が3組)
それぞれと、エラー信号出力回路13e,14eと制御
回路15との間に備えるインタフェース回路16におけ
る高耐圧ホトカプラなどの絶縁して信号を伝達する素子
の数は少なくとも4個必要となり、この高耐圧ホトカプ
ラは高価であり、回路構成も複雑になっていた。However, for example, in a three-phase output inversion circuit formed by bridge-connecting six power devices with current sense terminals, each of the upper arm gate drive circuits (three sets corresponding to the gate drive circuit 13) is provided. And the gate drive circuit of the lower arm (three sets corresponding to the gate drive circuit 14)
Each of the interface circuits 16 provided between the error signal output circuits 13e, 14e and the control circuit 15 must have at least four high-voltage photocouplers or the like to insulate and transmit signals. It was expensive and the circuit configuration was complicated.
【0007】この発明の目的は、上記問題点を解決する
インバータ装置の出力地絡保護方法を提供することにあ
る。An object of the present invention is to provide an output ground fault protection method for an inverter device which solves the above problems.
【0008】[0008]
【課題を解決するための手段】この発明は、複数個の電
流センス端子付のパワーデバイスをブリッジ接続して形
成される逆変換回路と、該パワーデバイスをオン・オフ
させる該複数個のゲート駆動回路と、これらのゲート駆
動回路との間で制御信号を送受する制御回路とにより、
該逆変換回路に入力される直流電圧を所望の周波数,電
圧の交流電圧に変換し、この交流電圧を負荷に供給する
インバータ装置において、ブリッジ接続された前記パワ
ーデバイスの内、上アームのそれぞれのパワーデバイス
の電流センス端子とソース端子又はエミッタ端子との間
に接続される検出抵抗の両端電圧が所定の値を超えたと
きから所定の期間の間は当該するパワーデバイスのゲー
ト駆動回路の出力をオフ状態にし、ブリッジ接続された
前記パワーデバイスの内、下アームのそれぞれのパワー
デバイスの電流センス端子とソース端子又はエミッタ端
子との間に接続される検出抵抗の両端電圧が所定の値を
超えたときに当該するパワーデバイスのゲート駆動回路
の出力をオフ状態にし、前記下アームのいずれかのゲー
ト駆動回路に発生した前記オフ状態を制御回路に伝達し
て、負荷への給電経路の地絡に対して保護する。SUMMARY OF THE INVENTION The present invention provides an inversion circuit formed by bridge-connecting a plurality of power devices with current sense terminals, and a plurality of gate drives for turning on / off the power devices. Circuit and a control circuit for transmitting and receiving a control signal between these gate drive circuits,
In an inverter device for converting a DC voltage input to the inverse conversion circuit into an AC voltage having a desired frequency and voltage and supplying the AC voltage to a load, each of the upper arms of the bridge-connected power devices is provided. During a predetermined period from when the voltage across the detection resistor connected between the current sense terminal and the source terminal or the emitter terminal of the power device exceeds a predetermined value, the output of the gate drive circuit of the power device is changed. In the off state, the voltage across the detection resistor connected between the current sense terminal and the source terminal or the emitter terminal of each power device of the lower arm of the bridge-connected power devices exceeds a predetermined value. Sometimes, the output of the gate drive circuit of the power device concerned is turned off, and any of the gate drive circuits of the lower arm generates an output. It was then transferred to the OFF state to the control circuit, to protect against ground fault of the power supply path to the load.
【0009】この発明によれば、後述の如く、インバー
タ装置が三相交流電圧を出力するものであっても、前記
インタフェース回路にはエラー信号伝達用の高耐圧ホト
カプラを1個備えればよい。According to the present invention, as will be described later, even if the inverter device outputs a three-phase AC voltage, the interface circuit may be provided with one high-voltage photocoupler for transmitting an error signal.
【0010】[0010]
【発明の実施の形態】図1は、この発明の実施例を示す
インバータ装置の回路構成図であり、図2に示した従来
例回路と同一機能を有するものには同一符号を付してい
る。すなわち図1に示したインバータ装置20において
は、図2に示したインバータ装置1のゲート駆動回路1
3に代えてゲート駆動回路21を備えている。なお制御
回路15aおよびインタフェース回路16aは先述の制
御回路15およびインタフェース回路16と同等機能を
有している。FIG. 1 is a circuit diagram of an inverter device according to an embodiment of the present invention, in which components having the same functions as those of the conventional circuit shown in FIG. . That is, in the inverter device 20 shown in FIG. 1, the gate drive circuit 1 of the inverter device 1 shown in FIG.
3, a gate drive circuit 21 is provided. The control circuit 15a and the interface circuit 16a have the same functions as the control circuit 15 and the interface circuit 16 described above.
【0011】図1に示したゲート駆動回路21はインタ
フェース回路16aを介して制御回路15aから送出さ
れたオン・オフ信号をIGBT12aのゲート信号に変
換する増幅回路21aと、IGBT12aの電流センス
端子とエミッタ端子間に接続された検出抵抗21bと、
検出抵抗21bの両端電圧が所定の値を超えたときに動
作して出力する比較器21cと、比較器13cが動作し
たときから所定の期間動作して出力するタイマー回路2
1dと、タイマー回路21dが動作中は増幅回路21a
の出力をオフ状態(Lowレベル)にするゲートオフ回
路21eとから構成されている。The gate drive circuit 21 shown in FIG. 1 converts an on / off signal sent from the control circuit 15a through the interface circuit 16a into a gate signal of the IGBT 12a, a current sense terminal of the IGBT 12a and an emitter. A detection resistor 21b connected between the terminals;
A comparator 21c that operates and outputs when the voltage across the detection resistor 21b exceeds a predetermined value, and a timer circuit 2 that operates and outputs for a predetermined period from when the comparator 13c operates.
1d and the amplification circuit 21a while the timer circuit 21d is operating.
And a gate-off circuit 21e for turning off the output of the gate-off circuit (low level).
【0012】上述のインバータ装置20において、イン
バータ装置20が動作中にインバータ装置20から負荷
3への給電経路、又は負荷3の内部で地絡が発生する
と、この地絡点と交流電源2の接地点との間にインバー
タ装置20を介した閉回路が形成され、逆変換回路12
のIGBT12a又はIGBT12bのいずれかに地絡
電流が流れ始めようとする。In the inverter device 20 described above, if a ground fault occurs in the power supply path from the inverter device 20 to the load 3 or inside the load 3 while the inverter device 20 is operating, the ground fault point is connected to the AC power supply 2. A closed circuit is formed between the point and the point via the inverter device 20, and the inverse conversion circuit 12
IGBT 12a or IGBT 12b starts to flow.
【0013】すなわち交流電源2の負の半サイクルで
は、前記地絡電流がIGBT12bに流れようとする
が、このときにIGBT12bの電流センス端子とエミ
ッタ端子間に接続された検出抵抗14bの両端電圧が所
定の値(例えば、インバータ装置20の定格出力電流の
300%に相当する値)を超えると、比較器14cが動
作をし、ゲートオフ回路14dにより増幅回路14aの
出力をオフ状態(Lowレベル)にすることによりIG
BT12bのコレクタ電流が遮断され、同時にエラー信
号出力回路14eからインタフェース回路16aを介し
て制御回路15aへエラー信号が送出され、このエラー
信号を受信した制御回路15aでは、インバータ装置2
0の動作を停止させ、外部へこの停止を表示する。That is, in the negative half cycle of the AC power supply 2, the ground fault current tries to flow to the IGBT 12b. At this time, the voltage across the detection resistor 14b connected between the current sense terminal and the emitter terminal of the IGBT 12b is reduced. When the value exceeds a predetermined value (for example, a value corresponding to 300% of the rated output current of the inverter device 20), the comparator 14c operates, and the output of the amplifier circuit 14a is turned off (Low level) by the gate-off circuit 14d. IG
The collector current of the BT 12b is cut off, and at the same time, an error signal is sent from the error signal output circuit 14e to the control circuit 15a via the interface circuit 16a.
0 is stopped, and this stop is displayed outside.
【0014】また交流電源2の正の半サイクルでは、前
記地絡電流がIGBT12aに流れようとするが、この
ときにIGBT12aの電流センス端子とエミッタ端子
間に接続された検出抵抗21bの両端電圧が所定の値
(例えば、インバータ装置20の定格出力電流の300
%に相当する値)を超えると、比較器21cが動作をし
てタイマー回路21dを起動させ、このタイマー回路2
1dは所定の期間(例えば2ミリ秒)動作をし、タイマ
ー回路21dが動作中はゲートオフ回路21eにより増
幅回路21aの出力をオフ状態(Lowレベル)にして
IGBT12aのコレクタ電流を遮断する。前記地絡電
流がIGBT12aに流れる最長の期間は交流電源2の
半サイクルであることから、交流電源2が商用電源の場
合の最長の期間は10ミリ秒となり、この10ミリ秒間
はタイマー回路21dの期間(例えば2ミリ秒)を経過
する毎に、IGBT12aにはインバータ装置20の定
格出力電流の300%に相当するコレクタ電流が微少な
時間流れても、IGBT12aの過電流耐量値以内にす
ることが可能となり、IGBT12aが保護される。さ
らに、前記地絡電流が交流電源2の正の半サイクルから
負の半サイクルの期間に入った時点で、上述の如くゲー
ト駆動回路14の比較器14c,ゲートオフ回路14
d,エラー信号出力回路14eそれぞれが動作をし、エ
ラー信号出力回路14eからインタフェース回路16a
を介して制御回路15aへエラー信号が送出され、この
エラー信号を受信した制御回路15aでは、インバータ
装置20の動作を停止させ、外部へこの停止を表示す
る。In the positive half cycle of the AC power supply 2, the ground fault current tries to flow to the IGBT 12a. At this time, the voltage across the detection resistor 21b connected between the current sense terminal and the emitter terminal of the IGBT 12a is reduced. A predetermined value (for example, 300 times the rated output current of the inverter device 20)
%), The comparator 21c operates and activates the timer circuit 21d.
1d operates for a predetermined period (for example, 2 milliseconds), and while the timer circuit 21d is operating, the output of the amplifier circuit 21a is turned off (Low level) by the gate-off circuit 21e to cut off the collector current of the IGBT 12a. Since the longest period during which the ground fault current flows through the IGBT 12a is a half cycle of the AC power supply 2, the longest period when the AC power supply 2 is a commercial power supply is 10 milliseconds. Every time a period (for example, 2 milliseconds) elapses, even if a collector current corresponding to 300% of the rated output current of the inverter device 20 flows through the IGBT 12a for a very short time, the current may be kept within the overcurrent withstand value of the IGBT 12a. IGBT 12a is protected. Further, when the ground fault current enters a period from the positive half cycle to the negative half cycle of the AC power supply 2, the comparator 14c and the gate-off circuit 14 of the gate drive circuit 14 as described above.
d, the error signal output circuit 14e operates, and the error signal output circuit 14e
An error signal is sent to the control circuit 15a through the control circuit 15a, and the control circuit 15a, which has received the error signal, stops the operation of the inverter device 20 and displays this stop to the outside.
【0015】すなわち図1に示したインバータ装置20
によれば、インバータ装置20が三相交流電圧を出力す
るものであっても、インタフェース回路16aには3組
のゲート駆動回路14に対して共通にエラー信号伝達用
の高耐圧ホトカプラを1個備えればよい。That is, the inverter device 20 shown in FIG.
According to this, even if the inverter device 20 outputs a three-phase AC voltage, the interface circuit 16a is provided with one high-voltage photocoupler for transmitting an error signal commonly to the three sets of gate drive circuits 14. Just do it.
【0016】[0016]
【発明の効果】この発明によれば、上述の如く、インバ
ータ装置が三相交流電圧を出力するものであっても、前
記インタフェース回路にはエラー信号伝達用の高耐圧ホ
トカプラを1個備えればよく、インバータ装置の回路の
簡素化,低価格化が計れる。According to the present invention, as described above, even if the inverter device outputs a three-phase AC voltage, if the interface circuit is provided with one high-voltage photocoupler for transmitting an error signal. Often, the circuit of the inverter device can be simplified and the price can be reduced.
【図1】この発明の制御方法の実施例を示すインバータ
装置の回路構成図FIG. 1 is a circuit configuration diagram of an inverter device showing an embodiment of a control method of the present invention.
【図2】従来の制御方法を示すインバータ装置の回路構
成図FIG. 2 is a circuit configuration diagram of an inverter device showing a conventional control method.
1…インバータ装置、2…交流電源、3…負荷、11…
整流回路、12…逆変換回路、12a,12b…IGB
T、13,14,21…ゲート駆動回路、15,15a
…制御回路、16,16a…インタフェース回路。DESCRIPTION OF SYMBOLS 1 ... Inverter apparatus, 2 ... AC power supply, 3 ... Load, 11 ...
Rectifier circuit, 12 ... inverting circuit, 12a, 12b ... IGB
T, 13, 14, 21 ... gate drive circuit, 15, 15a
... Control circuit, 16, 16a ... Interface circuit.
Claims (1)
スをブリッジ接続して形成される逆変換回路と、該パワ
ーデバイスをオン・オフさせる該複数個のゲート駆動回
路と、これらのゲート駆動回路との間で制御信号を送受
する制御回路とにより、該逆変換回路に入力される直流
電圧を所望の周波数,電圧の交流電圧に変換し、この交
流電圧を負荷に供給するインバータ装置において、 ブリッジ接続された前記パワーデバイスの内、上アーム
のそれぞれのパワーデバイスの電流センス端子とソース
端子又はエミッタ端子との間に接続される検出抵抗の両
端電圧が所定の値を超えたときから所定の期間の間は当
該するパワーデバイスのゲート駆動回路の出力をオフ状
態にし、 ブリッジ接続された前記パワーデバイスの内、下アーム
のそれぞれのパワーデバイスの電流センス端子とソース
端子又はエミッタ端子との間に接続される検出抵抗の両
端電圧が所定の値を超えたときに当該するパワーデバイ
スのゲート駆動回路の出力をオフ状態にし、 前記下アームのいずれかのゲート駆動回路に発生した前
記オフ状態を制御回路に伝達して、負荷への給電経路の
地絡に対して保護することを特徴とするインバータ装置
の出力地絡保護方法。1. An inversion circuit formed by bridge-connecting a plurality of power devices with current sense terminals, a plurality of gate drive circuits for turning on / off the power devices, and these gate drive circuits And a control circuit for transmitting and receiving a control signal between the inverter and the inverter. The inverter converts the DC voltage input to the inverter into an AC voltage having a desired frequency and voltage, and supplies the AC voltage to a load. A predetermined period from when the voltage across the detection resistor connected between the current sense terminal and the source terminal or the emitter terminal of each power device of the upper arm of the connected power devices exceeds a predetermined value. During the period, the output of the gate drive circuit of the power device concerned is turned off, and each of the lower arms of the bridge-connected power devices When the voltage across the detection resistor connected between the current sense terminal and the source terminal or the emitter terminal of the power device exceeds a predetermined value, the output of the gate drive circuit of the power device is turned off; An output ground fault protection method for an inverter device, wherein the off state generated in one of the gate drive circuits of the arm is transmitted to a control circuit to protect against a ground fault in a power supply path to a load.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP02748998A JP3589006B2 (en) | 1998-02-09 | 1998-02-09 | Inverter output ground fault protection method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP02748998A JP3589006B2 (en) | 1998-02-09 | 1998-02-09 | Inverter output ground fault protection method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11234896A true JPH11234896A (en) | 1999-08-27 |
JP3589006B2 JP3589006B2 (en) | 2004-11-17 |
Family
ID=12222557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP02748998A Expired - Fee Related JP3589006B2 (en) | 1998-02-09 | 1998-02-09 | Inverter output ground fault protection method |
Country Status (1)
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JP (1) | JP3589006B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013150866A1 (en) * | 2012-04-06 | 2013-10-10 | 住友電気工業株式会社 | Switching circuit |
-
1998
- 1998-02-09 JP JP02748998A patent/JP3589006B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013150866A1 (en) * | 2012-04-06 | 2013-10-10 | 住友電気工業株式会社 | Switching circuit |
JP2013219885A (en) * | 2012-04-06 | 2013-10-24 | Sumitomo Electric Ind Ltd | Switching circuit |
Also Published As
Publication number | Publication date |
---|---|
JP3589006B2 (en) | 2004-11-17 |
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