JPH11234348A - Data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of wirings for realizing the differential transmission of respective plural data bits. SOLUTION: The differential transmission of respective two bits D0 and D1 is realized by the three wirings 31, 32 and 33 between a transmission unit 11 and a reception unit 21. One is a first data line 31 corresponding to the bit D0, another one is a second data line 32 corresponding to the bit D1 and the other one is a reference line 33. In the case that the values of the bits D0 and D1 are different from each other, the reference line 33 is not used, the second data line 32 is turned to a complementary transmission path to the first data line 31 and the first data line 31 is turned to the complementary transmission path to the second data line 32. In the case that the values of the bits D0 and D1 are the same, a voltage for indicating the inverted value of the value of the data bits D0 and D1 is supplied to the reference line 33 so as to turn the reference line 33 to the complementary transmission path to the respective first and second data lines 31 and 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system for realizing differential transmission of a plurality of data bits.

[0002]

2. Description of the Related Art With the processing of huge amounts of moving image data, high-speed data transmission between a plurality of semiconductor integrated circuits mounted on a printed wiring board has been demanded. D in response
In the field of RAM (dynamic random access memory),
Rambus specifications and SyncLink specifications are known as clock synchronous high-speed input / output interface specifications. The former is a specification developed by Rambus in the United States and adopts an open drain type interface. The latter is a US JEDEC (Joint Electron
This is a specification proposed by the Device Engineering Council, which is a SSTL (stub series terminated tranceive).
r logic).

[0003]

In the above-mentioned conventional input / output interface specifications, a plurality of data bits are each transmitted by one data line. Such a single transmission system has a problem that it is easily affected by external noise.

Conventionally, differential data transmission excellent in common mode noise removal performance has been known. This achieves transmission of one data bit using two data lines. However, when trying to realize differential transmission of each of a plurality of data bits between semiconductor integrated circuits on a printed wiring board, the number of wirings is two in comparison with the single transmission method.
As a result, the wiring area on the printed wiring board becomes large, and the number of pins of the package of the semiconductor integrated circuit increases.

An object of the present invention is to reduce the number of wirings for realizing differential transmission of each of a plurality of data bits.

[0006]

In order to achieve the above-mentioned object, the present invention realizes differential transmission of each of two data bits with three wirings. One of the three wirings is a first data line, the other is a second data line,
The other one is a reference line. If the values of the two data bits to be transmitted are different from each other, without using a reference line,
The second data line is a complementary transmission path for the first data line, and the first data line is a complementary transmission path for the second data line. If the values of the two data bits to be transmitted are the same, the values of the first and second data bits are such that the reference line is the complementary transmission path for each of the first and second data lines. Is supplied to the reference line.

More specifically, a data transmission system according to the present invention transmits first and second data bits in a data transmission system for differential transmission of each of first and second data bits. And a receiving unit for receiving the first and second data bits, a first data line, a second data line, and a reference line interposed between the transmitting unit and the receiving unit, respectively. Are adopted. In addition, when the value of the first data bit is different from the value of the second data bit, the transmitting unit sets the second data line as a complementary transmission path to the first data line, and A voltage representing the value of the first data bit is applied to the first data line so that the line is a complementary transmission path to the second data line.
A voltage representing the value of the second data bit is supplied to each of the second data lines, and the value of the first data bit is
If the values of the data bits are the same, the voltages representing the values of the first and second data bits are changed so that the reference line is a complementary transmission path for each of the first and second data lines. It has a function of supplying a voltage representing an inverted value of the value of the first and second data bits to the first and second data lines, respectively, to the reference line.

[0008]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a configuration example of a data transmission system according to the present invention. 1 includes two semiconductor integrated circuits mounted on a printed wiring board, for example, two large scale integrated circuits (LSIs) 1 and 2.
Are connected by a transmission path 3. The LSI 1 transmits eight data bits D0 to D7 forming one word to the transmission path 3, and the LSI 2 receives the 8-bit word transmitted via the transmission path 3. The twelve wires constituting the transmission path 3 are connected to a terminal voltage VT
Each is pulled up to T.

The LSI 1 incorporates four transmission units (T0, T1, T2, T3) 11, 12, 13, and 14 that perform transmission operations when the enable signal EN1 is activated. The transmission unit 11 transmits the bits D0 and D
1 is a unit for transmitting the data line DL1 if the value of the bit D0 is different from the value of the bit D1.
Is a complementary transmission path for the data line DL0, and the voltage representing the value of the bit D0 is a data line DL0 so that the data line DL0 is a complementary transmission path for the data line DL1.
When the voltage representing the value of bit D1 is supplied to data line DL1 and the value of bit D0 and the value of bit D1 are the same, reference line REF0 is connected to data line DL1.
The voltages representing the values of bits D0 and D1 are applied to data lines DL0 and DL1, respectively, and the voltages representing the inversions of the values of bits D0 and D1 are applied to reference line REF0 so as to provide a complementary transmission path for each of 0 and DL1. Supply. The other three transmission units 12, 13, and 14 have similar functions, DL2 to DL7 are data lines, and REF1 to REF3 are reference lines. The power supply voltages VDDQ and VSSQ generated inside the LSI 1 from the external power supply voltages VDD and VSS are supplied to the output stages of the four transmission units 11 to 14, respectively.

The data lines DL0 and DL1 are wirings that are twisted twice around the reference line REF0 so as to form a twisted pair line. The twist is the data line DL
It is provided at each of one third and two thirds of the total length of 0 and DL1. Data lines DL2 and DL
3 is a reference line RE to form another twisted pair line.
This is a wiring to which one twist is given around F1.
The twist is provided at one half of the entire length of the data lines DL2 and DL3. Thereby, the influence of data lines DL0 and DL1 is reduced by data lines DL2 and DL2.
3, and the effects of the data lines DL2 and DL3 are equally applied to the data lines DL0 and DL1.
The reference line REF1 is shielded by the data lines DL2 and DL3, and the reference line REF0 is shielded by the data lines DL0 and DL1. Similarly, the twisted pair of the data lines DL4 and DL5 is given two twists around the reference line REF2, and the twisted pair of the data lines DL6 and DL7 is given one twist around the reference line REF3. Note that the number of twists is not limited to the above example.

The LSI 2 includes the four transmission units 1 described above.
Four receiving units (R0, R1, R2, R3) 21, 22, 23, 2 corresponding to each of 1, 12, 13, 14
4 built-in. These four receiving units 21 and 2
Reference numeral 4 denotes a signal receiving operation when the enable signal EN2 is activated. The receiving unit 21 is a unit for receiving the bits D0 and D1, and when the voltage of the data line DL0 and the voltage of the data line DL1 are different, the receiving unit 21 compares the voltage of the data line DL0 with the voltage of the data line DL1. The respective values of the bits D0 and D1 are determined by comparison, and when the voltage of the data line DL0 and the voltage of the data line DL1 are the same, the comparison between the voltage of the data line DL0 and the voltage of the reference line REF0 is performed. The value of bit D0 is
The value of the bit D1 is determined by comparing the voltage of the data line DL1 with the voltage of the reference line REF0.
The other three receiving units 22, 23, and 24 are units having the same function. Note that XD0 to XD7 in FIG.
Indicates inverted bits of the bits D0 to D7. The output terminal of the transmission unit 12 and the input terminal of the reception unit 22 are arranged reverse to each other in accordance with the odd number of twists of the data lines DL2 and DL3. Transmission unit 14
The same applies to the relationship between the data and the receiving unit 24.

FIG. 2 shows one transmission unit 11 shown in FIG.
2 shows a detailed configuration of each of the receiving unit 21 and the one receiving unit 21. However, the twist of the data lines DL0 and DL1 is not shown.

Referring to FIG. 2, the transmission unit 11 has first, second and third drivers 51, 52 and 53, each of which performs a transmission operation when the enable signal EN1 is activated. The first driver 51 is a driver for supplying a voltage representing the value of the bit D0 to the data line (DL0) 31. The second driver 52 is a driver for supplying a voltage representing the value of the bit D1 to the data line (DL1) 32. When the value of the bit D0 is equal to the value of the bit D1, the third driver 53 outputs the bit D0
And a voltage representing the inverted value of D1 as a reference line (REF0)
33, and if the value of the bit D0 is different from the value of the bit D1, the third line to the reference line (REF0) 33
Is a driver having means for holding the output of the driver 53 in a high impedance state.

The data line DL0, the data line DL1 and the reference line REF0 are pulled up to a termination voltage VTT via termination resistors 41, 42 and 43, respectively. Among these three terminating resistors, two terminating resistors 41 and 42 for pulling up each of the data lines DL0 and DL1 have a resistance value R.
And another one for pulling up the reference line REF0.
The terminating resistor 43 has a resistance value R / 2.

The receiving unit 21 includes first, second, and third comparators 61, 62, and 63 that perform a receiving operation when the enable signal EN2 is activated.
The first comparator 61 uses the voltage of the data line DL0 and the voltage of the reference line REF0, the second comparator 62 uses the voltage of the data line DL1 and the voltage of the reference line REF0, and the third comparator 63 uses the voltage of the data line DL0. Voltage and data line D
L1 is compared with the voltage of L1. When the voltage of the data line DL0 is different from the voltage of the data line DL1, the third comparator 63 sets the bits D0 and D1.
Are determined, and when the voltage of the data line DL0 and the voltage of the data line DL1 are the same, the value of the bit D0 is determined by the first comparator 61 and the value of the bit D1 is determined by the second comparator 62. Are determined.

FIG. 3 shows three lines DL0 and DL in FIG.
An example of a voltage change of each of 1 and REF0 is shown. In the period 1, since the enable signal EN1 is set to the inactivation level “L”, the first, second, and third drivers 51, 52, and 53 hold their outputs in a high impedance state. As a result, the three wirings DL0, D0
The voltages of L1 and REF0 are both equal to the termination voltage VTT. In the periods 2 to 7, the setting of the enable signal EN1 is changed to the activation level “H”, so that the first and second
Each of the third drivers 51, 52, and 53 performs a transmission operation according to the data bits D0 and D1. Period 2
In this case, D0 = 1 and D1 = 1. Therefore, in the period 2, the voltages of the data lines DL0 and DL1 become the high-level voltage VH representing the bit value 1 and the voltage of the reference line REF0 becomes the low-level voltage VL representing the bit value 0.
Here, the voltage VH is a voltage higher by ΔV than the terminal voltage VTT, and the voltage VL is a voltage lower by ΔV than the terminal voltage VTT. In period 3, D0 = 0 and D1 = 0. Therefore, in the period 3, the data lines DL0 and DL1
Is a low level voltage VL representing a bit value 0.
Then, the voltage of the reference line REF0 becomes the high-level voltage VH representing the bit value 1. In period 4, D0 = 0 and D1 = 1
In period 5, D0 = 1 and D1 = 0. Therefore, in the period 4 and the period 5, the output of the third driver 53 is in a high impedance state, so that the reference line REF
A voltage of 0 equals the termination voltage VTT. The state in period 6 is the same as period 3, and the state in period 7 is the same as period 2. As described above, the three wirings DL0, DL1, and R
The voltage amplitude of each of EF0 is 2ΔV. For example, VDD = + 3.3V, VSS = 0V, VTT = +
At 1.5V, ΔV = 0.4V (based on the output value of the transmitting unit 11). By employing such a small-amplitude interface, high-speed data transmission becomes possible.

FIG. 4 shows three lines DL0 and DL in FIG.
1 shows a combination of voltages of 1 and REF0. FIG.
Parentheses in the middle indicate the current flowing through each wiring. According to FIG. 4, when the voltages of the data lines DL0 and DL1 are the high-level voltage VH, the voltage of the reference line REF0 is the low-level voltage VL, and the current flowing into the reference line REF0 (− 2I) is larger than the data lines DL0 and D0.
It is twice the magnitude of the current (+ I) flowing out of each of L1. The voltage of the data line DL0 is the high-level voltage VH, and the voltage of the data line DL1 is the low-level voltage VH.
If L, the voltage of the reference line REF0 is the termination voltage V
TT, the current (+ I) flowing out of the data line DL0
Is equal to the magnitude of the current (-I) flowing into the data line DL1. When the voltage of the data line DL0 is the low-level voltage VL and the voltage of the data line DL1 is the high-level voltage VH, the voltage of the reference line REF0 is the termination voltage VTT and flows into the data line DL0. The magnitude of the current (-I) is equal to the magnitude of the current (+ I) flowing out of the data line DL1. Data lines DL0 and DL
1 is the low level voltage VL, the voltage of the reference line REF0 is the high level voltage VH, and the magnitude of the current (+ 2I) flowing out of the reference line REF0 is the data lines DL0 and DL1. Is twice the magnitude of the current (-I) flowing into each of the.

FIGS. 5A to 5D show combinations of currents flowing through each of the three wirings DL0, DL1 and REF0 in FIG. As described above, the resistance value (R / 2) of the terminating resistor for pulling up the reference line REF0 is set so that the current flowing through the reference line REF0 is twice the current flowing through each of the data lines DL0 and DL1. This is half of the resistance value (R) of the terminating resistor for pulling up each of the data lines DL0 and DL1. As can be seen from FIGS. 5A to 5D, the sum of the inflow current and the outflow current of the power supply for supplying the termination voltage VTT is always 0.
It is.

Hereinafter, the internal configuration of each of the transmission unit 11 and the reception unit 21 in FIG. 2 will be briefly described.

FIG. 6 shows a configuration example of the transmission unit 11 in FIG. First for driving data line DL0
Driver 51 includes a NAND gate 101 and a PMOS
The driver includes a transistor 102, an inverter 103, a NOR gate 104, and an NMOS transistor 105, and receives a data bit D0 and an enable signal EN1 as inputs. The second driver 52 for driving the data line DL1 includes a NAND gate 201
, A PMOS transistor 202 and an inverter 203
, NOR gate 204 and NMOS transistor 20
5 is a driver that receives the data bit D1 and the enable signal EN1 as inputs. Reference line RE
The third driver 53 for driving F0 includes two inverters 301 and 302, a NAND gate 303,
A PMOS transistor 304, an inverter 305,
The driver includes a NOR gate 306 and an NMOS transistor 307, and receives two data bits D0 and D1 and an enable signal EN1 as inputs.

FIG. 7 shows a modification of the transmission unit 11 of FIG. The transmission unit 11a in FIG. 7 is obtained by adding a transition acceleration circuit 310 to the third driver 53 in the transmission unit 11 in FIG. The transition acceleration circuit 310
A first delay circuit 311 including an odd number of inverters;
OR gate 312, PMOS transistor 313,
A second delay circuit 314 including an odd number of inverters;
It comprises an AND gate 315 and an NMOS transistor 316, and the voltage on the reference line REF0 is
At the time of transition from the voltage (VH) representing the bit value to another voltage (VL or VTT), the voltage (V
L) to the reference line REF0, and the voltage of the reference line REF0 is changed from the voltage (VL) representing the bit value 0 to another voltage (V
H or VTT), a bit value of 1 for a fixed time
Is supplied to the reference line REF0. Thereby, the voltage transition of the reference line REF0 is accelerated, which is convenient.

FIG. 8 shows another modification of the transmission unit 11 of FIG. The transmission unit 11b in FIG.
The voltage initialization circuit 320 is added to the third driver 53 in the transmission unit 11 of FIG. Voltage initialization circuit 3
Reference numeral 20 denotes an exclusive OR gate 321, an inverter 322, a NOR gate 323, and an NMOS transistor 324, and an enable signal EN.
When 1 is set to the activation level “H” and the value of the data bit D0 is different from the value of the data bit D1, the voltage (VL) representing the bit value 0 and the voltage (VH) representing the bit value 1 , Ie, the terminal voltage VTT to the reference line REF0. Thereby, the voltage (VH) representing the bit value 1 is applied to the reference line REF0.
And neither the voltage (VL) representing the bit value 0 is supplied,
This is advantageous because the voltage of the reference line REF0 is quickly determined to the termination voltage VTT. The transition acceleration circuit 310 in FIG.
May be added to the third driver 53 in the transmission unit 11b of FIG.

FIG. 9 shows a configuration example of the receiving unit 21 in FIG. Data line DL0 voltage and reference line REF
A first comparator 61 for comparing with a voltage of 0
Are two PMOS transistors 401 and 402 and 3
And NMOS transistors 403, 404, and 405. Data line DL1 voltage and reference line REF
A second comparator 62 for comparing with a voltage of 0
Are two PMOS transistors 411 and 412 and 3
And NMOS transistors 413, 414 and 415. Data line DL0 voltage and data line DL
A third comparator 63 for comparing with the voltage of 1
Are two PMOS transistors 421 and 422 and 3
And NMOS transistors 423, 424, and 425. Each of the first, second, and third comparators 61, 62, and 63 is a circuit having excellent common mode noise removal performance. The output of the first comparator 61 and one output of the third comparator 63 are data bits XD0 (an inverted bit of the bit D0).
, And the output of the second comparator 62 and the other output of the third comparator 63 are wired-OR connected to determine the data bit XD1 (the inverted bit of the bit D1). .
Thus, when the voltage of the data line DL0 is different from the voltage of the data line DL1, the third comparator 63 determines the value of each of the bits XD0 and XD1. When the voltage of the data line DL0 is the same as the voltage of the data line DL1, the first comparator 61 determines the value of the bit XD0, and the second comparator 62 determines the value of the bit XD1.

The arrangement of the terminating resistor array 4 in FIG. 1, that is, the three terminating resistors 41, 42 and 43 in FIG. 2 can be omitted. At this time, the reference line REF0 is set to the bit D0
Is set to a floating state when the value of bit D1 is different from the value of bit D1. According to the configuration of FIG. 9, even in such a case, the third comparator 63 sets the bits XD0 and XD
1 can be correctly determined.

FIG. 10 shows a modification of the receiving unit 21 of FIG. The receiving unit 21a of FIG.
The comparison result of the comparator 61 and the third comparator 6
4, a fourth comparator 64 for determining the value of the bit D0 based on one comparison result of the third comparator 63, and a bit based on the comparison result of the second comparator 62 and the other comparison result of the third comparator 63. And a fifth comparator 65 for determining the value of D1. The fourth comparator 64 includes two PMOS transistors 43
1,432 and five NMOS transistors 433,4
34, 435, 436 and 437, which compares the output voltage of the first comparator 61 with the termination voltage VTT and compares one output voltage of the third comparator 63 with the termination voltage VTT. As a result, bit D0
Is determined. Fifth comparator 65
Are two PMOS transistors 441 and 442 and 5
NMOS transistors 443, 444, 445, 4
46, 447 for comparing the output voltage of the second comparator 62 with the termination voltage VTT, and
Output voltage of the other comparator 63 and the termination voltage VTT
The value of bit D1 is determined by comparing According to the configuration of FIG. 10, it is possible to perform more reliable bit value determination than in the case of FIG.

FIG. 11 shows a modification of FIG. According to FIG. 11, power supply voltages VDDQ2 and VSSQ2 different from the power supply voltages VDDQ and VSSQ are supplied to the output stage of the third driver 53. That is, the third driver 53 in FIG. 11 determines the supply voltage to the reference line REF0 such that the voltage amplitude on the reference line REF0 is twice the voltage amplitude on the data lines DL0 and DL1. Data line DL0, data line DL1, and reference line R
Each of the terminating resistors 41, 42, 43 for pulling up each of the EF0 to the terminating voltage VTT has a resistance value R.

FIG. 12 shows three lines DL0, DL0,
An example of each voltage change of DL1 and REF0 is shown. In period 2, D0 = 1 and D1 = 1. Therefore, in the period 2, the voltage of each of the data lines DL0 and DL1 becomes the high-level voltage VH representing the bit value 1 and the voltage of the reference line REF0 becomes the low-level voltage VH representing the bit value 0.
LL. Here, the voltage VH is ΔΔ from the termination voltage VTT.
V, and the voltage VLL is a voltage lower than the termination voltage VTT by 2ΔV. In period 3, D0 = 0 and D1 = 0. Therefore, in the period 3, the data line D
Each of the voltages of L0 and DL1 is set to a low-level voltage VL representing the bit value 0, and the voltage of the reference line REF0 is set to the bit value 1
At a high level VHH. Where the voltage V
L is a voltage lower by ΔV than the termination voltage VTT, and voltage VHH is a voltage higher by 2ΔV than the termination voltage VTT. In period 4, D0 = 0 and D1 = 1, and in period 5, D0 = 1 and D1 = 0. Therefore, in the periods 4 and 5, the output of the third driver 53 is in the high impedance state, and the voltage of the reference line REF0 becomes equal to the termination voltage VTT. The state in period 6 is the same as period 3, and the state in period 7 is the same as period 2. As described above, the voltage amplitude of each of the data lines DL0 and DL1 is 2ΔV, whereas the voltage amplitude of the reference line REF0 is 4ΔV. Therefore, the three wirings DL0, DL
The sum of the voltage changes of 1 and REF0 is 0 in any period, which is convenient when a voltage equalizing mechanism (not shown) for these three wirings is provided.

FIG. 13 shows three lines DL0, DL0 in FIG.
The combination of the voltages of DL1 and REF0 is shown.
The current in parentheses in FIG. 13 indicates the current flowing through each wiring.
According to FIG. 13, when each of the data lines DL0 and DL1 is at the high-level voltage VH, the reference line RE
The voltage of F0 is a low-level voltage VLL, and the reference line R
The magnitude of the current (−2I) flowing into EF0 is determined by the data line D
This is twice the magnitude of the current (+ I) flowing out of each of L0 and DL1. When the voltage of the data line DL0 is the high-level voltage VH and the voltage of the data line DL1 is the low-level voltage VL, the voltage of the reference line REF0 is the termination voltage VTT and flows out of the data line DL0. The magnitude of the current (+ I) is equal to the magnitude of the current (−I) flowing into the data line DL1. When the voltage of the data line DL0 is the low-level voltage VL and the voltage of the data line DL1 is the high-level voltage VH, the reference line RE
The voltage of F0 is the termination voltage VTT, and the current (-I) flowing into the data line DL0 is equal to the current (+ I) flowing out of the data line DL1. Data line DL
When each of the voltages 0 and DL1 is the low-level voltage VL, the voltage of the reference line REF0 is the high-level voltage VHH, and the current flowing out of the reference line REF0 (+2
The magnitude of I) is twice the magnitude of the current (-I) flowing into each of the data lines DL0 and DL1.

FIGS. 14A to 14D show combinations of currents flowing through the three wirings DL0, DL1 and REF0 in FIG. The current flowing through the reference line REF0 is equal to 2 of the current flowing through each of the data lines DL0 and DL1.
As described above, the resistance value (R) of the terminating resistor for pulling up the reference line REF0 is doubled so that the resistance value (R) of the terminating resistor for pulling up each of the data lines DL0 and DL1 is doubled. It is equal to FIG.
As can be seen from (a) to (d), the sum of the inflow current and outflow current of the power supply for supplying the termination voltage VTT is always zero.

The data transmission between a plurality of LSIs mounted on a printed wiring board has been described above.
The present invention can also be applied to data transmission between a plurality of LSI chips constituting one multi-chip module and data transmission within an LSI chip. The number of data bits constituting one word is not limited to eight, but is arbitrary.

[0032]

As described above, according to the present invention, the differential transmission of each of the first and second data bits is performed by:
Where four wires are required in the conventional differential transmission method, 3
Since the present invention is realized by the book wiring, that is, the first data line, the second data line, and the reference line, it is possible to obtain an effect that differential data transmission excellent in common mode noise removal performance can be achieved with a small number of wirings.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a data transmission system according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of each of one transmission unit and one reception unit in FIG. 1;

FIG. 3 is a timing chart showing an example of a voltage change of each of three wires in FIG. 2;

FIG. 4 is a diagram showing combinations of voltages of three wires in FIG. 2;

5 (a), (b), (c) and (d) are diagrams showing combinations of currents flowing through each of the three wirings in FIG.

FIG. 6 is a detailed circuit diagram illustrating a configuration example of a transmission unit in FIG. 2;

FIG. 7 is a detailed circuit diagram showing a modification of the transmission unit of FIG. 6;

FIG. 8 is a detailed circuit diagram showing another modification of the transmission unit of FIG. 6;

FIG. 9 is a detailed circuit diagram illustrating a configuration example of a receiving unit in FIG. 2;

FIG. 10 is a detailed circuit diagram showing a modified example of the receiving unit of FIG.

FIG. 11 is a block diagram showing a modification of FIG. 2;

12 is a timing chart showing an example of a voltage change of each of three wires in FIG. 11;

FIG. 13 is a diagram showing combinations of voltages of three wires in FIG. 11;

14 (a), (b), (c) and (d) show FIG.
It is a figure showing the combination of the electric current which flows through each of three middle wirings.

[Explanation of symbols]

 1, 2 LSI (Semiconductor Integrated Circuit) 3 Transmission line 4 Terminating resistor array 11 to 14, 11a, 11b Transmitting unit 21 to 24, 21a Receiving unit 31, 32 Data line 33 Reference line 41 to 43 Terminating resistor 51 to 53 Driver 61 To 65 Comparator 310 Transition acceleration circuit 320 Voltage initialization circuit D0 to D7 Data bits DL0 to DL7 Data lines EN1, EN2 Enable signals REF0 to REF3 Reference lines VH, VHH Voltages representing bit value 1 VL, VLL Voltages representing bit value 0 VTT termination voltage XD0-XD7 Data bit

Claims (13)

[Claims] 1. A data transmission system for differential transmission of each of first and second data bits, wherein: a transmission unit for transmitting the first and second data bits; and And a receiving unit for receiving a second data bit; and a first data line, a second data line, and a reference line interposed between the transmitting unit and the receiving unit, respectively, When the value of the first data bit is different from the value of the second data bit, the second data line is used as a complementary transmission path for the first data line;
A voltage representing the value of the first data bit to the first data line so as to make the data line a complementary transmission path to the second data line. Are respectively supplied to the second data lines, and when the value of the first data bit and the value of the second data bit are the same, the reference line is connected to the first and second data lines. Voltage to represent the value of the first and second data bits to the first and second data lines, respectively, so as to provide a complementary transmission path for each of the data lines. A data transmission system having a function of supplying a voltage representing an inverted value of the value to each of the reference lines. 2. The data transmission system according to claim 1, wherein the receiving unit is configured to output the first data line when a voltage of the first data line is different from a voltage of the second data line. Of the first and second data lines by comparing the voltage of the first data line with the voltage of the second data line.
And if the voltage of the first data line and the voltage of the second data line are the same, the voltage of the first data line and the reference A function of determining the value of the first data bit by comparing with the voltage of the line, and determining the value of the second data bit by comparing the voltage of the second data line with the voltage of the reference line; A data transmission system, characterized in that: 3. The data transmission system according to claim 1, wherein the transmission unit and the reception unit are units incorporated in separate semiconductor integrated circuits, respectively, and the first data line and the second data line are connected to each other. A data transmission system, wherein each of the data line and the reference line is a wiring on a printed wiring board. 4. The data transmission system according to claim 1, wherein the first and second data lines are wires twisted about the reference line so as to form a twisted pair line. Characteristic data transmission system. 5. The data transmission system according to claim 1, further comprising three terminating resistors for pulling up each of the first data line, the second data line, and the reference line to a predetermined terminating voltage. A data transmission system, comprising: 6. The data transmission system according to claim 5, wherein the transmission unit supplies the reference line such that a voltage amplitude on the reference line is equal to a voltage amplitude on the first and second data lines. And a terminating resistor for pulling up the reference line among the three terminating resistors, wherein a current flowing through the reference line is equal to the first and second data lines. Has a resistance value that is half of the other two terminating resistors for pulling up each of the first and second data lines so as to be twice the current flowing through each of the first and second data lines. And a data transmission system. 7. The data transmission system according to claim 5, wherein the transmission unit transmits the signal to the reference line such that a voltage amplitude on the reference line is twice as large as a voltage amplitude on the first and second data lines. And a terminating resistor for pulling up the reference line out of the three terminating resistors, wherein a current flowing through the reference line is equal to the first and second currents. Each of the first and second data lines has a resistance value equal to two other terminating resistors for pulling up each of the first and second data lines so as to be twice the current flowing through each of the data lines. Data transmission system. 8. The data transmission system according to claim 1, wherein the transmission unit is configured to supply a voltage representing a value of the first data bit to the first data line; A second driver for supplying a voltage representing a value of a second data bit to the second data line; and a value of the first data bit and a value of the second data bit are the same. And a third driver for supplying a voltage representing an inverted value of the values of the first and second data bits to the reference line. 9. The data transmission system according to claim 8, wherein the third driver connects to the reference line when a value of the first data bit is different from a value of the second data bit. A data transmission system comprising means for maintaining an output of the third driver in a high impedance state. 10. The data transmission system according to claim 8, wherein the third driver changes a bit value of 0 when a value of the first data bit is different from a value of the second data bit. A data transmission system comprising: means for supplying an average voltage of a voltage representing a bit value 1 and a voltage representing the bit value 1 to the reference line. 11. The data transmission system according to claim 8, wherein the voltage of the reference line is one bit value.
When a voltage representing a bit value 0 is supplied to the reference line for a certain period of time when the voltage representing the bit line transitions to another voltage, and when the voltage of the reference line transitions from a voltage representing a bit value 0 to another voltage, And a means for supplying a voltage representing a bit value of 1 to the reference line for a fixed time. 12. The data transmission system according to claim 1, wherein the receiving unit comprises: a first comparator for comparing a voltage of the first data line with a voltage of the reference line; A second comparator for comparing a voltage of a data line with a voltage of the reference line; a third comparator for comparing a voltage of the first data line with a voltage of the second data line; When the voltage of the first data line is different from the voltage of the second data line, the third comparator determines the value of each of the first and second data bits. ,
And, when the voltage of the first data line and the voltage of the second data line are the same, the value of the first data bit is changed by the second comparator by the first comparator. A data transmission system, wherein a value of each of the second data bits is determined. 13. The data transmission system according to claim 1, wherein the receiving unit comprises: a first comparator for comparing a voltage of the first data line with a voltage of the reference line; A second comparator for comparing a voltage of a data line with a voltage of the reference line; a third comparator for comparing a voltage of the first data line with a voltage of the second data line; A fourth comparator for determining a value of the first data bit based on a comparison result of the first comparator and a comparison result of the third comparator; and a comparison result of the second comparator. A data transmission system, comprising: a fifth comparator for determining a value of the second data bit based on a comparison result of the third comparator.