JP3507687B2 - Data transmission system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system for realizing differential transmission of each of a plurality of data bits.

[0002]

2. Description of the Related Art Due to the huge amount of processing of moving image data, high-speed data transmission between a plurality of semiconductor integrated circuits mounted on a printed wiring board is required. In response to this, D
In the field of RAM (dynamic random access memory),
Rambus specifications and SyncLink specifications are known as clock synchronous high-speed input / output interface specifications. The former is a specification developed by Rambus, Inc. of the United States and employs an open drain type interface. The latter is JEDEC (Joint Electron
It is a specification advocated by the Device Engineering Council, which is SSTL (stub series terminated tranceive).
It employs a small-amplitude interface called r logic).

[0003]

In each of the above-mentioned conventional input / output interface specifications, a plurality of data bits are transmitted by one data line. Such a single transmission system has a problem that it is easily affected by external noise.

Conventionally, differential data transmission excellent in common mode noise elimination performance is known. This achieves the transmission of one data bit using two data lines. However, when it is attempted to realize differential transmission of each of a plurality of data bits between semiconductor integrated circuits on a printed wiring board, the number of wirings is 2 compared to the single transmission method.
As a result, the wiring area on the printed wiring board becomes large and the number of pins of the package of the semiconductor integrated circuit increases.

An object of the present invention is to reduce the number of wirings for realizing differential transmission of each of a plurality of data bits.

[0006]

In order to achieve the above object, the present invention realizes differential transmission of each of two data bits with three wires. One of the three wirings is the first data line, the other is the second data line,
The remaining one is a complementary data line. The voltage representing the value of the first data bit is applied to the first data line, the voltage representing the value of the second data bit is applied to the second data line, and the value of the first data bit is applied to the complementary data line. A voltage representing the inverted value of is supplied. The first data line and the complementary data line are
Used for differential transmission of the first data bit. When the value of the first data bit and the value of the second data bit are different from each other, the second data line and the first data line have the same value of the value of the first data bit and the value of the second data bit. If the values are the same, the second data line and the complementary data line are respectively used for differential transmission of the second data bit.

Specifically, the data transmission system according to the present invention transmits the first and second data bits in the data transmission system for differential transmission of each of the first and second data bits. And a receiving unit for receiving the first and second data bits, and a first data line, a second data line and complementary data interposed between the transmitting unit and the receiving unit, respectively. This is a configuration that employs a line and a line. Moreover, the transmission unit supplies the voltage representing the value of the first data bit to the first data line, the voltage representing the value of the second data bit to the second data line, and the voltage representing the value of the first data bit. It has a function of supplying a voltage representing an inverted value to each complementary data line. The receiving unit also determines the value of the first data bit by comparing the voltage of the first data line and the voltage of the complementary data line, and determines the voltage of the first data line and the voltage of the second data line. When is different from each other, the voltage of the first data line is compared with the voltage of the second data line, and when the voltage of the first data line and the voltage of the second data line are the same, complementary It has a function of determining the value of the second data bit by comparing the voltage of the data line with the voltage of the second data line.

[0008]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a configuration example of a data transmission system according to the present invention. The system of FIG. 1 includes two semiconductor integrated circuits mounted on a printed wiring board, for example, two large scale integrated circuits (LSIs) 1 and 2.
Are connected by a transmission line 3. The LSI1 transmits eight data bits D0 to D7 forming one word to the transmission line 3, and the LSI2 receives the 8-bit word transmitted via the transmission line 3. The twelve wirings forming the transmission line 3 are terminated by the termination voltage VT via the termination resistor string 4.
Each is pulled up to T.

The LSI 1 incorporates four transmission units (T0, T1, T2, T3) 11, 12, 13, 14 which perform a transmission operation when the enable signal EN1 is activated. The transmission unit 11 has bits D0 and D
1, which is a unit for transmitting 1, and outputs a voltage representing the value of bit D0 to the data line DL0, a voltage representing the value of bit D1 to the data line DL1, and a voltage representing the inverted value of the value of bit D0. These are supplied to the line XDL0. The other three transmitting units 12, 13, 14 are units having the same function, DL2-DL7 are data lines, and XDL2, XDL4, and XDL6 are complementary data lines. The power supply voltages VDDQ and VS generated inside the LSI 1 from the external power supply voltages VDD and VSS
SQ is supplied to the output stage of each of the four transmission units 11-14.

The data line DL0 and the complementary data line XDL0 are wirings twisted twice around the data line DL1 so as to form a twisted pair line. The twist is applied at each of one-third and two-thirds of the total length of the data line DL0 and the complementary data line XDL0. The data line DL2 and the complementary data line XDL2 are
It is a wire that is twisted once around the data line DL3 so as to form a twisted pair wire. The twist is applied at one-half of the total length of the data line DL2 and the complementary data line XDL2. This allows
The influence of the data line DL0 and the complementary data line XDL0 is evenly applied to the data line DL2 and the complementary data line XDL2, and conversely, the influence of the data line DL2 and the complementary data line XDL2 is equally applied to the data line DL0 and the complementary data line XDL0. To be The data line DL3 includes the data line DL2 and the complementary data line XDL2, and the data line DL1 includes the data line D1.
Shielded by L0 and complementary data line XDL0. Similarly, the data line DL4 and the complementary data line XDL4
The twisted pair is twisted twice around the data line DL5, and the twisted pair of the data line DL6 and the complementary data line XDL6 is twisted once around the data line DL7. The number of twists is not limited to the above example.

The LSI 2 is the above-mentioned four transmission units 1
Four receiving units (R0, R1, R2, R3) 21, 22, 23, 2 corresponding to 1, 12, 13, 14 respectively
4 built-in. These four receiving units 21-2
4 is for receiving operation when the enable signal EN2 is activated. The receiving unit 21 is a unit for receiving the bits D0 and D1, determines the value of the bit D0 by comparing the voltage of the data line DL0 with the voltage of the complementary data line XDL0, and
When the voltage of the data line DL1 and the voltage of the data line DL1 are different, the voltage of the data line DL0 and the voltage of the data line DL1 are compared, and when the voltage of the data line DL0 and the voltage of the data line DL1 are the same, complementary. The value of the bit D1 is determined by comparing the voltage of the data line XDL0 and the voltage of the data line DL1. The other three receiving units 2
2, 23 and 24 are units having the same function.
It should be noted that XD0 to XD7 in the figure represent the inverted bits of each of the bits D0 to D7. The output terminal of the transmission unit 12 and the input terminal of the reception unit 22 are connected to the data line DL.
The two and the complementary data lines XDL2 are arranged in opposite directions in accordance with the odd number of twists. The same applies to the relationship between the transmitting unit 14 and the receiving unit 24.

FIG. 2 shows one transmission unit 11 in FIG.
And the detailed structure of each of the receiving units 21. However, the data line DL0 and the complementary data line XDL
The twist of 0 is not shown.

According to FIG. 2, the transmission unit 11 has first, second and third drivers 51, 52 and 53 which perform a transmission operation when the enable signal EN1 is activated. The first driver 51 is a driver for supplying a voltage representing the value of the bit D0 to the data line (DL0) 31. The second driver 52 is a driver for supplying a voltage representing the value of the bit D1 to the data line (DL1) 32. The third driver 53 is a driver for supplying a voltage representing the inverted value of the value of the bit D0 to the complementary data line (XDL0) 33.

The data line DL0, the data line DL1 and the complementary data line XDL0 each have a terminating resistance 4 having a resistance value R.
It is pulled up to the termination voltage VTT via 1, 42 and 43.

The receiving unit 21 has first, second and third comparators 61, 62 and 63 which perform a receiving operation when the enable signal EN2 is activated.
The first comparator 61 compares the voltage of the data line DL0 and the voltage of the complementary data line XDL0 with the second comparator 62.
The third comparator 63 compares the voltage of the data line DL1 with the voltage of the complementary data line XDL0, and the third comparator 63 compares the voltage of the data line DL0 with the voltage of the data line DL1. The value of bit D0 is determined only by the first comparator 61. The value of the bit D1 is the data line DL0.
If the voltage of the data line and the voltage of the data line DL1 are different,
When the voltage of the data line DL0 and the voltage of the data line DL1 are the same, the second comparator 62 makes a determination.

FIG. 3 shows three wirings DL0 and XD in FIG.
An example of voltage changes of L0 and DL1 is shown. In the period 1, since the enable signal EN1 is set to the inactivation level "L", the first, second and third drivers 51, 52 and 53 hold their outputs in the high impedance state. As a result, the three wirings DL0, X
The voltages of DL0 and DL1 are both equal to the termination voltage VTT. In the periods 2 to 7, as a result of changing the setting of the enable signal EN1 to the activation level “H”, the first and second
And the third drivers 51, 52, 53 each perform a transmission operation according to the data bits D0 and D1. Period 2
Then, D0 = 1 and D1 = 1. Therefore, in the period 2, the voltage of each of the data lines DL0 and DL1 becomes the high level voltage VH representing the bit value 1, and the complementary data line XD
The voltage of L0 becomes the low level voltage VL representing the bit value 0. Here, the voltage VH is a voltage higher than the termination voltage VTT by ΔV, and the voltage VL is a voltage lower than the termination voltage VTT by ΔV. In period 3, D0 = 0 and D1 = 0
Is. Therefore, in the period 3, the data lines DL0 and DL0
Each voltage of L1 becomes a low level voltage VL representing a bit value 0, and the voltage of the complementary data line XDL0 becomes a high level voltage VH representing a bit value 1. In period 4, D0 = 0 and D1 = 1, and in period 5, D0 = 1 and D1 = 0. The state of period 6 is the same as period 3, and the state of period 7 is the same as period 2. As mentioned above, the three wires D
The voltage amplitude of each of L0, XDL0, and DL1 is 2ΔV. For example, VDD = + 3.3V, VSS =
When 0V and VTT = + 1.5V, ΔV = 0.4V (based on the output value of the transmission unit 11). The adoption of such a small-amplitude interface enables high-speed data transmission.

FIG. 4 shows three wirings DL0 and XD in FIG.
The combination of the voltages of L0 and DL1 is shown.

The internal structure of each of the transmission unit 11 and the reception unit 21 in FIG. 2 will be briefly described below.

FIG. 5 shows an example of the configuration of the transmission unit 11 in FIG. First for driving the data line DL0
Driver 51 includes a NAND gate 101 and a PMOS
The driver includes a transistor 102, an inverter 103, a NOR gate 104, and an NMOS transistor 105, and receives the data bit D0 and the enable signal EN1. The second driver 52 for driving the data line DL1 includes the NAND gate 111
, PMOS transistor 112, and inverter 113
, NOR gate 114, and NMOS transistor 11
And a data bit D1 and an enable signal EN1. The third driver 53 for driving the complementary data line XDL0 includes an inverter 121, a NAND gate 122, and a PMOS.
The driver includes a transistor 123, an inverter 124, a NOR gate 125, and an NMOS transistor 126, and receives the data bit D0 and the enable signal EN1.

FIG. 6 shows a configuration example of the receiving unit 21 shown in FIG. The first comparator 61 for comparing the voltage of the data line DL0 and the voltage of the complementary data line XDL0 has two PMOS transistors 201 and 202.
And three NMOS transistors 203, 204, 20
It is composed of 5 and 5. The second comparator 62 for comparing the voltage of the data line DL1 and the voltage of the complementary data line XDL0 has two PMOS transistors 211 and 211.
12 and three NMOS transistors 213, 214,
215 and. The third comparator 63 for comparing the voltage of the data line DL0 and the voltage of the data line DL1 has two PMOS transistors 221 and 22.
2 and 3 NMOS transistors 223, 224, 2
And 25. Each of the first, second, and third comparators 61, 62, 63 is a circuit having excellent common mode noise elimination performance. The output of the first comparator 61 is the data bit XD0 (bit D0
(Inverted bit of). Second comparator 62
And the output of the third comparator 63 are wired-OR connected so as to determine the data bit XD1 (inverted bit of the bit D1). Accordingly, when the voltage of the data line DL0 and the voltage of the data line DL1 are different, the value of the bit XD1 is determined by the third comparator 63. When the voltage of the data line DL0 and the voltage of the data line DL1 are the same, the value of the bit XD1 is determined by the second comparator 62.

FIG. 7 shows a modification of the receiving unit 21 of FIG. The receiving unit 21a of FIG. 7 includes the second and third comparators 62 in the receiving unit 21 of FIG.
63 is replaced with one (fourth) comparator 64. The fourth comparator 64 has two PMOs.
It is composed of S transistors 231 and 232 and five NMOS transistors 233, 234, 235, 236 and 237, and has a data line DL0 and a complementary data line XD.
The value of the bit XD1 is determined by comparing each voltage of L0 and the voltage of the data line DL1. According to the configuration of FIG. 7, the bit value determination can be performed with a smaller scale configuration than the case of FIG.

FIG. 8 shows another configuration example of the data transmission system according to the present invention. The system of FIG. 8 has two LSIs 301 and 302 mounted on a printed wiring board.
Is a system that is connected by a transmission line 303. LSI
Reference numeral 301 denotes 16 data bits D0 forming one word
~ D15 is transmitted to the transmission line 303, and the LSI 302 receives the 16-bit word transmitted via the transmission line 303.

The LSI 301 includes four transmission units (T
10, T11, T12, T13) 311, 312, 31
It contains 3,314. The transmission unit 311 is a unit for transmitting the bits D0, D1, D2 and D3, and outputs a voltage representing the value of the bit D0 to the data line DL.
0, the voltage representing the value of the bit D1 to the data line DL1,
The voltage representing the value of the bit D2 is supplied to the data line DL2, the voltage representing the value of the bit D3 is supplied to the data line DL3, and the voltage representing the inverted value of the value of the bit D0 is supplied to the complementary data line XDL0. The other three transmitting units 31
2, 313 and 314 are units having the same function, and DL4 to DL15 are data lines, XDL4 and XDL.
8 and XDL12 are complementary data lines.

The data line DL0 and the complementary data line XDL0 are wirings twisted twice around the data line DL2 so as to form a twisted pair line. Furthermore,
The data line D is placed outside the twisted pair wire so as to sandwich it.
L1 and DL3 are arranged. These five wires form one sub-transmission line. As a result, the influence of the data line DL0 and the complementary data line XDL0 is affected by the data line D.
L1 is evenly applied, and conversely, the influence of the data line DL1 is equally applied to the data line DL0 and the complementary data line XDL0. The mutual relationship between the data line DL3, the data line DL0, and the complementary data line XDL0 is similar. The data line DL2 is shielded by the data line DL0 and the complementary data line XDL0. Therefore, mutual interference between the data line DL2 and the data line DL1 and mutual interference between the data line DL2 and the data line DL3 are prevented. The other 15 wirings form a similar sub-transmission path with 5 wirings as one set. Moreover, the shield wire 304 is inserted between the sub transmission lines adjacent to each other.

The LSI 302 includes four receiving units (R10, R11, R12, R13) 3 corresponding to each of the four transmitting units 311, 312, 313, 314.
21, 322, 323, 324 are built in. The receiving unit 321 is a unit for receiving the bits D0, D1, D2 and D3, and compares the voltage of the data line DL0 with the voltage of the complementary data line XDL0 to determine the bit D.
The value of 0 is determined, and the voltage of the data line DL0 and the data line DL
When the voltage of 1 is different, the voltage of the data line DL0 and the voltage of the data line DL1 are compared, and when the voltage of the data line DL0 and the voltage of the data line DL1 are the same, the voltage of the complementary data line XDL0 And the voltage of the data line DL1 are compared to determine the value of the bit D1. If the voltage of the data line DL0 and the voltage of the data line DL2 are different, the voltage of the data line DL0 is compared with the voltage of the data line DL2. Accordingly, when the voltage of the data line DL0 and the voltage of the data line DL2 are the same, the value of the bit D2 is determined by comparing the voltage of the complementary data line XDL0 and the voltage of the data line DL2, and the data line DL0 is determined. If the voltage of the data line DL3 is different from the voltage of the data line DL3, the data line D0 is compared with the voltage of the data line DL0.
When the voltage of L0 and the voltage of the data line DL3 are the same, the value of the bit D3 is determined by comparing the voltage of the complementary data line XDL0 and the voltage of the data line DL3. The other three receiving units 322, 323, 3
24 is a unit having the same function. It should be noted that XD0 to XD15 in the figure represent the inverted bits of each of the bits D0 to D15.

According to the configuration of FIG. 8, the differential transmission of each of 16 data bits requires 32 wirings in the conventional differential transmission system, but 20 wirings and the shielded wire 30 are required.
4, the differential data transmission excellent in common mode noise elimination performance can be achieved with a small number of wirings.

The data transmission between a plurality of LSIs mounted on the printed wiring board has been described above.
The present invention can be applied to data transmission between a plurality of LSI chips constituting one multi-chip module and data transmission within an LSI chip. The number of data bits forming one word is not limited to 8 and 16 and is arbitrary.

[0029]

As described above, according to the present invention, by utilizing the complementary data lines, three differential transmissions of two data bits (four in the conventional differential transmission system) are performed.
With each wiring, the differential transmission of each of the four data bits is realized by each of the five wirings (8 in the conventional differential transmission method), so that the differential data transmission excellent in common mode noise elimination performance can be achieved. The effect that can be achieved with less wiring is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a data transmission system according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of each of one transmission unit and one reception unit in FIG.

FIG. 3 is a timing chart showing an example of voltage change of each of the three wirings in FIG.

FIG. 4 is a diagram showing a combination of voltages of three wires in FIG.

5 is a detailed circuit diagram showing a configuration example of a transmission unit in FIG.

FIG. 6 is a detailed circuit diagram showing a configuration example of a receiving unit in FIG.

7 is a detailed circuit diagram showing a modified example of the receiving unit of FIG.

FIG. 8 is a block diagram showing another configuration example of the data transmission system according to the present invention.

[Explanation of symbols]

1, 2 LSI (semiconductor integrated circuit) 3 transmission lines 4 Termination resistor string 11-14 Transmission unit 21-24, 21a receiving unit 31, 32 data lines 33 Complementary data line 41-43 Termination resistance 51-53 driver 61-64 comparator 301, 302 LSI (semiconductor integrated circuit) 303 transmission line 304 shielded wire 311 to 314 Transmission unit 321 to 324 receiving unit D0 to D15 data bits DL0 to DL15 data lines EN1, EN2 enable signal VH voltage that represents bit value 1 VL bit voltage representing 0 VTT termination voltage XD0 to XD15 data bits XDL0 to XDL12 Complementary data lines

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-54-96334 (JP, A) JP-A-51-68112 (JP, A) JP-A-63-244954 (JP, A) JP-A-11- 234348 (JP, A) Actually opened 63-153641 (JP, U) Actually opened 63-158044 (JP, U) Actually opened 63-165940 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 3/00 H04L 25/02

Claims (8)

(57) [Claims] 1. A data transmission system for differential transmission of each of first and second data bits, comprising: a transmission unit for transmitting the first and second data bits; And a receiving unit for receiving the second data bit, and a first data line, a second data line and a complementary data line, which are interposed between the transmitting unit and the receiving unit, respectively. The unit supplies a voltage representing the value of the first data bit to the first data line, a voltage representing the value of the second data bit to the second data line, and a voltage of the first data bit. The receiving unit has a function of supplying a voltage representing an inverted value of the value to the complementary data line, and the receiving unit compares the voltage of the first data line with the voltage of the complementary data line to obtain the first data. Bit of And the voltage of the first data line and the voltage of the second data line are different, by comparing the voltage of the first data line and the voltage of the second data line, When the voltage of the first data line and the voltage of the second data line are the same, the voltage of the complementary data line and the voltage of the second data line are compared to determine the second data, respectively. A data transmission system having a function of determining a value of a bit. 2. The data transmission system according to claim 1, wherein the transmitting unit and the receiving unit are units incorporated in separate semiconductor integrated circuits, and the first data line and the second data line are provided. The data transmission system characterized in that the data line and the complementary data line are wirings on a printed wiring board. 3. The data transmission system according to claim 1, wherein the first data line and the complementary data line are twisted around the second data line so as to form a twisted pair line. A data transmission system characterized in that 4. The data transmission system according to claim 3, wherein each of the third and the third units is interposed between the transmitting unit and the receiving unit and is arranged outside the twisted pair wire so as to sandwich the twisted pair wire. The transmission unit may further include a fourth data line, wherein the transmission unit supplies a voltage representing a value of a third data bit to the third data line and a voltage representing a value of a fourth data bit to the fourth data line. The receiving unit further has a function of supplying the voltage to the first data line and the voltage to the third data line when the voltage of the third data line is different from the voltage of the first data line. If the voltage of the first data line and the voltage of the third data line are the same, the voltage of the complementary data line and the voltage of the third data line are compared. By comparison with it The value of the third data bit is determined respectively, and when the voltage of the first data line and the voltage of the fourth data line are different, the voltage of the first data line and the fourth data line are determined. If the voltage of the first data line and the voltage of the fourth data line are the same, the voltage of the complementary data line and the voltage of the fourth data line are compared. The data transmission system further has a function of determining the value of the fourth data bit by comparison with 5. The data transmission system according to claim 4, wherein the transmission line formed by the first, second, third and fourth data lines and the complementary data line is also formed by five wires. A data transmission system, further comprising a shield wire inserted between an adjacent transmission path. 6. The data transmission system according to claim 1, wherein the transmission unit includes a first driver for supplying a voltage representing a value of the first data bit to the first data line, A second driver for supplying a voltage representing the value of a second data bit to the second data line, and a voltage representing an inverted value of the value of the first data bit to the complementary data line. And a third driver for the data transmission system. 7. The data transmission system according to claim 1, wherein the receiving unit determines the voltage of the first data line and the voltage of the complementary data line so as to determine the value of the first data bit. A second comparator for comparing the voltage of the second data line and the voltage of the complementary data line, a voltage of the first data line and the second comparator And a third comparator for comparing with the voltage of the data line, the third comparator when the voltage of the first data line and the voltage of the second data line are different, Data characterized in that when the voltage of the first data line and the voltage of the second data line are the same, the value of the second data bit is determined by the second comparator. Transmission Temu. 8. The data transmission system according to claim 1, wherein the receiving unit determines the voltage of the first data line and the voltage of the complementary data line so as to determine the value of the first data bit. For comparing the voltage of each of the first data line and the complementary data line with the voltage of the second data line so as to determine the value of the second data bit. And another comparator for performing the data transmission.