JPH11231984A - Data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of wirings for attaining differential transmissions of plural data bits. SOLUTION: Differential transmissions of two bits D0, D1 are attained by means of three wirings 31 to 33 between a transmitting unit 11 and a receiving unit 21. The wiring 31 is a 1st data line corresponding to the bit D0, the wiring 32 is a 2nd data line corresponding to the bit D1 and the wiring 33 is a complementary data line corresponding to the inverted value of the bit D0 value. The 1st data line 31 and the complementary data line 33 are used for differential transmission of the bit D0. When the values of the bits D0, D1 are mutually different, the 2nd data line 32 and the 1st data line 31 are used for differential transmission of the bit D1, and when the values of the bits D0, D1 are the same value, the 2nd data line 32 and the complementary data line 33 are used for differential transmission of the bit D1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system for realizing differential transmission of a plurality of data bits.

[0002]

2. Description of the Related Art With the processing of huge amounts of moving image data, high-speed data transmission between a plurality of semiconductor integrated circuits mounted on a printed wiring board has been demanded. D in response
In the field of RAM (dynamic random access memory),
Rambus specifications and SyncLink specifications are known as clock synchronous high-speed input / output interface specifications. The former is a specification developed by Rambus in the United States and adopts an open drain type interface. The latter is a US JEDEC (Joint Electron
This is a specification proposed by the Device Engineering Council, which is a SSTL (stub series terminated tranceive).
r logic).

[0003]

In the above-mentioned conventional input / output interface specifications, a plurality of data bits are each transmitted by one data line. Such a single transmission system has a problem that it is easily affected by external noise.

Conventionally, differential data transmission excellent in common mode noise removal performance has been known. This achieves transmission of one data bit using two data lines. However, when trying to realize differential transmission of each of a plurality of data bits between semiconductor integrated circuits on a printed wiring board, the number of wirings is two in comparison with the single transmission method.
As a result, the wiring area on the printed wiring board becomes large, and the number of pins of the package of the semiconductor integrated circuit increases.

An object of the present invention is to reduce the number of wirings for realizing differential transmission of each of a plurality of data bits.

[0006]

In order to achieve the above-mentioned object, the present invention realizes differential transmission of each of two data bits with three wirings. One of the three wirings is a first data line, the other is a second data line,
The other one is a complementary data line. A voltage representing the value of the first data bit is applied to the first data line, a voltage representing the value of the second data bit is applied to the second data line, and the value of the first data bit is applied to the complementary data line. Are supplied respectively. The first data line and the complementary data line
Used for differential transmission of the first data bit. When the value of the first data bit and the value of the second data bit are different from each other, the second data line and the first data line are connected to the first data bit and the second data bit, respectively. If the values are the same, the second data line and the complementary data line are used for differential transmission of the second data bit, respectively.

More specifically, a data transmission system according to the present invention transmits first and second data bits in a data transmission system for differential transmission of each of first and second data bits. And a receiving unit for receiving the first and second data bits, a first data line, a second data line, and complementary data interposed between the transmitting unit and the receiving unit, respectively. A configuration having a line and a line is adopted. In addition, the transmission unit transmits the voltage representing the value of the first data bit to the first data line, the voltage representing the value of the second data bit to the second data line, and the value of the first data bit. It has a function of supplying a voltage representing an inverted value to each complementary data line. The receiving unit determines the value of the first data bit by comparing the voltage of the first data line with the voltage of the complementary data line, and determines the voltage of the first data line and the voltage of the second data line. Are different from each other, the voltage of the first data line is compared with the voltage of the second data line. If the voltage of the first data line and the voltage of the second data line are the same, the voltages are complementary. It has a function of determining the value of the second data bit by comparing the voltage of the data line with the voltage of the second data line.

[0008]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a configuration example of a data transmission system according to the present invention. 1 includes two semiconductor integrated circuits mounted on a printed wiring board, for example, two large scale integrated circuits (LSIs) 1 and 2.
Are connected by a transmission path 3. The LSI 1 transmits eight data bits D0 to D7 forming one word to the transmission path 3, and the LSI 2 receives the 8-bit word transmitted via the transmission path 3. The twelve wires constituting the transmission path 3 are connected to a terminal voltage VT
Each is pulled up to T.

The LSI 1 incorporates four transmission units (T0, T1, T2, T3) 11, 12, 13, and 14 that perform transmission operations when the enable signal EN1 is activated. The transmission unit 11 transmits the bits D0 and D
1 is a unit for transmitting a voltage representing the value of the bit D0 to the data line DL0, a voltage representing the value of the bit D1 to the data line DL1, and a voltage representing the inverted value of the value of the bit D0 as complementary data. These are supplied to the line XDL0. The other three transmission units 12, 13, and 14 are units having the same function. DL2 to DL7 are data lines, and XDL2, XDL4, and XDL6 are complementary data lines. The power supply voltages VDDQ and VS generated inside the LSI 1 from the external power supply voltages VDD and VSS.
The SQ is supplied to the output stage of each of the four transmission units 11 to 14.

The data line DL0 and the complementary data line XDL0 are wirings that are twisted twice around the data line DL1 so as to form a twisted pair line. The twist is provided at each of one-third and two-thirds of the entire length of the data line DL0 and the complementary data line XDL0. The data line DL2 and the complementary data line XDL2 are
This is a wire that has been twisted once around the data line DL3 so as to form a twisted pair wire. The twist is provided at one half of the entire length of the data line DL2 and the complementary data line XDL2. This allows
The effects of the data line DL0 and the complementary data line XDL0 are equally applied to the data line DL2 and the complementary data line XDL2, and conversely, the effects of the data line DL2 and the complementary data line XDL2 are equally applied to the data line DL0 and the complementary data line XDL0. Can be The data line DL3 is constituted by the data line DL2 and the complementary data line XDL2, and the data line DL1 is constituted by the data line DDL.
Shielded by L0 and the complementary data line XDL0, respectively. Similarly, data line DL4 and complementary data line XDL4
Are twisted twice around the data line DL5, and the twisted pair of the data line DL6 and the complementary data line XDL6 are given one twist around the data line DL7. Note that the number of twists is not limited to the above example.

The LSI 2 includes the four transmission units 1 described above.
Four receiving units (R0, R1, R2, R3) 21, 22, 23, 2 corresponding to each of 1, 12, 13, 14
4 built-in. These four receiving units 21 and 2
Reference numeral 4 denotes a signal receiving operation when the enable signal EN2 is activated. The receiving unit 21 is a unit for receiving the bits D0 and D1, and determines the value of the bit D0 by comparing the voltage of the data line DL0 with the voltage of the complementary data line XDL0.
When the voltage of the data line DL1 is different from the voltage of the data line DL1, the voltage of the data line DL0 and the voltage of the data line DL1 are compared. The value of the bit D1 is determined by comparing the voltage of the data line XDL0 with the voltage of the data line DL1. The other three receiving units 2
2, 23 and 24 are units having the same function.
It should be noted that XD0 to XD7 in the figure indicate respective inverted bits of the bits D0 to D7. The output terminal of the transmission unit 12 and the input terminal of the reception unit 22 are connected to the data line DL.
2 and the complementary data line XDL2 are arranged in reverse to each other in accordance with the odd number of twists. The same applies to the relationship between the transmitting unit 14 and the receiving unit 24.

FIG. 2 shows one transmission unit 11 shown in FIG.
2 shows a detailed configuration of each of the receiving unit 21 and the one receiving unit 21. However, the data line DL0 and the complementary data line XDL
Illustration of the twist of 0 is omitted.

Referring to FIG. 2, the transmission unit 11 has first, second and third drivers 51, 52 and 53, each of which performs a transmission operation when the enable signal EN1 is activated. The first driver 51 is a driver for supplying a voltage representing the value of the bit D0 to the data line (DL0) 31. The second driver 52 is a driver for supplying a voltage representing the value of the bit D1 to the data line (DL1) 32. The third driver 53 is a driver for supplying a voltage representing an inverted value of the value of the bit D0 to the complementary data line (XDL0) 33.

The data line DL0, the data line DL1, and the complementary data line XDL0 each have a terminating resistor 4 having a resistance value R.
It is pulled up to the termination voltage VTT via 1, 42, 43.

The receiving unit 21 includes first, second, and third comparators 61, 62, and 63 that perform a receiving operation when the enable signal EN2 is activated.
The first comparator 61 compares the voltage of the data line DL0 and the voltage of the complementary data line XDL0 with the second comparator 62
Represents the voltage of the data line DL1 and the voltage of the complementary data line XDL0, and the third comparator 63 compares the voltage of the data line DL0 with the voltage of the data line DL1. The value of bit D0 is determined only by first comparator 61. The value of bit D1 is
When the voltage of the data line DL1 is different from the voltage of the data line DL1, the third
When the voltage of the data line DL0 and the voltage of the data line DL1 are the same, the second comparator 62 makes a determination.

FIG. 3 shows three wirings DL0 and XD in FIG.
An example of each voltage change of L0 and DL1 is shown. In the period 1, since the enable signal EN1 is set to the inactivation level “L”, the first, second, and third drivers 51, 52, and 53 hold their outputs in a high impedance state. As a result, three wirings DL0, X
The voltages of DL0 and DL1 are both equal to the termination voltage VTT. In the periods 2 to 7, the setting of the enable signal EN1 is changed to the activation level “H”, so that the first and second
Each of the third drivers 51, 52, and 53 performs a transmission operation according to the data bits D0 and D1. Period 2
In this case, D0 = 1 and D1 = 1. Therefore, in the period 2, the voltage of each of the data lines DL0 and DL1 is changed to the high-level voltage VH representing the bit value 1, and the complementary data line XD
The voltage of L0 becomes the low-level voltage VL representing the bit value 0. Here, the voltage VH is a voltage higher by ΔV than the terminal voltage VTT, and the voltage VL is a voltage lower by ΔV than the terminal voltage VTT. In period 3, D0 = 0 and D1 = 0
It is. Therefore, in the period 3, the data lines DL0 and D0
Each voltage of L1 becomes a low-level voltage VL representing the bit value 0, and the voltage of the complementary data line XDL0 becomes a high-level voltage VH representing the bit value 1. In period 4, D0 = 0 and D1 = 1, and in period 5, D0 = 1 and D1 = 0. The state in period 6 is the same as period 3, and the state in period 7 is the same as period 2. As described above, the three wirings D
The voltage amplitude of each of L0, XDL0 and DL1 is 2ΔV. For example, VDD = + 3.3V, VSS =
When 0V and VTT = + 1.5V, ΔV = 0.4V (based on the output value of the transmitting unit 11). By employing such a small-amplitude interface, high-speed data transmission becomes possible.

FIG. 4 shows three lines DL0 and XD in FIG.
The combination of the voltages of L0 and DL1 is shown.

Hereinafter, the internal configuration of each of the transmitting unit 11 and the receiving unit 21 in FIG. 2 will be briefly described.

FIG. 5 shows a configuration example of the transmission unit 11 in FIG. First for driving data line DL0
Driver 51 includes a NAND gate 101 and a PMOS
The driver includes a transistor 102, an inverter 103, a NOR gate 104, and an NMOS transistor 105, and receives a data bit D0 and an enable signal EN1 as inputs. The second driver 52 for driving the data line DL1 includes a NAND gate 111
, A PMOS transistor 112 and an inverter 113
, NOR gate 114 and NMOS transistor 11
5 is a driver that receives the data bit D1 and the enable signal EN1 as inputs. The third driver 53 for driving the complementary data line XDL0 includes an inverter 121, a NAND gate 122, a PMOS
The driver includes a transistor 123, an inverter 124, a NOR gate 125, and an NMOS transistor 126, and receives a data bit D0 and an enable signal EN1 as inputs.

FIG. 6 shows an example of the configuration of the receiving unit 21 in FIG. The first comparator 61 for comparing the voltage of the data line DL0 with the voltage of the complementary data line XDL0 includes two PMOS transistors 201 and 202.
And three NMOS transistors 203, 204, 20
5 is comprised. The second comparator 62 for comparing the voltage of the data line DL1 with the voltage of the complementary data line XDL0 includes two PMOS transistors 211 and 211.
12 and three NMOS transistors 213, 214,
215. The third comparator 63 for comparing the voltage of the data line DL0 with the voltage of the data line DL1 includes two PMOS transistors 221 and 22.
2 and three NMOS transistors 223, 224, 2
25. Each of the first, second, and third comparators 61, 62, and 63 is a circuit having excellent common mode noise removal performance. The output of the first comparator 61 is a data bit XD0 (bit D0
). Second comparator 62
And the output of the third comparator 63 are wired OR-connected so as to determine the data bit XD1 (the inverted bit of the bit D1). Thus, when the voltage of the data line DL0 is different from the voltage of the data line DL1, the value of the bit XD1 is determined by the third comparator 63. When the voltage of the data line DL0 is equal to the voltage of the data line DL1, the value of the bit XD1 is determined by the second comparator 62.

FIG. 7 shows a modification of the receiving unit 21 of FIG. The receiving unit 21a of FIG. 7 includes the second and third comparators 62,
63 is replaced with one (fourth) comparator 64. The fourth comparator 64 has two PMOs.
It comprises S transistors 231, 232 and five NMOS transistors 233, 234, 235, 236, 237, and has a data line DL0 and a complementary data line XD.
The value of bit XD1 is determined by comparing each voltage of L0 with the voltage of data line DL1. According to the configuration of FIG. 7, the bit value determination can be performed with a smaller configuration than the case of FIG.

FIG. 8 shows another configuration example of the data transmission system according to the present invention. The system shown in FIG. 8 includes two LSIs 301 and 302 mounted on a printed wiring board.
Are connected by a transmission path 303. LSI
Reference numeral 301 denotes 16 data bits D0 constituting one word.
To D15 to the transmission path 303, and the LSI 302 receives the 16-bit word transmitted through the transmission path 303.

The LSI 301 has four transmission units (T
10, T11, T12, T13) 311, 312, 31
3,314 are built-in. The transmission unit 311 is a unit for transmitting the bits D0, D1, D2, and D3, and transmits a voltage representing the value of the bit D0 to the data line DL.
0, and a voltage representing the value of bit D1 to data line DL1.
The voltage representing the value of bit D2 is supplied to data line DL2, the voltage representing the value of bit D3 is supplied to data line DL3, and the voltage representing the inverted value of bit D0 is supplied to complementary data line XDL0. The other three transmission units 31
2, 313, 314 are units having the same function, DL4 to DL15 are data lines, XDL4, XDL
8 and XDL12 are complementary data lines.

The data line DL0 and the complementary data line XDL0 are wires that are twisted twice around the data line DL2 so as to form a twisted pair line. Furthermore,
The data line D is placed outside the twisted pair line so as to sandwich it.
L1 and DL3 are arranged. These five wirings constitute one sub-transmission line. Thus, the influence of the data line DL0 and the complementary data line XDL0 is reduced by the data line DDL.
L1 is equally applied, and conversely, the influence of data line DL1 is equally applied to data line DL0 and complementary data line XDL0. The same applies to the relationship between the data line DL3, the data line DL0, and the complementary data line XDL0. The data line DL2 is shielded by the data line DL0 and the complementary data line XDL0. Therefore, mutual interference between the data lines DL2 and DL1 and between the data lines DL2 and DL3 are prevented. The other fifteen wirings constitute the same sub-transmission line with five wirings as one set. In addition, the shield line 304 is inserted between the sub-transmission paths adjacent to each other.

The LSI 302 has four receiving units (R10, R11, R12, R13) 3 corresponding to the four transmitting units 311, 312, 313, and 314, respectively.
21, 322, 323 and 324 are built-in. The receiving unit 321 is a unit for receiving the bits D0, D1, D2 and D3, and by comparing the voltage of the data line DL0 with the voltage of the complementary data line XDL0,
0 and determine the voltage of the data line DL0 and the data line DL.
1 is different from the voltage of the data line DL0 and the voltage of the data line DL1, and if the voltage of the data line DL0 and the voltage of the data line DL1 are the same, the voltage of the complementary data line XDL0 is The value of bit D1 is determined by comparing the voltage of data line DL1 with the voltage of data line DL1, and when the voltage of data line DL0 is different from the voltage of data line DL2, the voltage of data line DL0 is compared with the voltage of data line DL2. Therefore, when the voltage of the data line DL0 and the voltage of the data line DL2 are the same, the value of the bit D2 is determined by comparing the voltage of the complementary data line XDL0 and the voltage of the data line DL2, and Is different from the voltage of the data line DL3, the voltage of the data line DL0 is compared with the voltage of the data line DL3.
When the voltage of L0 is equal to the voltage of data line DL3, the value of bit D3 is determined by comparing the voltage of complementary data line XDL0 with the voltage of data line DL3. The other three receiving units 322, 323, 3
24 is a unit having a similar function. It should be noted that XD0 to XD15 in the figure indicate respective inverted bits of bits D0 to D15.

According to the configuration shown in FIG. 8, the differential transmission of each of the 16 data bits requires 20 lines and the shield line 30 instead of 32 lines in the conventional differential transmission system.
4, the effect of achieving differential data transmission excellent in common mode noise elimination performance with a small number of wirings can be obtained.

The data transmission between a plurality of LSIs mounted on a printed wiring board has been described above.
The present invention can also be applied to data transmission between a plurality of LSI chips constituting one multi-chip module and data transmission within an LSI chip. The number of data bits constituting one word is not limited to 8, 16 and is arbitrary.

[0029]

As described above, according to the present invention, three differential transmissions of each of two data bits are performed (four in the conventional differential transmission system) by utilizing complementary data lines.
The differential transmission of each of the four data bits is realized by five lines (eight lines in the conventional differential transmission system) with the above wiring, so that the differential data transmission excellent in the common mode noise elimination performance is realized. The effect that can be achieved with a small number of wirings can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a data transmission system according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of each of one transmission unit and one reception unit in FIG. 1;

FIG. 3 is a timing chart showing an example of a voltage change of each of three wires in FIG. 2;

FIG. 4 is a diagram showing combinations of voltages of three wires in FIG. 2;

FIG. 5 is a detailed circuit diagram illustrating a configuration example of a transmission unit in FIG. 2;

FIG. 6 is a detailed circuit diagram illustrating a configuration example of a receiving unit in FIG. 2;

FIG. 7 is a detailed circuit diagram showing a modification of the receiving unit of FIG. 6;

FIG. 8 is a block diagram showing another configuration example of the data transmission system according to the present invention.

[Explanation of symbols]

 1, 2 LSI (semiconductor integrated circuit) 3 transmission line 4 terminating resistor string 11 to 14 transmitting unit 21 to 24, 21a receiving unit 31, 32 data line 33 complementary data line 41 to 43 terminating resistor 51 to 53 driver 61 to 64 comparator 301, 302 LSI (semiconductor integrated circuit) 303 transmission line 304 shield line 311 to 314 transmission unit 321 to 324 reception unit D0 to D15 data bit DL0 to DL15 data line EN1, EN2 enable signal VH voltage representing bit value 1 VL bit value Voltage representing 0 VTT Termination voltage XD0 to XD15 Data bit XDL0 to XDL12 Complementary data line

Claims (8)

[Claims] 1. A data transmission system for differential transmission of each of first and second data bits, wherein: a transmission unit for transmitting the first and second data bits; and And a receiving unit for receiving a second data bit; and a first data line, a second data line, and a complementary data line interposed between the transmitting unit and the receiving unit, respectively. A unit for applying a voltage representing the value of the first data bit to the first data line, applying a voltage representing the value of the second data bit to the second data line, Having a function of supplying a voltage representing an inverted value of the value to each of the complementary data lines, wherein the receiving unit compares the first data line voltage with the complementary data line voltage by comparing the voltage of the first data line with the voltage of the complementary data line. Bit of And when the voltage of the first data line and the voltage of the second data line are different, by comparing the voltage of the first data line with the voltage of the second data line, When the voltage of the first data line and the voltage of the second data line are the same, the voltage of the complementary data line and the voltage of the second data line are compared to each other to obtain the second data line. A data transmission system having a function of determining a bit value. 2. The data transmission system according to claim 1, wherein the transmission unit and the reception unit are units built in separate semiconductor integrated circuits, respectively, and the first data line and the second data line are connected to each other. A data transmission system, wherein each of the data line and the complementary data line is a wiring on a printed wiring board. 3. The data transmission system according to claim 1, wherein the first data line and the complementary data line are twisted about the second data line so as to form a twisted pair line. A data transmission system, characterized in that: 4. The data transmission system according to claim 3, wherein said third and said third transmission units are interposed between said transmission unit and said reception unit, and are disposed outside said twisted pair line so as to sandwich said twisted pair line. The transmitting unit further includes a fourth data line, wherein the transmitting unit applies a voltage representing a value of a third data bit to the third data line, and supplies a voltage representing a value of a fourth data bit to the fourth data line. The receiving unit further has a function of supplying the voltage of the first data line to the voltage of the third data line when the voltage of the first data line is different from the voltage of the third data line. When the voltage of the first data line is equal to the voltage of the third data line, the voltage of the complementary data line is equal to the voltage of the third data line. By comparison with it The value of the third data bit is determined, and if the voltage of the first data line is different from the voltage of the fourth data line, the voltage of the first data line is When the voltage of the first data line is equal to the voltage of the fourth data line, the voltage of the complementary data line is equal to the voltage of the fourth data line. A data transmission system further comprising a function of judging the value of the fourth data bit by comparing with the first data bit. 5. The data transmission system according to claim 4, wherein the transmission line includes the first, second, third, and fourth data lines and the complementary data line, and similarly includes five wires. A data transmission system, further comprising a shield wire inserted between adjacent transmission lines. 6. The data transmission system according to claim 1, wherein the transmission unit supplies a voltage representing a value of the first data bit to the first data line; A second driver for supplying a voltage representing a value of a second data bit to the second data line; and supplying a voltage representing an inverted value of the value of the first data bit to the complementary data line. And a third driver for the data transmission system. 7. The data transmission system according to claim 1, wherein the receiving unit determines a value of the first data bit and a voltage of the first data line and a voltage of the complementary data line. A first comparator for comparing a voltage of the second data line with a voltage of the complementary data line; a first comparator for comparing the voltage of the second data line with the voltage of the complementary data line; A third comparator for comparing the voltage of the first data line with the voltage of the second data line, when the voltage of the first data line is different from the voltage of the second data line, When the voltage of the first data line and the voltage of the second data line are the same, the value of the second data bit is determined by the second comparator, respectively. Transmission system Temu. 8. The data transmission system according to claim 1, wherein the receiving unit determines a value of the first data bit and a voltage of the first data line and a voltage of the complementary data line so as to determine a value of the first data bit. And comparing the voltage of each of the first data line and the complementary data line with the voltage of the second data line so as to determine the value of the second data bit. A data transmission system having another comparator for performing the operation.