JPH11234159A - Radio receiver and radio transmitter-receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a pull-in time of frequency correction (synchronization) by an AFC prolonged due to an A/D conversion part. SOLUTION: Based on a frequency error detected by a frequency error detection means 4, a control means 5 performs AFC feedback control to a reference signal generation means 1, as in the conventional case. In this method, however, a frequency synthesis means 40 generates clock signals by performing frequency synthesis with the frequency of reference signals generated from the reference signal generation means 1 as a reference and supplies them to an A/D conversion means 30. Thus, the clock signals supplied to the A/D conversion means 30 are synchronized with received waves and thus, the A/D conversion means 30 does not adversely affect the AFC feedback control and the pull-in time of the frequency correction (synchronization) by the AFC is made shorter than before.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio receiver and a radio transceiver, and more particularly, to a CDMA (Code Division Multiplexer).
Like a mobile communication system to which the tiple access method is applied, a radio receiver and a radio transceiver that perform frequency conversion and modulation / demodulation based on a local oscillation signal whose oscillation frequency matches the radio frequency of an incoming reception wave with high accuracy. About the machine.

The CDMA system provides higher transmission quality against interference, interference and fluctuations in transmission characteristics of a wireless transmission path than other multiple access systems, and is rich in secrecy. Various developments and researches are being conducted in the direction applied to the system.

[0003]

2. Description of the Related Art FIG. 13 is a diagram showing a configuration example of a conventional radio receiver to which the CDMA system is applied.

In the figure, a received wave is a low noise amplifier (LNA) 1
01 and a band pass filter (BPF) 102 to the frequency converter 103. The frequency conversion unit 103 includes a multiplier, and converts a received wave into an intermediate frequency signal using a local oscillation signal sent from a local oscillation unit 112 described later. The output of the frequency conversion unit 103 is a band-pass filter (BP
F) The signal is input to the demodulation unit 105 via 104. Demodulation section 105 includes multipliers 105a and 105b, 90 ° phase shifter 1
05c, an oscillator 105d, and performs phase detection.
Outputs I-channel and Q-channel baseband signals. The A / D converter 106 converts the baseband signal from analog to digital. A / D converter 106
Is composed of A / D converters 106a and 106b and a clock oscillator 106c. The phase detector 107 obtains the amplitudes Imt and Qmt of the I channel and the Q channel corresponding to the time series t (here, for simplicity, it is assumed that the integer values are normalized by the symbol period), and The phase θt of the received wave is calculated based on the equation (1).

[0005]

.Theta.t = arctan (Qmt / Imt) (1) The frequency error detector 108 calculates the frequency error by differentiating the phase .theta.t twice with respect to the time series t. The frequency error is a difference between the sum of the frequency of the local oscillation signal and the frequency of the intermediate frequency signal and the frequency of the received wave.

[0006] The calculation of such a frequency error is performed based on information that is known to be received based on the format of the received wave among the components of the received wave described above. The information includes, for example, a preamble, a unique word, and a continuous symbol (bit) string having the same value used for establishing synchronization on the receiving side.

The control unit 109 determines whether or not the calculated frequency error is within a predetermined allowable range. If not, the control unit 109 outputs a digital signal indicating a value proportional to the frequency error. Output. D / A converter 110 converts the value indicated by the digital signal into control voltage Vco.
A control signal indicated as nt is generated and a reference signal generator 11 is generated.
Send to 1. The reference signal generator 111 is constituted by a voltage-controlled temperature-compensated crystal oscillator (VCTCXO), and generates a reference signal whose oscillation frequency is varied in a direction in which the above-described frequency error is compressed, according to the control signal.

[0008] The local oscillating unit 112 includes the reference signal generator 11.
Frequency synthesis is performed based on the reference signal (frequency fvctcxo) sent from 1, a local oscillation signal (local oscillation signal) is generated and sent to the frequency conversion unit 103. The local oscillator 112 includes a frequency divider 112a having a frequency division ratio of 1 / M and a frequency divider 1 having a frequency division ratio of 1 / N.
12b, phase comparator 112c, loop filter 112
d, comprising a voltage controlled oscillator (VCO) 112e, and outputs a local oscillation signal having a frequency fms represented by the following equation (2) to the frequency conversion unit 103.

[0009]

Fms = fvctcxo · (N / M) (2) Note that the frequency converter 103, the bandpass filter 104,
Demodulator 105, A / D converter 106, phase detector 10
7. AFC composed of a frequency error detection unit 108, a D / A converter 110, a reference signal generator 111, and a local oscillation unit 112
(Auto Frequency Control) The feedback loop repeats the frequency correction of the local oscillation signal as described above.If the frequency error falls within a predetermined allowable range, the control unit 109 stops the frequency correction at that time and cancels the frequency correction. Maintain the correction state. That is, the control voltage Vcont is maintained.

[0010] Thereby, the radio receiver as the mobile terminal can be synchronized with the base station as the transmitting side, and accurate data demodulation can be performed. Also, when the mobile terminal is a wireless transceiver, the transmitting unit synchronizes with the receiving unit as described above, so that the transmission signal transmitted from the mobile terminal to the base station is also a signal that is accurately synchronized. Becomes

[0011]

In the above-mentioned conventional radio receiver, accurate data demodulation is realized by correcting the frequency of a local oscillation signal by an AFC feedback loop.
However, the clock signal output from the clock oscillator 106c used by the A / D converter 106 for sampling is not synchronized with the received wave. Therefore, AFC
There is a problem that it takes time to perform frequency correction (synchronization) due to the above. This seems likely to be solved by sharing the reference signal generator 111 instead of the clock oscillator 106c, but its use has the following obstacles.

That is, for example, while the frequency of the reference signal of the reference signal generator 111 is 12 MHz, the frequency of the clock signal required by the A / D converter 106 is 32.
In the case of 768 MHz, even if the frequency is divided, they do not coincide with each other and cannot be shared.

In this case, it is sufficient that the frequency of the reference signal of the reference signal generator 111 is 32.768 MHz. At present, however, a VCTCXO which is small enough to be mounted on a mobile terminal and has desired stability and accuracy. Does not exist. That is,
The frequency of the clock signal 32.768 MHz required by the A / D converter 106 is higher than the frequency of the clock signal required by the normal A / D converter, and can be mounted on mobile terminals at present. The frequency of a VCTCXO is limited to 20 MHz.

In addition, in order to stably perform the subsequent processing on the digital signal converted by the A / D converter 106, it is desirable to set the duty of the clock signal to 50%. To achieve this, 32.768 MHz
Therefore, a clock signal of 65.536 MHz, which is twice as large, is required, and VCTCXO is required to have a higher frequency.

The present invention has been made in view of the above points, and has been made longer by the A / D converter.
It is an object of the present invention to provide a wireless receiver and a wireless transceiver that reduce the time required for frequency correction (synchronization) by FC.

[0016]

According to the present invention, in order to achieve the above object, as shown in FIG. 1, reference signal generating means 1 for generating a reference signal whose frequency can be varied by an external control signal; A local oscillation means 10 for performing frequency synthesis based on the frequency of the reference signal generated from the reference signal generation means 1 to generate a local oscillation signal, and a reception wave taking a plurality of signal points having different phases in a signal space, Frequency conversion means 2 for performing frequency conversion of a received wave by a local oscillation signal given from the local oscillation means and generating an intermediate frequency signal
Demodulation means 20 for digitally demodulating the intermediate frequency signal generated by the frequency conversion means 2 and outputting in-phase and quadrature-component baseband signals; analog-to-digital conversion of the in-phase and quadrature-component baseband signals; A / D conversion means 30 for performing each conversion to each other and outputting each digital signal, and a phase detection means 3 for detecting a phase of a signal point based on each digital signal output from the A / D conversion means 30. , By time-differentiating twice the phase of the signal point output along the time series from the phase detection means 3, the sum of the frequency of the local oscillation signal and the frequency of the intermediate frequency signal and the frequency of the reception wave are obtained. Frequency error detecting means 4 for obtaining a frequency error as a difference, and changing the frequency of the reference signal in a direction in which the frequency error obtained by the frequency error detecting means 4 is compressed. A control unit 5 for providing a control signal to the reference signal generation unit 1 and a frequency signal are synthesized based on the frequency of the reference signal generated from the reference signal generation unit 1 to generate a clock signal and supplied to the A / D conversion unit 30 And a frequency synthesizing unit 40 that performs the operation.

In the above configuration, the control means 5 is controlled based on the frequency error detected by the frequency error detection means 4.
Performs AFC feedback control on the reference signal generating means 1. This is the same operation as the conventional one.

In the present invention, the frequency synthesizing means 40 further comprises:
Generating a clock signal by performing frequency synthesis with reference to the frequency of the reference signal generated from the reference signal generating means 1;
It is supplied to A / D conversion means 30. Therefore, the clock signal supplied to the A / D converter 30 is synchronized with the received wave, so that the A / D converter 30 does not adversely affect the AFC feedback control, and the AFC
, The pull-in time of the frequency correction (synchronization) can be shortened as compared with the related art.

The frequency synthesizing means 40 is provided with a PLL (Phase
The use of a Locked Loop) circuit solves the problem that the frequencies do not match even if the frequency is divided, and also makes it possible to use the existing VCTCXO that can be mounted on a mobile terminal.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. A first embodiment will be described.

First, a principle configuration according to the first embodiment will be described with reference to FIG. In the first embodiment, reference signal generating means 1 for generating a reference signal whose frequency can be varied by an external control signal, and frequency synthesis based on the frequency of the reference signal generated from the reference signal generating means 1 are used as a reference. Local oscillation means 10 for generating a local oscillation signal and receiving a reception wave taking a plurality of signal points having different phases in a signal space, and performing frequency conversion of the reception wave by the local oscillation signal given from the local oscillation means. A frequency converting means 2 for generating an intermediate frequency signal, a demodulating means 20 for digitally demodulating the intermediate frequency signal generated by the frequency converting means 2 and outputting a baseband signal of an in-phase component and a quadrature component; A / D conversion means 30 for performing analog-to-digital conversion on the baseband signal of each component and outputting each digital signal; Phase detecting means 3 for detecting the phase of a signal point based on each digital signal output from the converting means 30, and twice temporally differentiating the phase of the signal point output from the phase detecting means 3 in time series. Thereby, a frequency error detecting means 4 for obtaining a frequency error which is a difference between a sum of the frequency of the local oscillation signal and the frequency of the intermediate frequency signal and a frequency of the received wave, and a frequency obtained by the frequency error detecting means 4 Control means 5 for providing a control signal for changing the frequency of the reference signal to the reference signal generation means 1 in a direction in which the error is compressed;
A clock signal is generated by performing frequency synthesis with reference to the frequency of the reference signal generated from the A / D converter 30.
And a frequency synthesizing means 40 for supplying the signal to the frequency synthesizer 40.

In the above arrangement, the control means 5 is controlled based on the frequency error detected by the frequency error detection means 4.
Performs AFC feedback control on the reference signal generating means 1. This is the same operation as the conventional one.

In the present invention, the frequency synthesizing means 40 further comprises:
Generating a clock signal by performing frequency synthesis with reference to the frequency of the reference signal generated from the reference signal generating means 1;
It is supplied to A / D conversion means 30. Therefore, the clock signal supplied to the A / D converter 30 is synchronized with the received wave, so that the A / D converter 30 does not adversely affect the AFC feedback control, and the AFC
, The time required for frequency correction (synchronization) is shortened as compared with the conventional case.

If a PLL circuit is used for the frequency synthesizing means 40, the problem that the frequencies do not match even when the frequency is divided can be solved.
Can also be used.

Next, the first embodiment will be described in detail. In the first embodiment described below, FIG.
The reference signal generating means 1 shown in FIG. 1 corresponds to the reference signal generating section 1a. Similarly, the local oscillating means 10
The frequency conversion unit 2 includes a demodulation unit 20
Is a demodulator 20a, A / D converter 30 is an A / D converter 30a, phase detector 3 is a phase detector 3a, frequency error detector 4 is a frequency error detector 4a, and control unit 5
Is the control unit 5a, and the frequency synthesis unit 40 is the frequency synthesis unit 4
0a.

FIG. 2 shows a CDMA according to the first embodiment.
It is a block diagram which shows the structure of the radio receiver to which the system was adapted. In FIG. 2, the received wave is transmitted through a low-noise amplifier (LNA) 7 and a band-pass filter (BPF) 8 to a frequency conversion unit 2.
sent to a. The frequency conversion unit 2a includes a multiplier, and converts a received wave into an intermediate frequency signal using a local oscillation signal sent from the local oscillation unit 10a. The output of the frequency converter 2a is passed through a band-pass filter (BPF) 9 to a demodulator 20.
is input to a. The demodulation unit 20a includes multipliers 21, 22,
It comprises a 90 ° phase shifter 23 and an oscillator 24, performs phase detection, and outputs I-channel and Q-channel baseband signals. This baseband signal is converted from analog to digital by the A / D converter 30a. A / D converter 3
0a is composed of A / D converters 31 and 32, and a clock signal is sent from the frequency synthesizer 40a to the A / D converters 31 and 32. The phase detection unit 3a calculates the I corresponding to the time series t.
The amplitudes Imt and Qmt of the channel and the Q channel are obtained, and the phase θt of the received wave is calculated from these, and is sent to a subsequent signal processing unit (not shown).

The frequency error detector 4a calculates the frequency error by branching the phase θt and differentiating it twice with respect to the time series t. The frequency error is a difference between the sum of the frequency of the local oscillation signal and the frequency of the intermediate frequency signal and the frequency of the received wave.

The calculation of such a frequency error is performed on the basis of information, of the components of the received wave, which is known to be received based on the format of the received wave. The information includes, for example, a preamble, a unique word, and a continuous symbol (bit) string having the same value used for establishing synchronization on the receiving side.

The controller 5a determines whether the calculated frequency error is within a predetermined allowable range, and if not, outputs a digital signal indicating a value proportional to the frequency error. Output. D / A converter 6
Generates a control signal indicating the value indicated by the digital signal as the control voltage Vcont, and sends the control signal to the reference signal generator 1a. The reference signal generation unit 1a is configured by a voltage-controlled temperature-compensated crystal oscillator (VCTCXO), and generates a reference signal whose oscillation frequency is varied in a direction in which the above-described frequency error is compressed according to the control signal.

The local oscillation section 10a includes a reference signal generation section 1a
Performs frequency synthesis based on the reference signal (frequency fvctcxo) sent from the
Send to The local oscillator 10a includes a frequency divider 1 having a frequency division ratio of 1 / M.
1, a frequency divider 12 having a frequency division ratio of 1 / N, a phase comparator 13, a loop filter 14, and a voltage controlled oscillator (VCO) 15 for converting a local oscillation signal having a frequency fvctcxo · (N / M) into a frequency converter 103 Output to

The frequency converter 2a, bandpass filter 9, demodulator 20a, A / D converter 30a, phase detector 3a, frequency error detector 4a, D / A converter 6, reference signal generator 1a, The above-described frequency correction of the local oscillation signal is repeatedly performed by the AFC feedback loop including the local oscillation unit 10a. If the frequency error falls within the predetermined allowable range, the control unit 5a performs the frequency correction at that time. Cancel and maintain the corrected state. That is, the control voltage V
Maintain cont.

Further, the frequency synthesizer 40a performs frequency synthesis based on the reference signal (frequency fvctcxo) sent from the reference signal generator 1a, generates a clock signal, and generates an A / A signal.
It is sent to the D conversion unit 30a. The frequency synthesizer 40a includes a frequency divider 41 having a frequency division ratio of 1 / M ', a frequency divider having a frequency division ratio of 1 / N',
It comprises a phase comparator 43, a loop filter 44, and a voltage controlled oscillator (VCO) 45, and has a frequency fvctcxo · (N ′ /
M ′) is output to the A / D converter 30a.

As a result, the clock signal is synchronized with the received wave, the A / D converter 30a does not adversely affect the AFC feedback control, and the time for pulling in the frequency correction (synchronization) by the AFC is reduced as compared with the conventional case. .

Next, a second embodiment will be described. FIG.
FIG. 9 is a block diagram illustrating a configuration of a wireless receiver according to a second embodiment. Since the second embodiment has basically the same configuration as the first embodiment, the same components are denoted by the same reference numerals, and the description thereof will be omitted. Only different portions will be described below. explain.

In the second embodiment, the changeover switch (S
W) 51 is provided in front of the low-noise amplifier 7 so that a reception wave is input to one input terminal of the changeover switch 51. Normally, the changeover switch 51 outputs a received wave to the low noise amplifier 7. Further, the storage device 53 is connected to the control unit 5a.

At the time of manufacturing this radio receiver, a reference signal generator 52 is connected to the other input terminal of the changeover switch 51, and the changeover switch 51 is switched to lower the output signal from the received wave reference signal generator 52. The signal is sent to the noise amplifier 7, and the AFC feedback control operation is performed for the wireless receiver. The reference signal generator 52 is a device that generates a standard modulation signal whose frequency is highly stable (for example, 0.01 ppm).

When the frequency error detected by the frequency error detector 4a falls within a predetermined range as a result of the AFC feedback control operation in the radio receiver, the controller 5a sends the signal to the D / A converter 6 at that time. The output digital signal is stored in the storage device 53 as an initial value. The stored initial value indicates a digital value representing a voltage value (control voltage Vcont) proportional to the frequency error to be sent to the reference signal generator 1a.

That is, the value of the power supply voltage, the magnitude of the output load of the reference signal generator 1a, the capacity of the trimmer capacitor added for adjusting the oscillation frequency, the value of the output resistance of the D / A converter 6, and the VCTCXO
The frequency of the reference signal generated by the reference signal generation unit 1a is different for each wireless receiver. For this reason, depending on the radio receiver, it may take several tens of seconds for the frequency error to fall within the predetermined range.

Therefore, at the time of manufacture, the AFC feedback control operation is performed in advance using the reference signal generator 52 for each radio reception. As a result, a digital signal when the frequency error falls within a predetermined range (a signal indicating the control voltage Vcont as a digital value, which is output from the control unit 5a to the D / A converter 6) is obtained. As an initial value. Then, each time the user activates the wireless receiver, the control unit 5a reads out the initial value stored in the storage device 53 and sends it to the D / A converter 6. As a result, when the AFC feedback control operation is performed, the frequency error always quickly falls within the predetermined range. That is, in the AFC feedback control operation at the time of manufacture, even if it takes a long time until the frequency error falls within the predetermined range, once the initial value is obtained, the user can actually perform the wireless reception. By using that initial value when starting the machine, the frequency error falls within the predetermined range in a very short time, thus
Quick and accurate reception processing is possible.

Next, a third embodiment will be described. FIG.
FIG. 9 is a block diagram illustrating a configuration of a wireless receiver according to a third embodiment. Since the third embodiment has basically the same configuration as the first embodiment, the same components are denoted by the same reference numerals, and description thereof will be omitted. Only different portions will be described below. explain.

In the third embodiment, the demodulation unit 20b
The frequency synthesizer 60 includes multipliers 21, 22, and a 90 ° phase shifter 23. The frequency synthesizer 60 is connected to the multiplier 21 and the phase shifter 23.
The frequency synthesizer 60 performs frequency synthesis based on the reference signal (frequency fvctcxo) sent from the reference signal generator 1a, generates a carrier signal, and sends it to the demodulator 20b. The frequency synthesizer 60 includes a frequency divider 61 having a frequency division ratio of 1 / M ′ and a frequency division ratio of 1
/ N 'frequency divider 62, phase comparator 63, loop filter 64, and voltage controlled oscillator (VCO) 65, and demodulates a carrier signal of frequency fvctcxo. (N' / M ') to demodulator 20b.
Output to Here, the frequency division ratio 1 / M 'and the frequency division ratio 1 / N' in the frequency synthesis unit 60 are the same as the frequency division ratio 1 / M 'and the frequency division ratio in the frequency synthesis unit 40a in the first embodiment. Although the same sign as that of the circumference ratio 1 / N 'is used, it does not indicate that it is the same value. Here, for convenience, the first
Division ratio 1 in frequency synthesizer 40a in the first embodiment.
/ M 'and the dividing ratio 1 / N', the dividing ratio 1 / M "in FIG.
And the frequency division ratio 1 / N ″.

In this way, the carrier wave signal is also synchronized with the received wave, and therefore, there is no adverse effect on the AFC feedback control caused by the demodulation unit due to the lack of synchronization, and the AFC The pull-in time of the frequency correction (synchronization) is reduced.

Note that, in the third embodiment, the second
Switch 51 and the storage device 5 as in the embodiment.
3 and the reference signal generator 52 may be connected to obtain an initial value and store it.

Next, a fourth embodiment will be described. FIG.
FIG. 14 is a block diagram illustrating a configuration of a wireless receiver according to a fourth embodiment. Since the fourth embodiment has basically the same configuration as the third embodiment, the same components are denoted by the same reference numerals, and the description thereof will be omitted. Only different portions will be described below. explain.

In the fourth embodiment, the frequency synthesizer 40
The clock signal output from a is supplied to the phase detector 3a, the frequency error detector 4a, and the controller 5a. By doing so, all parts of the wireless receiver are synchronized with the received signal, the accuracy of AFC is improved, and the time for pulling in the frequency correction (synchronization) is reduced.

In the fourth embodiment, the second
Switch 51 and the storage device 5 as in the embodiment.
3 and the reference signal generator 52 may be connected to obtain an initial value and store it.

In the fourth embodiment, the clock signal output from the frequency synthesizer 40a is supplied to all of the phase detector 3a, the frequency error detector 4a, and the controller 5a. Alternatively, the information may be supplied to at least one of the phase detector 3a, the frequency error detector 4a, and the controller 5a.

Next, a fifth embodiment will be described. FIG.
FIG. 17 is a block diagram illustrating a configuration of a wireless receiver according to a fifth embodiment. Since the fifth embodiment has basically the same configuration as the third embodiment, the same components are denoted by the same reference numerals and the description thereof will be omitted, and only different portions will be described below. explain.

In the fifth embodiment, a reference signal generator 54 and a D / A are provided between the controller 5a and the frequency synthesizer 40a.
A converter 55 is newly provided, and a reference signal generator 56 and a D / A converter 57 are newly provided between the controller 5a and the frequency synthesizer 60. The reference signal generators 54 and 56
Like the reference signal generator 1a, each is constituted by a voltage-controlled temperature-compensated crystal oscillator (VCTCXO). When the frequency error does not fall within the predetermined allowable range, each digital signal indicating a value proportional to the frequency error is output from the control unit 5a to the D / A converters 55 and 57. The D / A converters 55 and 57 generate control signals indicating the respective values indicated by the digital signals as control voltages and send the control signals to the reference signal generators 54 and 56, respectively. The reference signal generators 54 and 56 generate reference signals in which the oscillation frequency is varied in a direction in which the above-described frequency error is compressed, according to the control signals.

Thus, by providing the reference signal generators 54 and 56 separately from the reference signal generator 1a, it is possible to cope with a case where a desired frequency cannot be synthesized because there is no appropriate frequency division ratio. Will be possible.

It should be noted that the frequency synthesizing section 60 is provided only by newly providing the reference signal generating section 54 and the D / A converter 55 between the control section 5a and the frequency synthesizing section 40a. A configuration using a signal may be used.

Further, also in the fifth embodiment,
As in the second embodiment, a changeover switch 51 and a storage device 53 may be provided, and a reference signal generator 52 may be connected to obtain and store an initial value. However, in this case, the initial value is separately stored for each D / A converter.

Next, a sixth embodiment will be described. FIG.
FIG. 17 is a block diagram illustrating a configuration of a wireless receiver according to a sixth embodiment. Since the sixth embodiment has basically the same configuration as the third embodiment, the same components are denoted by the same reference numerals, and description thereof will be omitted. Only different portions will be described below. explain.

In the sixth embodiment, the frequency synthesizer 40
switch (SW) between a and the A / D converter 30a
The clock signal from the frequency synthesizer 40a is input to one input terminal, and the output clock signal of a newly provided clock oscillator (OSC) 59 is input to the other input terminal. Then, the selection switch 58 is sent from the control unit 5a.
Is sent a selection signal. When the frequency error detected by the frequency error detection unit 4a is equal to or less than a predetermined value, the control unit 5a sends a selection signal instructing to select a clock signal sent from the clock oscillator 59 to the selection switch 58, and When the error exceeds a predetermined value, a selection signal instructing to select the clock signal sent from the frequency synthesizer 40a is sent to the selection switch 58. Note that the control unit 5a sends a selection signal for instructing to select a clock signal sent from the frequency synthesis unit 40a to the selection switch 58 even when the wireless receiver is not synchronized with the received signal. You may do so.

As described above, since there is no feedback when there is no synchronization deviation, the processing is unnecessarily complicated, and as a result, a delay in synchronization can be prevented. In the sixth embodiment, as in the second embodiment, the changeover switch 51 and the storage device 53 may be provided, and the reference signal generator 52 may be connected to obtain an initial value and store the initial value. .

Next, a seventh embodiment will be described. FIG.
FIG. 17 is a block diagram illustrating a configuration of a wireless receiver according to a seventh embodiment. Since the seventh embodiment has basically the same configuration as the fifth embodiment, the same components are denoted by the same reference characters, and description thereof will be omitted. Only different portions will be described below. explain.

The seventh embodiment differs from the fifth embodiment shown in FIG. 6 in that a reference signal generator 56 and a D / A converter 57 are provided between the controller 5a and the frequency synthesizer 60. Instead, the frequency synthesizer 60 uses the reference signal from the reference signal generator 1a. The reference signal generator 54 and D /
A selection switch (SW) 71 is provided between the A / D converter 55 and the A / D converter 55. A control signal from the D / A converter 55 is input to one input terminal, and a newly provided constant voltage unit 72 is connected to the other input terminal.
Is input. D / A converter 55
The control signal outputted from is composed of an analog voltage value. Then, a selection signal is sent from the control unit 5a to the selection switch 71. The control unit 5a includes the frequency error detection unit 4
When the frequency error detected by a is equal to or less than the predetermined value, a selection signal instructing to select a predetermined constant voltage sent from the constant voltage unit 72 is sent to the selection switch 71, and the frequency error exceeds the predetermined value. In this case, the selection switch 71 instructs to select the control signal consisting of the analog voltage value sent from the D / A converter 55.
Send to In addition, the control unit 5a keeps the D / A converter 55 synchronized even when the radio receiver is not synchronized with the received signal.
A selection signal for instructing selection of a control signal consisting of an analog voltage value sent from the control switch may be sent to the selection switch 71.

Thus, since no feedback is performed when there is no synchronization deviation, the processing is unnecessarily complicated, and as a result, a delay in synchronization can be prevented. In the seventh embodiment as well, the changeover switch 51 and the storage device 53 may be provided as in the second embodiment, and the reference signal generator 52 may be connected to obtain an initial value and store the initial value. . However, in this case, the initial value is separately stored for each D / A converter.

Next, an eighth embodiment will be described. FIG.
FIG. 27 is a block diagram illustrating a configuration of a wireless transceiver according to an eighth embodiment. The eighth embodiment relates to a wireless transceiver in which a transmitting unit is further added to a receiving unit 200 having the same configuration as the wireless receiver according to the third embodiment shown in FIG. In FIG. 9, the receiving unit 20
Detailed illustration of 0 is omitted. Since the receiving unit 200 has the same configuration as that of the third embodiment, the following description uses the wireless receiver according to the third embodiment.

In the eighth embodiment, based on the reference signal (frequency fvctcxo) from the reference signal generator 1a of the receiver 200, the frequency synthesizer 210 performs frequency synthesis, generates a clock signal, and generates a clock signal. / A converter 220. The frequency synthesizer 210 includes a frequency divider 211 having a frequency division ratio of 1 / L ″, a frequency divider 212 having a frequency division ratio of 1 / K ″, a phase comparator 213, a loop filter 214, and a voltage controlled oscillator (VCO) 215. , And outputs a clock signal having a frequency fvctcxo · (K ″ / L ″) to the D / A converter 220.

The D / A converter 220 is connected to the D / A converter 22
1 and 222, and converts digital transmission information sent from the transmission information processing unit into an analog signal. The receiving unit 20
0 from the reference signal generator 1a (frequency fvctc
xo), the frequency synthesizer 230 performs frequency synthesis, generates a carrier signal, and sends it to the modulator 240. The frequency synthesizer 230 includes a frequency divider 231 having a frequency division ratio of 1 / L ', a frequency divider 232 having a frequency division ratio of 1 / K', a phase comparator 233, a loop filter 234, and a voltage controlled oscillator (VCO) 235. , And outputs a carrier signal having a frequency fvctcxo · (K ′ / L ′) to the modulation unit 240.

The modulation section 240 includes multipliers 241, 242,
A 90 ° phase shifter 243 performs QPSK modulation. Further, based on the reference signal (frequency fvctcxo) from the reference signal generator 1a of the receiver 200, the local oscillator 250 performs frequency synthesis, generates a local oscillation signal, and sends it to the frequency converter 203. The local oscillator 250 has a frequency division ratio of 1 /
An L frequency divider 251, a frequency divider 252 having a frequency division ratio of 1 / K, a phase comparator 253, a loop filter 254, and a voltage controlled oscillator (VCO) 255, and have a frequency fvctcxo · (K /
The local oscillator signal L) is output to the frequency conversion unit 203.

The frequency conversion section 203 receives the modulated signal from the modulation section 240 through a band-pass filter (BPF) 202, performs frequency conversion to generate a transmission wave, and passes through a band-pass filter (BPF) 204. Power amplifier (P
A) Send to 205. Power amplifier 205 amplifies the transmission wave to a predetermined level and sends it to the antenna.

In this way, the clock signal on the transmitting side
The carrier signal and the local oscillation signal are also synchronized with the received wave.
Therefore, when the transmission wave reaches the transmission source of the reception wave, for example, the base station, the base station can receive a signal synchronized with its own clock.

In the eighth embodiment, the clock signal, the carrier signal, and the local oscillation signal on the transmitting side are all synchronized with the received wave. One or two of them are synchronized with the received wave. May be synchronized.

Next, a ninth embodiment will be described. FIG.
0 is a block diagram illustrating a configuration of a wireless receiver according to a ninth embodiment. Since the ninth embodiment has basically the same configuration as the third embodiment, the same components are denoted by the same reference numerals, and description thereof will be omitted. Only different portions will be described below. explain.

In the ninth embodiment, the changeover switch (S
W) 73 is provided before the low-noise amplifier 7 so that a reception wave is input to one input terminal of the changeover switch 73. Normally, the changeover switch 73 outputs a received wave to the low noise amplifier 7. Further, a storage device 75, a timer 76, and an alarm device 77 are connected to the control unit 5a.

At the time of manufacturing this radio receiver, a reference signal generator 74 is connected to the other input terminal of the changeover switch 73, and the changeover switch 73 is switched to lower the output signal from the reception wave reference signal generator 74. The signal is sent to the noise amplifier 7, and the AFC feedback control operation is performed for the wireless receiver. The reference signal generator 74 is a device that generates a standard modulation signal whose frequency is highly stable (for example, 0.01 ppm).

When the frequency error detected by the frequency error detector 4a falls within a predetermined range as a result of the AFC feedback control operation in the radio receiver, the controller 5a sends the signal to the D / A converter 6 at that time. The output digital signal is stored in the storage device 75 as an initial value. The stored initial value indicates a digital value representing a voltage value (control voltage Vcont) proportional to the frequency error to be sent to the reference signal generator 1a.

That is, similarly to the second embodiment, the power supply voltage value, the magnitude of the output load of the reference signal generator 1a, the capacitance of the trimmer capacitor added for adjusting the oscillation frequency,
Since there is an individual difference in the value of the output resistance of the A-converter 6 for each wireless receiver, the reference signal generator 1a composed of VCTCXO
The frequency of the reference signal in which the error occurs is inevitably different for each wireless receiver. Therefore, as it is, depending on the wireless receiver, it may take as long as 10 seconds or more until the frequency error falls within the predetermined range.

Therefore, at the time of manufacturing, for each radio reception, an AFC feedback control operation is performed in advance using the reference signal generator 74, and a digital signal (control voltage Vcont) when the frequency error falls within a predetermined range is obtained. A signal which is output as a digital value to the D / A converter 6 by the control unit 5a) is obtained and stored in the storage device 75 as an initial value. Then, when the user activates the wireless receiver, the control unit 5 a reads out the initial value stored in the storage device 75 and sends it to the D / A converter 6. As a result, when the AFC feedback control operation is performed, the frequency error always quickly falls within the predetermined range.

Further, in the ninth embodiment, the timer 76
Measures the passage of time since the initial value was stored in the storage device 75. The control unit 5a monitors the measurement time of the timer 76, and the timer 76 determines the predetermined time (for example, 1 to 3 years).
When the elapsed time is measured, the alarm device 77 is operated to urge the operator to update the initial value stored in the storage device 75.

At this time, the operator brings the wireless receiver to a service station or the like, and receives an update of the initial value in the same procedure as the initial value setting at the time of manufacture. Thus, when the frequency error changes due to the aging of the VCTCXO or the like and as a result, it takes time to pull in the synchronization, it can be improved.

In the ninth embodiment, the timer 76
Although the alarm device 77 is provided, the initial value may be updated according to the operator's intention without providing them.

In the ninth embodiment, since the reference signal generator 74 needs to be connected to the changeover switch 73 after manufacturing, the connector of the radio receiver is connected to the changeover switch 73. And the reference signal generator 74 is connected to the changeover switch 73 via this connector. Therefore, when a wireless receiver is used in a vehicle and the vehicle has an antenna for a wireless receiver, the antenna is connected to this connector. This makes it possible to easily receive signals with higher sensitivity than an antenna built in a wireless receiver.

Next, a tenth embodiment will be described. FIG. 11 is a block diagram illustrating a configuration of a wireless receiver according to the tenth embodiment. Since the tenth embodiment has basically the same configuration as the ninth embodiment, the same components will be denoted by the same reference characters, and description thereof will be omitted. Only different portions will be described below. explain.

The tenth embodiment differs from the ninth embodiment in that a timer 76 and an alarm device 77 are not provided.
A storage device 78 is newly provided. In a normal start-up operation, the control unit 5a reads out the initial value stored in the storage device 75 and supplies it to the D / A converter 6, and AFC feedback control is performed. As a result, the frequency error detector 4a
When the frequency error obtained by the above falls within a predetermined allowable range, the control unit 5a calculates the average value of the value represented by the digital signal sent to the D / A converter 6, and stores the average value in the storage device 78. I do. The average value is calculated by storing the values represented by the digital signal each time the signal is obtained and calculating the arithmetic average every predetermined time, or by calculating the average value calculated by the previous time every time a new value is obtained. A weighted average is obtained by adding to the value.

Then, the control unit 5a compares the average value stored in the storage device 78 with the initial value stored in the storage device 75 every predetermined period (for example, one year), and determines a different value. If there is, the average value is stored in the storage device 75 as an initial value.

As a result, when the frequency error changes due to the aging of the VCTCXO or the like, and as a result it takes a long time to pull in the synchronization, it can be improved.

Next, an eleventh embodiment will be described. FIG. 12 is a block diagram showing a configuration of the wireless receiver according to the eleventh embodiment. Since the eleventh embodiment has basically the same configuration as that of the tenth embodiment, the same components are denoted by the same reference numerals, and the description thereof will be omitted. Only different portions will be described below. explain.

In the eleventh embodiment, a timer 79 is newly provided. The timer 79 measures the lapse of time since the initial value was stored in the storage device 75. An average value is stored in the storage device 78 as in the tenth embodiment.

Then, the control unit 5a monitors the time measured by the timer 79, and when the timer 79 measures the elapse of a predetermined time (for example, one year), the control unit 5a is stored in the storage device 78. The average value is stored in the storage device 75 as an initial value.

As a result, when the frequency error changes due to the aging of the VCTCXO or the like and it takes a long time to pull in the synchronization, it can be improved.

[0084]

As described above, according to the present invention, the frequency synthesizing means generates a clock signal by performing frequency synthesizing on the basis of the frequency of the reference signal generated by the reference signal generating means, and outputs the clock signal. Supply to Therefore, A / D
The clock signal supplied to the conversion means is synchronized with the received wave, so that the A / D conversion means does not adversely affect the AFC feedback control, and the pull-in time of the frequency correction (synchronization) by the AFC is made longer than before. Can also be shortened.

If a PLL circuit is used for the frequency synthesizing means, the problem that the frequencies do not match even if the frequency is divided can be solved.
It is also possible to use a VCTCXO that can be currently mounted on a mobile terminal.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a wireless receiver to which the CDMA system according to the first embodiment is applied.

FIG. 3 is a block diagram illustrating a configuration of a wireless receiver according to a second embodiment.

FIG. 4 is a block diagram illustrating a configuration of a wireless receiver according to a third embodiment.

FIG. 5 is a block diagram illustrating a configuration of a wireless receiver according to a fourth embodiment.

FIG. 6 is a block diagram illustrating a configuration of a wireless receiver according to a fifth embodiment.

FIG. 7 is a block diagram illustrating a configuration of a wireless receiver according to a sixth embodiment.

FIG. 8 is a block diagram illustrating a configuration of a wireless receiver according to a seventh embodiment.

FIG. 9 is a block diagram showing a configuration of a wireless transceiver according to an eighth embodiment.

FIG. 10 is a block diagram illustrating a configuration of a wireless receiver according to a ninth embodiment.

FIG. 11 is a block diagram illustrating a configuration of a wireless receiver according to a tenth embodiment.

FIG. 12 is a block diagram illustrating a configuration of a wireless receiver according to an eleventh embodiment.

FIG. 13 is a diagram illustrating a configuration example of a conventional wireless receiver to which a CDMA scheme is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference signal generation means 2 Frequency conversion means 3 Phase detection means 4 Frequency error detection means 5 Control means 6 D / A converter 7 Low noise amplifier 8 Low pass filter 9 Low pass filter 10 Local oscillation means 20 Demodulation means 30 A / D conversion means 40 Frequency synthesis means

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04B 1/707 H04J 13/00 D (72) Inventor Shigeki Takahashi 2-1-1 Kitaichijo Nishi, Chuo-ku, Sapporo, Hokkaido Technology Co., Ltd.

Claims (14)

[Claims] 1. A radio receiver for receiving a digital modulation signal, comprising: a reference signal generating means for generating a reference signal whose frequency can be varied by an external control signal; and a reference signal generated from the reference signal generating means. Local oscillation means for performing local frequency synthesis by performing frequency synthesis based on the frequency of the received signal, taking in a received wave taking a plurality of signal points having different phases in a signal space, and using a local oscillation signal given from the local oscillation means. Frequency converting means for performing frequency conversion of the received wave and generating an intermediate frequency signal; demodulating means for digitally demodulating the intermediate frequency signal generated by the frequency converting means and outputting baseband signals of in-phase and quadrature components And converting the baseband signal of the in-phase component and the quadrature component from analog to digital, respectively, A / D conversion means for outputting a digital signal; a phase detection means for detecting a phase of a signal point based on each digital signal output from the A / D conversion means; The frequency of the sum of the frequency of the local signal and the frequency of the intermediate frequency signal and the frequency of the received wave are obtained by time-differentiating the phase of the signal point output twice in time. Frequency error detection means, control means for providing a control signal for changing the frequency of the reference signal to the reference signal generation means in a direction in which the frequency error determined by the frequency error detection means is compressed, Frequency synthesizing means for synthesizing a frequency based on the frequency of the reference signal generated from the means to generate a clock signal and supplying the clock signal to the A / D conversion means. And a wireless receiver. 2. The apparatus according to claim 1, further comprising a frequency synthesizing unit that performs frequency synthesis on the basis of the frequency of the reference signal generated by the reference signal generating unit, generates a carrier signal, and supplies the carrier signal to the demodulation unit. Item 1. The wireless receiver according to Item 1. 3. The apparatus according to claim 2, further comprising a supply unit that supplies an output of the frequency synthesis unit to at least one of the phase detection unit, the frequency error detection unit, and the control unit as a clock signal. The wireless receiver according to claim 1. 4. A clock generator for generating a clock signal that can be supplied to the A / D converter, one of a clock signal sent from the clock generator and a clock signal sent from the frequency synthesizer. And a selection switch unit that selects based on a selection signal sent from the control unit and supplies it to the A / D conversion unit, wherein the control unit is determined at least by the frequency error detection unit. When the frequency error is equal to or less than a predetermined value, it is instructed to select the clock signal sent from the clock generating means. At least when the frequency error exceeds a predetermined value, the clock signal sent from the frequency synthesizing means is selected. And selecting means for sending a selection signal for instructing selection to the selection switch means. 2. The wireless receiver according to 1. 5. A storage device for storing a control signal steadily output by the control unit when a reference reception wave is given to the frequency conversion unit, wherein the control unit starts the start-up operation. 5. The radio receiver according to claim 1, further comprising a reading unit that reads out the control signal stored in the storage unit and supplies the control signal to the reference signal generation unit. 6. A timer means for measuring an elapse of time from when a control signal is stored in said storage means, and said control signal to an operator when said timer means measures an elapse of a predetermined time. 6. The wireless receiver according to claim 5, further comprising: alarm means for prompting the updating of. 7. The radio receiver according to claim 6, further comprising an input terminal provided on a housing of the radio receiver for taking in a reference reception wave when updating the control signal. 8. The apparatus according to claim 7, further comprising connection means for connecting said input terminal to an external antenna.
The wireless receiver as described. 9. The frequency error obtained by the frequency error detection means falls within a predetermined allowable range after the control means reads out the control signal stored in the storage means and provides it to the reference signal generation means. Average value storage means for storing an average value of the control signal at the time of receiving, the control means for every predetermined period, the average value stored in the average value storage means, stored in the storage means 6. The radio receiver according to claim 5, further comprising control signal updating means for comparing the average value with the control signal in the case where the average value is different, as the control signal. 10. A timer means for measuring a lapse of time from when a control signal is stored in said storage means, and said control means reads out the control signal stored in said storage means and outputs said reference signal generation means. And average value storage means for storing an average value of the control signal when the frequency error obtained by the frequency error detection means falls within a predetermined allowable range, further comprising: 6. A control signal updating unit for storing an average value stored in the average value storage unit as a control signal in the storage unit when the timer unit measures the elapse of a predetermined time. The wireless receiver as described. 11. A radio receiver for receiving a digital modulation signal, wherein: a first reference signal generating means for generating a first reference signal whose frequency can be varied by an external first control signal; A second reference signal generating means for generating a second reference signal whose frequency can be varied by the second control signal, and a frequency of the first reference signal generated from the first reference signal generating means as a reference. Local oscillation means for performing frequency synthesis as a local oscillation signal, and taking in a reception wave taking a plurality of signal points having different phases in a signal space, and receiving the reception wave by the local oscillation signal given from the local oscillation means. Frequency conversion means for performing frequency conversion to generate an intermediate frequency signal; and digitally demodulating the intermediate frequency signal generated by the frequency conversion means to perform baseband of in-phase and quadrature components. Demodulation means for outputting a signal, an analog-to-digital conversion for the in-phase component and quadrature-component baseband signals, and an output of each digital signal, and the A / D conversion means. Based on each digital signal output from the above, based on the phase detection means for detecting the phase of the signal point, by time-differentiating twice the phase of the signal points output in time series from the phase detection means, A sum of the frequency of the local oscillation signal and the frequency of the intermediate frequency signal, and a frequency error detection unit that obtains a frequency error that is a difference between the frequency of the received wave and a frequency error obtained by the frequency error detection unit. A first control signal for changing the frequency of the first reference signal in the direction of compression is provided to the first reference signal generation means, and the frequency error detection means is provided. Control means for providing a second control signal for changing the frequency of the second reference signal to the second reference signal generating means in a direction in which the obtained frequency error is compressed; Frequency receiving means for performing frequency synthesis on the basis of the frequency of the second reference signal generated from the generating means to generate a clock signal and supplying the clock signal to the A / D conversion means. Machine. 12. A constant voltage generating means for generating a constant voltage that can be supplied to said second reference signal generating means, a constant voltage sent from said constant voltage generating means, and a second voltage sent from said control means. Selecting switch means for selecting one of the control signals based on a selection signal sent from the control means and supplying the selected signal to the second reference signal generating means, wherein the control means comprises at least the When the frequency error determined by the frequency error detection means is equal to or less than a predetermined value, it is instructed to select the constant voltage sent from the constant voltage generation means, at least when the frequency error exceeds a predetermined value, 12. The apparatus according to claim 11, further comprising a selection unit that sends a selection signal for instructing selection of a second control signal sent from the control unit to the selection switch unit. Line receiver. 13. A wireless transceiver for transmitting and receiving a digital modulation signal, wherein: a reference signal generating means for generating a reference signal whose frequency can be varied by an external control signal; and a reference signal generated from said reference signal generating means. Receiving local oscillation means for performing local frequency synthesis by performing frequency synthesis based on the frequency of the received signal, and receiving a received wave taking a plurality of signal points having different phases in the signal space, and receiving the received signals from the receiving local oscillation means. The receiving-side frequency converting means for performing frequency conversion of the received wave by the local oscillation signal and generating an intermediate frequency signal, and digitally demodulating the intermediate frequency signal generated by the receiving-side frequency converting means to obtain an in-phase component and a quadrature component. Demodulation means for outputting a baseband signal; from analog to digital for the baseband signal of the in-phase component and the quadrature component A / D conversion means for performing each conversion and outputting each digital signal; phase detection means for detecting the phase of a signal point based on each digital signal output from the A / D conversion means; By time-differentiating the phase of the signal point output from the means in time series twice, the difference between the sum of the frequency of the local oscillation signal and the frequency of the intermediate frequency signal and the frequency of the received wave is obtained. Frequency error detection means for obtaining a frequency error, and control means for providing a control signal for changing the frequency of the reference signal to the reference signal generation means in a direction in which the frequency error obtained by the frequency error detection means is compressed. A first synthesizing unit that performs frequency synthesis on the basis of the frequency of the reference signal generated from the reference signal generating unit to generate a clock signal, and supplies the clock signal to the A / D conversion unit; D / A converting the wavenumber synthesizing means, the transmission information of the digital to analog signal
Conversion means; modulation means for performing digital modulation on the analog signal from the D / A conversion means; and frequency synthesis based on the frequency of the reference signal generated from the reference signal generation means to obtain a local oscillation signal. Transmitting side local oscillation means to generate, frequency conversion by a local oscillation signal given from the transmission side local oscillation means to the modulation signal from the modulation means, transmission side frequency conversion means to generate a transmission wave, A second frequency synthesizing unit that performs frequency synthesis based on the frequency of the reference signal generated from the reference signal generation unit as a reference to generate a clock signal and supplies the clock signal to the D / A conversion unit. Wireless transceiver. 14. The apparatus according to claim 1, further comprising third frequency synthesizing means for performing frequency synthesis on the basis of the frequency of the reference signal generated from said reference signal generating means, generating a carrier signal, and supplying the carrier signal to said modulation means. The wireless transceiver according to claim 13, wherein: