JPH11233806A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the variations of light reception sensitivity and to improve the matching to the manufacturing process of a bipolar transistor, by forming a protection film at a light incidence region for the light reception surface of a semiconductor photodetector and another protection film with a lower refractive index than that of the protection film on the upper layer of the protection film. SOLUTION: An opening is formed at a first interlayer insulation film 7 consisting of silicon oxide on the upper layer of a light reception surface and becomes an incidence region of light for the light reception surface. Then, a second interlayer insulation film 12 consisting of silicon nitride, a third interlayer insulation film 13 consisting of silicon oxide, and a fourth interlayer insulation film 16 consisting of silicon oxide are directly formed on the upper layer of an n<+> -type region 1 as the protection film of a light reception element. The refractive index of the silicon nitride is, for example, 2.0, that of the silicon oxide is, for example, 1.4, and that of the third and fourth interlayer insulation films 13 and 16 is set lower than that of the second interlayer insulation film 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a light receiving element (photodiode) and a method of manufacturing the same, and more particularly to a so-called photo IC (PDIC) having a bipolar IC in addition to the light receiving element and a method of manufacturing the same.

[0002]

2. Description of the Related Art Photodiodes, which are light receiving elements, are capable of converting optical signals into electrical signals, and are widely used as control optical sensors in various optical-electrical conversion devices. Such a photodiode is often mounted on the same semiconductor substrate together with other elements such as a transistor, a resistor, and a capacitor, and is generally manufactured according to a manufacturing process of a bipolar integrated circuit (IC).

FIG. 8 shows a conventional semiconductor device having a bipolar element and a photodiode (photo IC (PDI)).
It is sectional drawing of C)). In the drawing, from the left side, an npn bipolar transistor and a polysilicon resistor are formed as bipolar elements, and an anode common type photodiode is formed as a photodiode in each region of the same semiconductor substrate.

In the region of an npn bipolar transistor
For example, p with a resistivity of 20 Ωcm ^-Type silicon substrate 1
The upper part is the collector region of the npn bipolar transistor.
N⁺The mold buried region 2 is selectively formed. Ma
, P^-On the silicon substrate 1, the resistivity is, for example, 1Ω.
cm and a film thickness of, for example, 1 μm.^-Type epitaxy
Layer 3 is formed. N above⁺Embedding area 2
Is n^-Formed in the epitaxial layer 3
ing.

In the above-mentioned n ⁻ type epitaxial layer 3, for example, silicon oxide (Si) formed by the LOCOS method is used.
An element isolation insulating film 5 made of O ₂ ) is buried. Element isolation is performed by the element isolation insulating film 5, the p ⁺ -type element isolation region 4 formed below the element isolation insulating film 5, and the p ⁻ -type silicon substrate 1. A first interlayer insulating film 7 made of, for example, silicon oxide is formed on the n ⁻ -type epitaxial layer 3 and the element isolation insulating film 5.

A p-type base region 10 is formed in the n ⁻ -type epitaxial layer 3 at a portion surrounded by the element isolation insulating film 5 in the npn bipolar transistor region, and is connected to the p-type base region 10 and formed thereover. The p ⁺ -type polysilicon layer 8 is formed and serves as a base extraction region. An n-type emitter region 1 is provided in the p-type base region 10.
4 'is formed thereon, and an n ⁺ -type polysilicon layer 14 is formed thereon to serve as an emitter extraction region. On the other hand, n ^- n ⁺ -type plug region 6 in the type epitaxial layer 3 to reach the n ⁺ -type buried region 2 is formed. As described above, the emitter region (n-type emitter region 14 ', n
⁺ Type polysilicon layer 14), a base region (p type base region 10, p ⁺ type polysilicon layer 8), and a collector region (n ⁻ type epitaxial layer 3, n ⁺ type buried region 2, n ⁺ type plug region 6). ) Constitute an npn bipolar transistor.

Further, a second interlayer insulating film 12 made of, for example, silicon nitride is formed so as to cover the entire npn bipolar transistor, and a third interlayer insulating film 13 made of, for example, silicon oxide is formed thereon. . A contact is opened in a necessary region of the first to third interlayer insulating films (7, 12, 13), and a first wiring 15 made of a metal wiring formed by laminating, for example, titanium and aluminum is used as an n ⁺ It is formed so as to be connected to the type polysilicon layer 14, the p ⁺ type polysilicon layer 8, and the n ⁺ type plug region 6, respectively. A fourth interlayer insulating film 16 made of, for example, silicon oxide is formed on the first wiring 15,
A second wiring 17 made of a metal wiring formed by laminating, for example, titanium and aluminum is formed on the upper layer. On the upper layer, a protective insulating film 18 made of, for example, silicon nitride is formed so as to cover the whole.

In the polysilicon resistance region,
A p ⁺ -type element isolation region 4 reaching the p ⁻ -type silicon substrate 1 is formed below the element isolation insulating film 5, and a first interlayer insulating film 7 of silicon oxide is formed above the element isolation insulating film 5. ing. A polysilicon layer 9 serving as a resistor is formed thereon.
Are formed. Further, the second interlayer insulating film 1 made of, for example, silicon nitride is coated so as to cover the entire polysilicon layer 9.
2 is formed, and a third interlayer insulating film 13 made of, for example, silicon oxide is formed thereon. Contacts are opened in the second and third interlayer insulating films (12, 13), and a first wiring 15 made of, for example, a metal wiring formed by laminating titanium, aluminum, or the like is formed at a predetermined position of the polysilicon layer 9. Is formed by being connected to. A fourth interlayer insulating film 16 made of, for example, silicon oxide is formed on the first wiring 15, and a second wiring 17 made of a metal wiring formed by stacking, for example, titanium and aluminum is formed on the fourth interlayer insulating film 16. ing. On the upper layer, a protective insulating film 18 made of, for example, silicon nitride is formed so as to cover the whole.

The polysilicon layer 9 forming a resistor is covered with a second interlayer insulating film 12 of silicon nitride, and the silicon nitride film is formed over the entire surface of the semiconductor device, so that a polysilicon resistor 9 is formed. In the heat treatment after the formation, it is possible to prevent hydrogen (H ₂ ) from entering and causing a decrease in the resistance value, and to stabilize the resistance value of the polysilicon resistor.

[0010] In the anode common type photodiode region, n ^{+ is} formed near the surface of the n ⁻ -type epitaxial layer 3 in a portion surrounded by the element isolation insulating film 5.
A mold region 11 is provided. Further, in a portion surrounded by the element isolation insulating film 5 formed adjacent to the n ⁺ type region 11 (on the right side of the n ⁺ type region 11 in the drawing), the p ⁺ type element isolation reaching the p ⁻ type silicon substrate 1 is formed. A region 4 is formed, and a p-type electrode for taking out an anode is formed above the p ⁺ -type element isolation region 4.
^{A +} type polysilicon layer 8 is formed. The p ⁺ -type element isolation region 4 is separated from the n ⁺ -type region 11 by the element isolation insulating film 5 and the n ⁻ -type epitaxial layer 3. n
^- -type epitaxial layer 3 and the p ^- pn junction diode at the junction surface of the type silicon substrate 1 is formed, n
^A cathode formed of the ⁺ type region 11 and the n ⁻ type epitaxial layer 3, an anode formed of the p ⁻ type silicon substrate 1, and an anode common formed by the p ⁺ type element isolation region 4 and the p ⁺ type polysilicon layer 8 for taking out the anode. A type photodiode is configured.

Above the light receiving element, a first interlayer insulating film 7 made of silicon oxide, a second interlayer insulating film 12 made of silicon nitride, a third interlayer insulating film 13 made of silicon oxide, and a fourth interlayer insulating film made of silicon oxide A film 16 and a protective insulating film 18 made of silicon nitride are formed. These first to fourth interlayer insulating films (7, 12, 13, 16) and the protective insulating film 18 allow light to enter the light receiving surface of the photodiode. It has a function as an antireflection film at the time of incidence. The second wiring 17 covers a portion other than the opening, which is the light receiving surface of the photodiode, and serves as a light shield.

[0012]

However, in a semiconductor device including the above-described light receiving element (photodiode), that is, a photo IC (PDIC), there is a problem that the sensitivity of the photodiode varies widely.

The above problem will be specifically described.
Among the anti-reflection films of the photodiode shown in FIG.
The fourth interlayer insulating film 16 made of silicon oxide between the wiring 15 and the second wiring 17 needs to smooth a step caused by the first wiring portion when forming the second wiring 17. The smoothing process is performed, for example, as follows. First, FIG.
As shown in (a), a silicon oxide layer 16a is formed on the entire surface covering the npn bipolar transistor forming region, the polysilicon resistor forming region, and the photodiode forming region.
Is deposited. At this stage, a step occurs on the surface of the silicon oxide layer 16a due to the first wiring 15.

Next, as shown in FIG. 9B, an SOG (spin-on-glass) 16 is formed on the silicon oxide layer 16a.
Apply and dry b. Thereby, steps on the surface of the silicon oxide layer 16a caused by the first wiring 15 are buried to obtain a smoothed shape.

Next, as shown in FIG. 10 (c), for example, RIE (reactive ion etching) is performed to remove the SOG other than the step edge portion while maintaining the smoothed shape, and the surface is smoothed. A silicon oxide layer 16c is obtained.

Next, as shown in FIG. 10D, a silicon oxide layer 16d is further deposited on the silicon oxide layer 16c, and a fourth interlayer having a smoothed surface composed of the silicon oxide layers 16c and 16d is formed. An insulating film 16 is formed.

The above-described smoothing process is complicated, and the thickness of the SOG deposited differs depending on the step. In addition, since the silicon oxide layer is deposited twice, the SOG is deposited once, and the RIE is performed once, the film thickness variations generated in the respective steps are accumulated, and the fourth interlayer insulating layer of the finally formed silicon oxide is stacked. In the worst case, the thickness variation of the film 16 may vary by ± 40%.

In the structure of the anti-reflection film of the photodiode shown in FIG. 8, for example, a first interlayer insulating film (silicon oxide) 7
Has a refractive index of 1.45, a thickness of 130 nm, a refractive index of the second interlayer insulating film (silicon nitride) 12 of 2, and a thickness of 36 n.
m, third and fourth interlayer insulating films (silicon oxide) 13,
16 with a refractive index of 1.45, protective insulating film (silicon nitride)
The refractive index of 18 is 2, the film thickness is 750 nm, and a sufficiently thick transparent mold resin with a refractive index of 1.5 or a bryth with a refractive index of 1.5 is formed above the light receiving element (photodiode). Shall be. In this case, the reflectance of light with respect to the sum of the thicknesses of the third interlayer insulating film 13 and the fourth interlayer insulating film 16 is shown in FIG. In FIG. 11, the wavelength of light is 780 nm used for CD and MD, and the wavelength of light is DVD.
The reflectance at 650 nm used for the measurement is shown. As shown in FIG. 11, the reflectance changes from the maximum value to the minimum value only when the sum of the thicknesses of the third interlayer insulating film 13 and the fourth interlayer insulating film 16 is shifted by about 100 nm. In this case, the variation is very large, for example, from about 55% to about 20%. Assuming that the sum of the thicknesses of the third interlayer insulating film 13 and the fourth interlayer insulating film 16 is, for example, 1.4 μ ± 30%, the reflectance greatly varies within this range.

Therefore, in the conventional photodiode shown in FIG. 8, the variation in the reflectance in the anti-reflection film portion is very large with respect to the variation in the thickness of the fourth interlayer insulating film 16 of silicon oxide. Since a large variation in the reflectance corresponds to a large variation in the ratio of light entering the photodiode, the number of carriers generated by photoelectric conversion in the photodiode varies. Therefore, as a result, a problem that the light receiving sensitivity of the photodiode has a large variation is caused.

The present invention has been made in view of the above-mentioned problems, and accordingly, the present invention has a structure which reduces the variation in the light receiving sensitivity of the photodiode and has good compatibility with the manufacturing process of the bipolar transistor to be mounted. Photodetector with photodiode anti-reflection coating (photodiode)
It is an object of the present invention to provide a semiconductor device having the same and a method for manufacturing the same.

[0021]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a semiconductor light receiving element on a substrate, wherein a light incident area on a light receiving surface of the semiconductor light receiving element is provided. A first protective film having a first refractive index formed at least on the first protective film, and a second protective film having a second refractive index lower than the first refractive index formed on the first protective film. Having.

According to the semiconductor device of the present invention described above, the first refractive index of the first refractive index formed on the light receiving surface of the semiconductor light receiving element.
A laminate of a protective film and a second protective film having a second refractive index has a function as an antireflection film, and the second refractive index is set lower than the first refractive index, Accordingly, even if the above-described variation in the thickness of the interlayer insulating film occurs, the variation in the reflectance can be suppressed to be small, and therefore, the variation in the light receiving sensitivity of the light receiving element can be reduced. In addition, this structure can be formed with good compatibility with the manufacturing process of the bipolar transistor, and can be easily mounted together with the bipolar transistor. The first refractive index and the second refractive index are 1.5 to 2.
5, and 1.3 to 1.6.

The semiconductor device of the present invention is preferably
The first protective film is formed from silicon nitride.
Preferably, the second protective film is formed from silicon oxide. Thereby, it is possible to set the refractive index (second refractive index) of the second protective film to be lower than the refractive index (first refractive index) of the first protective film. Variation in sensitivity can be reduced.

The above-described semiconductor device of the present invention is preferably
A polysilicon resistance element is formed on the substrate.
Preferably, the first protective film is also formed so as to cover an upper layer of the polysilicon resistance element. In the heat treatment after the formation of the polysilicon resistor, the intrusion of hydrogen (H ₂ ) may cause a decrease in the resistance value. In the polysilicon resistor element forming region, the polysilicon resistor is replaced with a first protective film made of, for example, silicon nitride. By covering, it is possible to easily prevent intrusion of hydrogen, and it is possible to mount a polysilicon resistor having a stable resistance value.

The above semiconductor device of the present invention is preferably
A bipolar transistor is formed on the substrate.
The light receiving element having the above structure can be formed with good consistency with the manufacturing process of the bipolar transistor, and can be easily mounted together with the bipolar transistor.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a semiconductor light receiving element and a polysilicon resistance element on a semiconductor substrate. Forming a light-receiving surface of the semiconductor light-receiving element on the semiconductor substrate in the semiconductor light-receiving element formation region, forming a first insulating film in an upper layer of the light-receiving surface and a polysilicon resistance element formation region; Forming a polysilicon layer serving as a resistor on the first insulating film in a silicon resistance element forming region, removing the first insulating film in a light incident region with respect to the light receiving surface; Forming a second insulating film on an upper layer of the light receiving surface and an upper layer of the polysilicon layer in a region where light is incident on the second insulating film; Forming a third insulating film on the upper layer of the first insulating film, forming a first wiring on the third insulating film, forming a fourth insulating film by covering the first wiring, (4) forming a second wiring in an upper layer of the insulating film; and forming the second wiring in a light incident area on the light receiving surface.
Removing the wiring, forming a protective insulating film on the second wiring, and removing the protective insulating film in a light incident area on the light receiving surface.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Forming a light-receiving surface of the semiconductor light-receiving element on the semiconductor substrate in a semiconductor light-receiving element formation region on the semiconductor substrate, forming a first insulating film in an upper layer of the light-receiving surface and a polysilicon resistance element formation region; A polysilicon layer serving as a resistor is formed on the first insulating film. Next, the first in the light incident area on the light receiving surface
The insulating film is removed, and a second insulating film is formed on the light receiving surface and the polysilicon layer in the light incident area on the light receiving surface. Next, a third insulating film is formed on the second insulating film, a first wiring is formed on the third insulating film, a fourth insulating film is formed by covering the first wiring, and a fourth insulating film is formed. A second wiring is formed on the film, and the second wiring in a light incident area on the light receiving surface is removed. Next, a protective insulating film is formed on the second wiring, and the protective insulating film in a light incident region on the light receiving surface is removed.

According to the method of manufacturing a semiconductor device of the present invention described above, a structure in which the light receiving surface of the light receiving element is covered with the second to fourth insulating films can be provided. In this structure, for example, the second insulating film is formed of silicon nitride, and the third and fourth insulating films are formed of silicon oxide. A laminate having a function as an anti-reflection film capable of suppressing variations in reflectance can be reduced, and thus variations in light receiving sensitivity of the light receiving element can be reduced. Further, this structure can be formed with good consistency with the manufacturing process of the bipolar transistor, and can be easily mounted together with the bipolar transistor. On the other hand, a polysilicon layer serving as a polysilicon resistor element is covered with a second insulating film, and by forming the second insulating film with, for example, silicon nitride, hydrogen (H ₂ ) is generated in a heat treatment after the formation of the polysilicon resistor. Intrusion can be prevented, and a polysilicon resistance element having a stabilized resistance value can be formed with good consistency with the formation of the light receiving element.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the second insulating film is formed of silicon nitride. Preferably, the third insulating film and the fourth insulating film are formed of silicon oxide. As described above, it is possible to obtain a laminate having a function as an antireflection film capable of suppressing a variation in reflectance even if a variation in the thickness of the interlayer insulating film occurs.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the method further includes a step of flattening the fourth insulating film after the step of forming the fourth insulating film and before the step of forming the second wiring. Even when the thickness of the interlayer insulating film varies during the planarization, the interlayer insulating film can be formed with a small variation in reflectance.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, the protective insulating film is formed of silicon nitride. Although the protective insulating film is removed in the region where the light receiving element is formed, the removal of the protective insulating film of silicon nitride can be performed simultaneously with the opening of the bonding pad, and the number of steps is not increased.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, the method further includes a step of forming a bipolar transistor on the semiconductor substrate. Since the light receiving element can be formed with good consistency with the manufacturing process of the bipolar transistor, it is easy to mount the light receiving element together with the bipolar transistor.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to the present embodiment. This semiconductor device is a so-called photo IC (PDIC) in which a photodiode (PD) and a bipolar IC are mixedly mounted. In the drawing, from the left side, an npn bipolar transistor and a polysilicon resistor are formed as bipolar elements, and an anode common type photodiode is formed as a photodiode in each region of the same semiconductor substrate. Although not shown, in addition to these elements, an element such as a pnp bipolar transistor and a capacitor may be further provided.

In the npn bipolar transistor region, for example, a p ⁻ type silicon substrate 1 having a resistivity of 20 Ωcm
An n ⁺ -type buried region 2 serving as a collector region of an npn bipolar transistor is selectively formed thereon. On the p ⁻ type silicon substrate 1, the resistivity is, for example, 1Ω.
cm and an n ⁻ -type epitaxial layer 3 having a thickness of, for example, 1 μm. The above n ⁺ type buried region 2
Are also diffused and formed in the n ⁻ -type epitaxial layer 3.

In the n ⁻ type epitaxial layer 3, for example, silicon oxide (Si) formed by the LOCOS method is used.
An element isolation insulating film 5 made of O ₂ ) is buried. Element isolation is performed by the element isolation insulating film 5, the p ⁺ -type element isolation region 4 formed below the element isolation insulating film 5, and the p ⁻ -type silicon substrate 1. A first interlayer insulating film 7 made of, for example, silicon oxide is formed on the n ⁻ -type epitaxial layer 3 and the element isolation insulating film 5.

A p-type base region 10 is formed in the n ⁻ -type epitaxial layer 3 at a portion surrounded by the element isolation insulating film 5 in the npn bipolar transistor region, and is connected to the p-type base region 10 and formed thereover. The p ⁺ -type polysilicon layer 8 is formed and serves as a base extraction region. An n-type emitter region 1 is provided in the p-type base region 10.
4 'is formed thereon, and an n ⁺ -type polysilicon layer 14 is formed thereon to serve as an emitter extraction region. On the other hand, n ^- n ⁺ -type plug region 6 in the type epitaxial layer 3 to reach the n ⁺ -type buried region 2 is formed. As described above, the emitter region (n-type emitter region 14 ', n
⁺ Type polysilicon layer 14), a base region (p type base region 10, p ⁺ type polysilicon layer 8), and a collector region (n ⁻ type epitaxial layer 3, n ⁺ type buried region 2, n ⁺ type plug region 6). ) Constitute an npn bipolar transistor.

Further, a second interlayer insulating film 12 made of, for example, silicon nitride is formed so as to cover the entire npn bipolar transistor, and a third interlayer insulating film 13 made of, for example, silicon oxide is formed thereon. . A contact is opened in a necessary region of the first to third interlayer insulating films (7, 12, 13), and a first wiring 15 made of, for example, titanium is formed on the n ⁺ type polysilicon layer 14, the p ⁺ type polysilicon. It is formed so as to be connected to the layer 8 and the n ⁺ type plug region 6, respectively. A fourth interlayer insulating film 16 made of, for example, silicon oxide is formed on the first wiring 15, and a second wiring 17 made of, for example, titanium or the like is formed thereon.
Are formed. On the upper layer, a protective insulating film 18 made of, for example, silicon nitride is formed so as to cover the whole.

In the polysilicon resistance region,
A p ⁺ -type element isolation region 4 reaching the p ⁻ -type silicon substrate 1 is formed below the element isolation insulating film 5, and a first interlayer insulating film 7 of silicon oxide is formed above the element isolation insulating film 5. ing. A polysilicon layer 9 serving as a resistor is formed thereon.
Are formed. Further, the second interlayer insulating film 1 made of, for example, silicon nitride is coated so as to cover the entire polysilicon layer 9.
2 is formed, and a third interlayer insulating film 13 made of, for example, silicon oxide is formed thereon. Contacts are opened in the second and third interlayer insulating films (12, 13), and a first wiring 15 made of, for example, a metal wiring formed by laminating titanium, aluminum, or the like is formed at a predetermined position of the polysilicon layer 9. Is formed by being connected to. A fourth interlayer insulating film 16 made of, for example, silicon oxide is formed on the first wiring 15, and a second wiring 17 made of a metal wiring formed by stacking, for example, titanium and aluminum is formed on the fourth interlayer insulating film 16. ing. On the upper layer, a protective insulating film 18 made of, for example, silicon nitride is formed so as to cover the whole.

The polysilicon layer 9 forming a resistor is covered with a second interlayer insulating film 12 of silicon nitride, and the silicon nitride film is formed over the entire surface of the semiconductor device, so that the polysilicon resistance 9 is reduced. In the heat treatment after the formation, it is possible to prevent hydrogen (H ₂ ) from entering and causing a decrease in the resistance value, and to stabilize the resistance value of the polysilicon resistor.

Further, in the anode common type photodiode region, n ^{+ is provided} near the surface of the n ⁻ type epitaxial layer 3 in a portion surrounded by the element isolation insulating film 5.
A mold region 11 is provided. Further, in a portion surrounded by the element isolation insulating film 5 formed adjacent to the n ⁺ type region 11 (on the right side of the n ⁺ type region 11 in the drawing), the p ⁺ type element isolation reaching the p ⁻ type silicon substrate 1 is formed. A region 4 is formed, and a p-type electrode for taking out an anode is formed above the p ⁺ -type element isolation region 4.
^{A +} type polysilicon layer 8 is formed. The p ⁺ -type element isolation region 4 is separated from the n ⁺ -type region 11 by the element isolation insulating film 5 and the n ⁻ -type epitaxial layer 3. n
^- -type epitaxial layer 3 and the p ^- pn junction diode at the junction surface of the type silicon substrate 1 is formed, n
^A cathode formed of the ⁺ type region 11 and the n ⁻ type epitaxial layer 3, an anode formed of the p ⁻ type silicon substrate 1, and an anode common formed by the p ⁺ type element isolation region 4 and the p ⁺ type polysilicon layer 8 for taking out the anode. A type photodiode is configured.

In the upper layer of the light receiving surface, an opening is formed in the first interlayer insulating film 7 made of silicon oxide to serve as a light incident region on the light receiving surface.
a second layer made of silicon nitride directly on the n ⁺ -type region 11
An interlayer insulating film 12, a third interlayer insulating film 13 made of silicon oxide, and a fourth interlayer insulating film 16 made of silicon oxide are formed. The refractive index of silicon nitride is, for example, 2.0, the refractive index of silicon oxide is, for example, 1.45, and the third interlayer insulating film 13 and the fourth
The refractive index of the interlayer insulating film 16 is set low. These second to fourth interlayer insulating films (12, 13, 16) have a function as an antireflection film when light is incident on the light receiving surface of the photodiode. The second wiring 17 covers a portion other than the opening, which is the light receiving surface of the photodiode, and serves as a light shield.

Here, in the antireflection film structure of the structure of FIG.
For example, the refractive index of the surface portion of the n ⁺ region 11 on the surface of the n ⁻ type epitaxial layer 3 is 3.7, the refractive index of the second interlayer insulating film 12 of silicon nitride is 2.0, the film thickness is 36 nm, and the third layer of silicon oxide is The refractive indices of the interlayer insulating film 13 and the fourth interlayer insulating film 16 are set to 1.45, and a sufficiently thick transparent mold resin having a refractive index of 1.5 or a refractive index of 1.5 is formed on the light receiving element (photodiode). FIG. 2 shows the reflectance of light with respect to the sum of the film thicknesses of the third interlayer insulating film 13 and the fourth interlayer insulating film 16 when the above prism is formed.
FIG. 2 shows the reflectance at 780 nm used for CD and MD and 650 nm used for DVD as the wavelength of light. As shown in FIG.
In the structure (1), even if the thickness of the interlayer insulating film varies, the variation in the reflectance is within 5%, and the absolute value of the reflectance is as low as 25% or less. Since the variation in the reflectance is small as described above, the variation in the light receiving sensitivity of the light receiving element (photodiode) can be reduced.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described. Until the formation of the polysilicon low resistance body and the base extraction polysilicon of the npn transistor, it can be formed according to a generally known manufacturing method of a bipolar IC process having a double base type bipolar npn transistor. First, steps up to an apparatus shown in FIG. 3A will be described. N ^{+ on} a p ⁻ type silicon substrate 1 having a resistivity of 20 Ωcm
The mold buried region 2 is formed by solid source diffusion using Sb ₂ O ₃ . Next, an n ^-- type epitaxial layer 3 is formed on the p ^-- type silicon substrate 1 with a resistivity of 1?
It is deposited under the condition of μm. Next, an element isolation insulating film 5 of silicon oxide is formed to a thickness of 800 nm by, for example, the LOCOS method. This is because, for example, the n ⁻ -type epitaxial layer 3
A thermal oxide film is formed on the surface to a thickness of 50 nm, and a silicon nitride film is formed to a thickness of 100 nm by a low pressure CVD method. The silicon nitride film, the thermal oxide film and the n ⁻ -type epitaxial layer 3 in the LOCOS element isolation insulating film formation region are selectively removed. RIE
(Reactive ion etching)
It can be formed by performing thermal oxidation using the remaining silicon nitride film as a mask. The silicon nitride film formed at this time is removed by, for example, phosphoric acid (hot phosphoric acid) heated to 150 ° C.

Next, for example, phosphorus is added to 50 KeV, 5 × 10 5
Implanted in the ¹⁵ atoms / cm ² conditions, 10 in an N ₂ atmosphere
An activation heat treatment is performed at 00 ° C. for 30 minutes to form an n ⁺ -type plug region 6. Next, boron was applied at 360 KeV and 5 ×
Ions are implanted under the condition of 10 ¹³ atoms / cm ² to form p ⁺ -type element isolation regions 4. Next, a first interlayer insulating film 7 is formed by depositing silicon oxide to a thickness of 100 nm over the entire surface by, for example, a CVD method. Next, in the npn bipolar transistor formation region, the region for forming the emitter and the base and the first interlayer insulating film 7 in the opening region for taking out the anode in the photodiode formation region are selectively removed by etching such as RIE. .

Next, polysilicon is deposited to a thickness of 150 nm on the entire surface by, for example, a low pressure CVD method, and BF ₂ is selectively deposited at 50 Ke in a polysilicon resistance formation region.
V ions are implanted into the polysilicon layer under the conditions of 5 × 10 ¹⁴ atoms / cm ² . Subsequently, a polysilicon region for taking out the base of the npn bipolar transistor formation region, a contact region with the metal wiring of the polysilicon layer, and
¹⁵ KeV boron, 3 × 10 ¹⁵ atoms / cm in the polysilicon region for taking out the anode in the photodiode formation region
Ions are implanted at a ^second condition, npn bipolar transistors forming the p ⁺ -type polysilicon layer 8 serves as a base extraction region of the region, the polysilicon layer 9 forming the resistor of the polysilicon resistor forming region, and the anode of the photo diode forming region Etching such as RIE is selectively performed leaving the p ⁺ -type polysilicon layer 8 for taking out. With the above, FIG.
The device shown in FIG.

Next, as shown in FIG. 3B, the first interlayer insulating film 7 on the light receiving surface in the photodiode forming region
Is selectively removed by etching such as RIE,
For example, silicon nitride is deposited to a thickness of 36 nm by a low pressure CVD method to form the second interlayer insulating film 12.

Next, as shown in FIG.
Silicon oxide is deposited to a thickness of 300 nm by a VD method to form a silicon oxide layer 13a. In the npn bipolar transistor forming region, the silicon oxide layer 13a in the region serving as an emitter, the second interlayer insulating film 12, and p ⁺
The mold polysilicon layer 8 is selectively removed by etching such as RIE. Next, for example, at 900 ° C. in an O ₂ atmosphere,
In order to form a thermal oxide film on the surface of the n ⁻ -type epitaxial layer 3 by performing heat treatment for 0 minutes and to form a p-type base region, boron is ion-implanted under the conditions of 30 KeV and 1 × 10 ¹³ atoms / cm ^2. I do.

Next, as shown in FIG.
Silicon oxide is deposited to a thickness of 550 nm by the VD method, and a heat treatment is performed, for example, at 900 ° C. for 15 minutes in an N ₂ atmosphere in order to activate impurities (boron) in the p-type base region. Next, the silicon oxide is etched back by, for example, RIE or the like to a thickness of 600 nm to leave the silicon oxide sidewall 13b on the side wall of the opening for taking out the base. A third interlayer insulating film 13 is formed from the silicon oxide layer 13a and the sidewall 13b.

Next, as shown in FIG. 5E, in accordance with a general manufacturing method of a bipolar IC process having an npn transistor having a double polysilicon structure, a polysilicon layer serving as an emitter is formed by, for example, a low pressure CVD method to a thickness of 150 nm.
arsenic (As ⁺ ), 50 KeV,
Ions are implanted under the condition of 1 × 10 ¹⁶ atoms / cm ² to form an n ⁺ -type polysilicon layer 14. Next, silicon oxide is deposited to a thickness of 300 nm by, for example, a CVD method, and heat treatment is performed at 900 ° C. for 30 minutes in an N ₂ atmosphere, for example, to activate an emitter impurity (arsenic). Heat treatment at 1100 ° C. for 10 seconds is performed in an N ₂ atmosphere by RTA (Rapid thermal anneal) processing. Then, the n ⁺ -type polysilicon layer 14 over the silicon oxide film serving as the emitter region is removed by wet etching hydrofluoric acid (HF) system, the n ⁺ -type polysilicon layer 14 serving as the emitter region of the npn bipolar transistor Etching, such as RIE, is performed, leaving selectively. On the other hand, in the photodiode formation region,
Ion implantation of n-type impurities such as arsenic or phosphorus,
An n ⁺ -type region 11 is provided near the surface of n ⁻ -type epitaxial layer 3.
To form

Next, by etching such as RIE, p-type is formed in the npn bipolar transistor forming region.
^The opening for exposing the ⁺ type polysilicon layer 8 and the n ⁺ type plug region 6, the opening for exposing the polysilicon layer 9 in the polysilicon resistance forming region, and the n ⁺ type region 11 in the photodiode forming region. Are formed, and heat treatment is performed at 400 ° C. for 60 minutes in an atmosphere of Fo gas (mixed gas of 95% N ₂ + 5% H ₂ ) in order to alleviate RIE damage remaining in the opening. Next, for example, by sputtering method Ti / TiON / Ti / A
lSi is deposited in a thickness of 30/70/50/600 nm and patterned to form an n ⁺ -type polysilicon layer 14, a p ⁺ -type polysilicon layer 8 and an n ⁺ -type plug region 6 in an npn bipolar transistor formation region. Next, a first wiring 15 is formed to be connected to the polysilicon layer 9 in the polysilicon resistance formation region and to the n ⁺ type region 11 in the photodiode formation region.

Next, as shown in FIG. 5F, a silicon oxide layer 16a is deposited on the entire surface to cover the npn bipolar transistor forming region, the polysilicon resistor forming region, and the photodiode forming region. At this stage,
A step occurs on the surface of the silicon oxide layer 16a due to the first wiring 15.

Next, as shown in FIG. 6G, an SOG (spin-on-glass) 16 is formed on the silicon oxide layer 16a.
Apply and dry b. Thereby, steps on the surface of the silicon oxide layer 16a caused by the first wiring 15 are buried to obtain a smoothed shape.

Next, as shown in FIG.
IE (Reactive Ion Etching) is performed to remove the SOG other than the step edge portion while maintaining the smoothed shape, thereby obtaining the smoothed silicon oxide layer 16c.

Next, as shown in FIG. 7 (i), a silicon oxide layer 16d is further deposited on the silicon oxide layer 16c, and a fourth interlayer having a smoothed surface composed of the silicon oxide layers 16c and 16d is formed. An insulating film 16 is formed.

Next, as shown in FIG. 7J, for example, a contact hole (not shown) reaching the first wiring 15 is formed by RI.
After being formed by E or the like, the second wiring 17 is formed by stacking Ti / AlSi to a thickness of 100/700 nm by, for example, a sputtering method, and performing patterning. At this time, patterning is performed so as to remove the second wiring 17 in the light receiving region of the photodiode.

Next, silicon nitride is deposited by, for example, a plasma CVD method to form a protective insulating film 18, and the protective insulating film 18 in the bonding pad portion and the light receiving region of the photodiode is selectively formed by, for example, RIE. It is removed by etching, and 400
A heat treatment at 60 ° C. for 60 minutes is performed to sinter the metal wiring film. Thus, the semiconductor device shown in FIG. 1 is obtained.

According to the method of manufacturing a semiconductor device of the present embodiment, the second insulating film made of silicon nitride and the third and fourth films made of silicon oxide are formed on the light receiving surface of the light receiving element as antireflection films.
Since the insulating film is formed so as to cover, even if the thickness of the interlayer insulating film varies, the variation in the reflectance can be suppressed small, and the variation in the light receiving sensitivity of the light receiving element can be reduced. is there. Further, this structure can be formed with good consistency with the manufacturing process of the bipolar transistor, and can be easily mounted together with the bipolar transistor.
On the other hand, a polysilicon layer serving as a polysilicon resistor element is covered with a second insulating film, and by forming the second insulating film with, for example, silicon nitride, hydrogen (H ₂ ) is generated in a heat treatment after the formation of the polysilicon resistor. Intrusion can be prevented, and a polysilicon resistance element having a stabilized resistance value can be formed with good consistency with the formation of the light receiving element.

The semiconductor device and the method of manufacturing the same according to the present invention
It is not limited to the above embodiment. For example, although the bipolar transistor is an npn type, it may be a pnp type, or may have both an npn type and a pnp type. Further, it is also possible to mix a capacitor element and other semiconductor elements. In addition, various changes can be made without departing from the gist of the present invention.

[0060]

As described above, according to the semiconductor device of the present invention, even if the thickness of the interlayer insulating film varies, the variation in the reflectance can be suppressed to a small value. Variation in sensitivity can be reduced. In addition, this structure can be formed with good compatibility with the manufacturing process of the bipolar transistor, and can be easily mounted together with the bipolar transistor.

Further, according to the method of manufacturing a semiconductor device of the present invention, a laminate having a function as an antireflection film capable of suppressing a variation in reflectance even if a variation in the thickness of an interlayer insulating film occurs. Therefore, it is possible to reduce the variation in the light receiving sensitivity of the light receiving element. Further, it can be formed with good consistency with the manufacturing process of the bipolar transistor, and can be easily mounted together with the bipolar transistor. Further, a polysilicon resistance element having a stabilized resistance value can be formed with good consistency with the formation of the light receiving element.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a graph showing a change in reflectance with respect to a variation in film thickness of an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

3A and 3B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3A illustrates a polysilicon layer serving as a resistor and p ^{+ serving as} a base extraction region of a transistor. (B) shows the process up to the process of forming the mold polysilicon layer and the process up to the process of forming the second interlayer insulating film.

FIG. 4 is a sectional view showing a step subsequent to that of FIG. 3;
(C) shows the steps up to the step of opening the base and emitter regions of the transistor, and (d) shows the steps up to the step of forming the sidewalls of the opening.

FIG. 5 is a sectional view showing a step subsequent to that of FIG. 4;
(E) shows up to the step of forming a first wiring, and (f) shows up to the step of forming a silicon oxide layer to be a third interlayer insulating film.

FIG. 6 is a sectional view showing a step subsequent to that of FIG. 5;
(G) shows the steps up to the step of applying and drying SOG, and (h) shows the steps up to the step of etching the silicon oxide layer while maintaining the flattened shape.

FIG. 7 is a sectional view showing a step subsequent to that of FIG. 6;
(I) shows the process up to the step of forming the third interlayer insulating film, and (j) shows the process
The steps up to the step of forming the wiring are shown.

FIG. 8 is a sectional view of a semiconductor device according to a conventional example.

FIGS. 9A and 9B are cross-sectional views showing a manufacturing process of a method of manufacturing a semiconductor device according to a conventional example, in which FIG. 9A shows a process up to a process of forming a silicon oxide layer serving as a third interlayer insulating film, and FIG.
Up to the application and drying steps.

10 is a cross-sectional view showing a step subsequent to that of FIG. 9; FIG. 10C shows a step until an etching step of a silicon oxide layer maintaining a flattened shape; and FIG. 10D shows a step of forming a third interlayer insulating film. Up to

FIG. 11 is a graph showing a change in reflectance with respect to a variation in film thickness of an interlayer insulating film of a semiconductor device according to a conventional example.

[Explanation of symbols]

1 ... p ^- -type silicon substrate, 2 ... n ⁺ -type buried region, 3
... n ^- type epitaxial layers, 4 ... p ⁺ type element isolation regions,
5 ... element isolation insulating film, 6 ... n ⁺ type plug region, 7 ... first
Interlayer insulating film, 8 ... p ⁺ type polysilicon layer, 9 ... Polysilicon layer forming resistor, 10 ... p type base region, 11 ... n
⁺ Type region, 12 ... second interlayer insulating film, 13 ... third interlayer insulating film, 14 ... n ⁺ type polysilicon layer, 14 '... n type emitter region, 15 ... first wiring, 16 ... fourth interlayer insulating film , 17
... second wiring, 18 ... protective insulating film.

Claims (13)

[Claims] 1. A semiconductor device having a semiconductor light receiving element on a substrate, comprising: a first protective film having a first refractive index formed at least in a light incident area on a light receiving surface of the semiconductor light receiving element; And a second protective film having a second refractive index lower than the first refractive index formed on the first protective film. 2. The semiconductor according to claim 1, wherein said first refractive index is in a range of 1.5 to 2.5, and said second refractive index is in a range of 1.3 to 1.6. apparatus. 3. The semiconductor device according to claim 1, wherein said first protective film is formed of silicon nitride. 4. The semiconductor device according to claim 1, wherein said second protective film is formed of silicon oxide. 5. The semiconductor device according to claim 1, wherein a polysilicon resistance element is formed on said substrate. 6. The semiconductor device according to claim 5, wherein said first protective film is formed so as to cover an upper layer of said polysilicon resistance element. 7. The semiconductor device according to claim 1, wherein a bipolar transistor is formed on said substrate. 8. A method for manufacturing a semiconductor device having a semiconductor light receiving element and a polysilicon resistance element on a semiconductor substrate, wherein:
Forming a light receiving surface of the semiconductor light receiving element on the semiconductor substrate; forming a first insulating film in an upper layer of the light receiving surface and a polysilicon resistance element forming region; (1) forming a polysilicon layer serving as a resistor on an insulating film; (b) removing the first insulating film in a light incident area on the light receiving surface; and receiving the light in a light incident area on the light receiving surface. Forming a second insulating film on the upper layer of the surface and the polysilicon layer; forming a third insulating film on the second insulating film; and forming a first wiring on the third insulating film. Forming a fourth insulating film by covering the first wiring; forming a second wiring on an upper layer of the fourth insulating film; and forming a light incident area on the light receiving surface. Removing the second wiring, forming a protective insulating film on an upper layer of the second wiring, and removing the protective insulating film in a light incident region on the light receiving surface. Production method. 9. The method according to claim 8, wherein said second insulating film is formed of silicon nitride. 10. The method according to claim 8, wherein said third insulating film and said fourth insulating film are formed of silicon oxide. 11. The semiconductor device according to claim 8, further comprising a step of flattening the fourth insulating film after the step of forming the fourth insulating film and before the step of forming the second wiring. Production method. 12. The method according to claim 8, wherein said protective insulating film is formed of silicon nitride. 13. The method according to claim 8, further comprising the step of forming a bipolar transistor on said semiconductor substrate.