JPH11233744A - Non-volatile semiconductor storage device and method for driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read data at a high speed under low voltage by connecting a plurality of memory cells included in a column with a first source line, connecting of a plurality of memory cells included in a neighboring column with a second source line, and by making the first source line electrically independent from the second source line. SOLUTION: A source line SL1 corresponds to a column including M11 to M14, a source line SL2 corresponds to a column including M21 to M24, a source line SL3 corresponds to a column including M31 to M34, and a source line SL4 corresponds to a column including M41 to M44. That is, in a non-volatile semiconductor memory device 10, a memory cell of one column does not share a source line with a memory cell of the other column. Further, an element- separating region and a bit line contact are provided, and the element-separating region is positioned between the source line SL2 and the source line SL3, whereby neighboring source lines are electrically independent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a mask type and floating gate electrode type nonvolatile semiconductor memory device and a method of driving the same.

[0002]

2. Description of the Related Art In recent years, non-volatile semiconductor memory devices which operate at a low voltage and at a high speed have been used. In order to widely provide such a nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device that can operate at high speed at a low voltage and a driving method of the nonvolatile semiconductor memory device are required.

Hereinafter, a conventional nonvolatile semiconductor memory device 50 will be described.
0 will be described with reference to FIGS. 15, 16 and 17.

The nonvolatile semiconductor memory device 500 has a memory cell array structure called a NOR type because a plurality of memory cells are connected in parallel to bit lines.

FIG. 15 is a schematic diagram showing a memory cell array configuration of a conventional nonvolatile semiconductor memory device 500.

A nonvolatile semiconductor memory device 50 shown in FIG.
0 is a memory cell M11-
M44, word lines WL1 to WL4, source lines SL1 to S
L3 and bit lines BL1 to BL4.

[0007] The non-volatile semiconductor memory device 500 is similar to that shown in FIG.
As shown in the figure, the gate of the memory cell M24 is connected to the word line W
L2, the source of the memory cell M24 is connected to the source line SL2, and the drain of the memory cell M24 is connected to the bit line BL4. In the nonvolatile semiconductor memory device 500, the memory cells in the row to which the memory cells M21 to M24 belong share the source line SL2 with the memory cells in the row to which the memory cells M31 to M34 belong. The memory cells in the row to which the memory cells M11 to M14 belong are the memory cells (not shown) in the opposing row and the source line S.
L1 is shared. The same applies to the source line SL3.

FIG. 16 is a schematic plan view showing a pattern layout of the nonvolatile semiconductor memory device 500 shown in FIG.

As shown in FIG. 16, the nonvolatile semiconductor memory device 500 further includes an element isolation region 5 and a bit line contact 6.

Hereinafter, a conventional nonvolatile semiconductor memory device 50 will be described.
A method of writing information to 0 and an erasing method will be described with reference to FIG.

FIG. 17 shows a nonvolatile semiconductor memory device 500.
FIG. 7 is a threshold voltage distribution diagram (a plurality of memory cells) of a memory cell in FIG. In FIG. 17, the horizontal axis indicates the threshold voltage _VTM of the memory cell, and the vertical axis indicates the number of memory cells.

Here, the nonvolatile semiconductor memory device 500
Is a mask ROM composed of N-type MOS transistors having two different threshold voltages.

The erase state ("E" state in FIG. 17)
The N-type MOS transistor is set to a threshold voltage of about 1 V (lower threshold voltage) which is an enhancement state, and the erase state is a state in which ion implantation is performed on a channel portion of a memory cell of the entire memory array. Controlled by the law.

The write state (the "W" state in FIG. 17) is defined as a state in which the ion implantation is further performed only on the channel portion of the selected N-type MOS transistor to increase the power supply voltage from the power supply voltage V _DD. A threshold voltage of about 4 V in a high enhancement state (higher threshold voltage)
Is set.

Hereinafter, a conventional nonvolatile semiconductor memory device 50 will be described.
A method for reading information from 0 will be described with reference to FIG.

A memory cell M24 surrounded by a broken line in FIG.
Is selected, the semiconductor substrate potential is set to the ground potential (0
V), the word line WL2 is set to 3V, and the bit line BL
4 is set to 1V. Further, other word lines WL1, WL3,
WL4, the source lines SL1, SL2, SL3, and the other bit lines BL1, BL2, BL3 are set to 0V or OPEN state. Note that the semiconductor substrate on which the memory cell array of FIG. 15 is arranged is fixed to the ground potential, and serves as a reference potential when applying a voltage to other parts.

If the memory cell M24 is in an erased state, the threshold voltage is about 0.5 V, so that the memory cell M24 is turned on and a memory cell read current flows to the bit line BL4. On the other hand, if the memory cell M24 is in the write state, the threshold voltage is about 4 V, so that the memory cell M24 is turned off and the bit line BL
4, no memory cell read current flows. A read operation is performed by detecting this amount of current with a sense amplifier.

As described above, the operation of reading the information stored in the memory cell M24 is performed by using the amount of the read current flowing through the selected memory cell M24. Unselected memory cells (M1) connected to the same bit line BL4
4, M34, M44) must be suppressed to almost zero. For that purpose, the threshold voltage of these unselected memory cells must be set to about 0.5 V or more.

[0019]

However, in the conventional nonvolatile semiconductor memory device 500 and its rewriting method, the threshold voltage of the memory cell in the erased state, that is, the lower threshold voltage is about 0.5 V or more. Therefore, when the nonvolatile semiconductor memory device 500 is operated at a low voltage (low power supply voltage), the read current of the memory cell in the erased state (ON state) at the time of reading is reduced, and it is difficult to read at high speed. There was a problem of becoming.

In view of the above problems, the present invention provides a nonvolatile semiconductor memory device capable of securing a sufficient ON-state memory cell read current even at a low voltage, enabling high-speed read at a low voltage, and a nonvolatile semiconductor memory device therefor. It is an object to provide a driving method.

[0021]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a plurality of memory cells arranged in a matrix on a semiconductor substrate; a plurality of word lines extending in a row direction; A plurality of source lines extending in a row and a plurality of bit lines extending in a column direction, wherein a plurality of memory cells belonging to a certain row include a first one of the plurality of source lines. A plurality of memory cells connected to a source line and belonging to a row adjacent to the certain row are connected to a second source line of the plurality of source lines;
The first source line is electrically independent of the second source line, thereby achieving the above object.

[0022] The first source line may be insulated from the second source line by an element isolation region.

Another nonvolatile semiconductor memory device according to the present invention comprises:
On a semiconductor substrate, a plurality of memory cells arranged in a matrix, a plurality of word lines extending in a row direction, a plurality of source lines extending in the row direction, and a plurality of bit lines extending in a column direction are provided. A non-volatile semiconductor storage device,
A first set of the plurality of memory cells belonging to a certain column is
A second bit line connected to a first one of the plurality of bit lines and connected to a first one of the plurality of bit lines;
Are connected to a second bit line of the plurality of bit lines, and the first bit line is electrically independent of the second bit line, thereby achieving the above object. You.

[0024] The first set may be adjacent to the second set in the column direction.

[0025] Each of the plurality of memory cells may be a MOS transistor having a gate electrode, a gate insulating film, a drain region and a source region.

[0026] Each of the plurality of memory cells may be a floating gate electrode type MOS transistor having a control gate electrode, a floating gate electrode, a drain region and a source region.

[0027] Among the plurality of memory cells, a memory cell having a lower threshold voltage may be in a depletion state.

The nonvolatile semiconductor memory device includes a plurality of first conductivity type wells extending in the row direction, and one of the plurality of memory cells is located above one of the plurality of first conductivity type wells. A MOS transistor having a gate electrode, a gate insulating film, a drain region and a source region,
Each of the plurality of first conductivity type wells may be electrically independent.

The nonvolatile semiconductor memory device includes a plurality of first conductivity type wells extending in the row direction, and one of the plurality of memory cells is located above one of the plurality of first conductivity type wells. Having a control gate electrode, a floating gate electrode, a gate insulating film, a drain region and a source region
The transistor may be a transistor, and each of the plurality of first conductivity type wells may be electrically independent.

[0030] A method of driving a nonvolatile semiconductor memory device for reading information stored in a memory cell selected from the plurality of memory cells, wherein a bit line corresponding to the selected memory cell includes Applying a first voltage having a reverse bias to the substrate; and applying the first voltage to a word line corresponding to the selected memory cell.
Applying a second voltage having the same polarity as the first voltage, and applying a third voltage having the same polarity as the first voltage to source lines corresponding to memory cells other than the selected memory cell. Applying a potential of the semiconductor substrate to a source line corresponding to the selected memory cell.

[0031] The first voltage and the third voltage may be substantially the same voltage.

[0032] Information stored in a memory cell selected from the plurality of memory cells may be read.

Applying a first voltage having a reverse bias to the semiconductor substrate to a bit line corresponding to the selected memory cell; and applying a first voltage to a word line corresponding to the selected memory cell. Applying a second voltage having the same polarity as the first voltage, and applying a third voltage having a polarity opposite to the first voltage to a first conductivity type well to which the selected memory cell does not belong. The method may include a step of applying a ground potential to a well of the first conductivity type to which the selected memory cell belongs.

The operation will be described below.

According to the present invention, the lower limit of the threshold voltage of the selected memory cell is allowed to be a depletion type, and the lower limit of the threshold voltage of the non-selected memory cell on the same bit line as the selected memory cell is backed up. The enhancement effect is achieved by a bias effect.

In the nonvolatile semiconductor memory device according to the present invention, an array structure in which the potential of the source line of the selected memory cell can be set to a potential different from that of the source line of the non-selected memory cell,
Alternatively, it has an array structure in which the potential of a well line of a selected memory cell can be set to a different potential from the well line of a non-selected memory cell.

For writing and erasing information in the nonvolatile semiconductor memory device of the present invention, a depletion state is allowed as a lower limit of a threshold voltage in a memory cell in an erased state.

In the method of driving a nonvolatile semiconductor memory device for reading information stored in a memory cell selected from a plurality of memory cells, the source line of the selected memory cell is set to the ground potential, The source line of the cell is set to a positive voltage, or the well line of the selected memory cell is set to the ground potential, and the well line of the unselected memory cell is set to the negative voltage.

In the nonvolatile semiconductor memory device of the present invention, the threshold voltage of the non-selected memory cell is obtained by applying a reverse bias voltage to the source line of the non-selected memory cell with respect to the semiconductor substrate. Is higher. For this reason, in the nonvolatile semiconductor memory device of the present invention, the lower threshold voltage of the memory cell can be set lower than that of the conventional nonvolatile semiconductor memory device. The read current amount of the cell can be secured. As a result, the nonvolatile semiconductor memory device of the present invention enables high-speed reading at a low voltage.

In the nonvolatile semiconductor memory device of the present invention, since at least a part of the lower threshold voltage state of the memory cell is in the depletion state, the read current in that state can be increased, and , The reading speed can be further increased.

According to the method of driving a nonvolatile semiconductor memory device for reading out information stored in a memory cell selected from a plurality of memory cells according to the present invention, a source line of a non-selected memory cell is connected to a semiconductor substrate in reverse. The threshold voltage of the non-selected memory cells can be increased by the back bias effect caused by applying the bias voltage. Therefore, according to the driving method of the present invention, the lower threshold voltage of the memory cell can be set lower than the conventional driving method,
Even at a low voltage, a sufficient read current amount of the memory cell in the ON state can be secured. As a result, the driving method of the present invention enables high-speed reading at a low voltage.

According to the driving method of the present invention, since the back bias effect is large and no current flows from the source line, the highest speed reading performance can be improved.

In another nonvolatile semiconductor memory device of the present invention, the threshold of the non-selected memory cell is generated by applying a forward bias voltage to the semiconductor substrate to the well line of the non-selected memory cell. The value voltage is increased. For this reason, in the other nonvolatile semiconductor memory device of the present invention, the lower threshold voltage of the memory cell can be set lower than that of the conventional nonvolatile semiconductor memory device. The read current amount can be secured. As a result, another nonvolatile semiconductor memory device of the present invention enables high-speed reading at a low voltage.

In another nonvolatile semiconductor memory device of the present invention, since at least a part of the lower threshold voltage state of the memory cell is in the depletion state, the read current in that state can be increased, and The reading speed under voltage can be further increased.

Another driving method of a nonvolatile semiconductor memory device for reading information stored in a memory cell selected from a plurality of memory cells according to the present invention is as follows. As a result, the threshold voltage of the non-selected memory cells can be increased by a back bias effect caused by applying a forward bias voltage. Therefore, according to another driving method of the present invention, the lower threshold voltage of the memory cell can be set lower than that of the conventional driving method, and a sufficient read current amount of the on-state memory cell can be ensured even at a low voltage. As a result, another driving method of the present invention enables high-speed reading at a low voltage.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram of a memory cell array configuration of a nonvolatile semiconductor memory device 10 according to the first embodiment of the present invention.

The nonvolatile semiconductor memory device 10 includes memory cells M11 to M44 formed of MOS transistors, word lines WL1 to WL4, source lines SL1 to SL4, and bit lines BL1 to BL4.

In the nonvolatile semiconductor memory device 10, the gate of the memory cell M24 is connected to the word line WL2, the source of the memory cell M24 is connected to the source line SL2, and the drain of the memory cell M24 is connected to the bit line BL4. I have.

The source line SL1 corresponds to the row to which the memory cells M11 to M14 belong, the source line SL2 to the row to which the memory cells M21 to M24 belong, and the memory cells M31 to M24.
The source line SL3 corresponds to the row to which M34 belongs, and the source line SL4 corresponds to the row to which the memory cells M41 to M44 belong. That is, in the nonvolatile semiconductor memory device 10, a memory cell in a certain row does not share a source line with a memory cell in another row.

FIG. 2 is a schematic plan view showing a pattern layout of the nonvolatile semiconductor memory device 10. That is, FIG. 2 shows an example of an array structure of the nonvolatile semiconductor memory device 10 shown in FIG. 3 is a diagram showing a cross section when the nonvolatile semiconductor memory device 10 shown in FIG. 2 is cut along line AA. FIG. 4 is a diagram showing the nonvolatile semiconductor memory device 10 shown in FIG. It is a figure which shows the cross section at the time of cut | disconnecting by BB.

The nonvolatile semiconductor memory device 10 has a memory cell array structure called a NOR type because a plurality of memory cells are connected in parallel to bit lines.

As shown in FIG. 2, the nonvolatile semiconductor memory device 10 further includes an element isolation region 5,
X and bit line contacts 6a and 6b. For example, the element isolation region 5X is located between the adjacent source lines SL2 and SL3. For this reason,
Adjacent source lines are electrically independent. The element isolation region 5 and the element isolation region 5X are LOCOS (LOC
al Oxidation of Silicon),
STI (Shallow Trench Isolat)
ion), but other methods may be used.

Hereinafter, a method for writing and erasing information in the nonvolatile semiconductor memory device 10 will be described with reference to FIG.

FIG. 5 is a threshold voltage distribution diagram (a plurality of memory cells) of a memory cell in nonvolatile semiconductor memory device 10. In FIG. 5, the horizontal axis indicates the threshold voltage _VTM of the memory cell, and the vertical axis indicates the number of memory cells.

Here, the nonvolatile semiconductor memory device 10
Is a mask ROM composed of N-type MOS transistors having two different threshold voltages.

The erase state (the “E” state in FIG. 5)
Type MOS transistor is in a depletion state-
This means that the threshold voltage is set to about 1 V (lower threshold voltage), and the erased state is controlled by the ion implantation method for the channel portion of the memory cell of the entire memory array.

The write state ("W" state in FIG. 5) is defined as a state in which the ion implantation is further performed only on the channel portion of the selected N-type MOS transistor so that it is lower than the power supply voltage V _DD. A threshold voltage of about 4 V in a high enhancement state (higher threshold voltage)
Is set.

Hereinafter, a method for reading information from the nonvolatile semiconductor memory device 10 will be described with reference to FIG.

FIG. 6 is a diagram showing an example of a flowchart for reading information from the nonvolatile semiconductor memory device 10.

In step S1, a third voltage having the same polarity as the first voltage is applied to the unselected source lines, that is, unselected source lines. Note that the first voltage is a voltage applied to the selected bit line in step S3 described later.

In step S2, a source line corresponding to an arbitrary memory cell to be selected is selected. In particular,
A voltage substantially equal to the potential of the semiconductor substrate is applied to the selected source line.

In step S3, a bit line corresponding to the arbitrary memory cell is selected. Specifically, a first voltage having a polarity that is reversely biased with respect to the semiconductor substrate is applied to the selected bit line.

In step S4, a word line corresponding to the arbitrary memory cell is selected. Specifically, a second voltage having the same polarity as the first voltage is applied to the selected word line.

According to the above-described steps, when information is read from a selected memory cell, if the unselected memory cell has a lower threshold voltage, the non-selected memory cell having a lower threshold voltage Is a depletion type, it can be an enhancement type due to a back bias effect. Therefore, it is possible to suppress a leak current flowing from the non-selected memory cell to the bit line connected to the selected memory cell.

When the selected memory cell is in the erased state, that is, when the selected memory cell has the lower threshold voltage, the selected memory cell can be set to the depletion state. . Therefore, the potential difference between the voltage applied to the gate of the selected memory cell and the threshold voltage increases, and the amount of current read from the selected memory cell can be increased.

In this embodiment, the processing does not need to be executed in the order of steps S1 to S4. That is, even if Steps S1 to S4 are executed in an arbitrary order, the present embodiment has the above-described effects.

Further, the first voltage applied to the selected bit line and the third voltage applied to the non-selected source line may be substantially the same.

Hereinafter, a specific method for reading information from the memory cell M24 of the nonvolatile semiconductor memory device 10 will be described.

In FIG. 1 and FIG. 2, when the memory cell M24 surrounded by a broken line is selected, the semiconductor substrate potential is set to the ground potential (0 V), the word line WL2 is set to 3 V (second voltage), and the bit The line BL4 is set to 1 V (first voltage). The other word lines WL1, WL3, WL4 and the other bit lines BL1, BL2, BL3 are set to 0V, and the source line SL2 is set to 0V. Further, another source line SL
1, SL3 and SL4 are set to 1V (third voltage). Although not shown, the potential of the well to which the memory cell belongs is set to 0V. If the memory cell M24 is in the erased state, the threshold voltage is about -1 V, so that the memory cell M24 is turned on, and a memory cell read current flows to the bit line BL4. In this case, the read current of the memory cell M24 is larger than that in the case where the threshold voltage of the memory cell included in the conventional nonvolatile semiconductor memory device is 0.5V.

On the other hand, if the memory cell M24 is in a write state, the threshold voltage of the memory cell M24 is about 4 V, so that the memory cell M24 is turned off and no memory cell read current flows to the bit line BL4. The read operation is performed by the above-described current amount being detected by the sense amplifier.

In the first embodiment of the present invention, the non-selected memory cells M14, M34 and M44 connected to the same bit line BL4 as the selected memory cell M24 are formed by utilizing the back bias effect. The threshold voltage can be set to about 0.5V or more. That is, by applying a voltage of 1 V to the source lines SL1, SL3, and SL4 of the non-selected memory cells, even if the threshold voltage of the non-selected memory cells is -1 V, the non-selected memory cells may be non-selected due to the back bias effect. The threshold value of the selected memory cell can be set to about 0.5 V or more. Therefore, the current flowing from the non-selected memory cells can be suppressed to almost zero.

Unselected memory cells M14, M34, M4
4 has a lower threshold voltage, the lower threshold voltage of the non-selected memory cells M14, M34, M44 can be made enhancement type by the back bias effect during the read operation, and the selected memory cell The leak current flowing from the other unselected memory cells M14, M34, M44 connected to the bit line BL4 to which M24 is connected can be suppressed.

When the selected memory cell is in the erased state, the threshold voltage (lower threshold voltage) of the memory cell in the erased state can be set to the depletion state. For this reason, the read current amount in the ON state in the selected memory cell increases. As a result, a sufficient ON-state memory cell read current can be ensured even at a low voltage, and the nonvolatile semiconductor memory device according to the first embodiment enables high-speed read at a low voltage.

As described above, according to this embodiment,
By applying a positive voltage that becomes a reverse bias to the semiconductor substrate to the source line connected to the unselected memory cell,
The threshold voltage of the memory cell in the erased state, that is, the lower threshold voltage can be set to the depletion state.
For this reason, even if the voltage applied to the gate of the selected memory cell is a low voltage, the read current amount of the memory cell in the ON state can be sufficiently secured. As a result, even if the voltage applied to the gate of the selected memory cell is a low voltage, it is possible to read information from the memory cell at high speed.

In the first embodiment, the voltage applied to the bit line selected at the time of reading and the voltage applied to the non-selected source line are the same, but even if these voltages are different. Good. However, when the voltage of the unselected source line is lower than the voltage applied to the selected bit line, the back bias effect is small, and in the opposite case, the current flows from the source line. For,
The effect of the present invention is reduced.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 7 is a schematic diagram of a memory cell array configuration of a nonvolatile semiconductor memory device 20 according to the second embodiment of the present invention. FIG. 8 shows the nonvolatile semiconductor memory device 20.
FIG. 3 is a schematic plan view showing a pattern layout of FIG. That is, FIG. 8 illustrates the nonvolatile semiconductor memory device 20 shown in FIG.
1 shows an example of the array structure. FIG. 9 is similar to FIG.
FIG. 10 is a diagram showing a cross section when the nonvolatile semiconductor memory device 20 shown in FIG.
13 is a diagram showing a cross section when the nonvolatile semiconductor memory device 20 shown in FIG. In FIG. 10, when the cross section is viewed from the direction D, the bit line BL7 is not actually seen, but is shown so that it is easy to understand that the bit line BL7 is connected to the bit line contact 6b. .

The non-volatile semiconductor storage device 20 includes memory cells M11 to M64 formed of MOS transistors, word lines WL1 to WL6, source lines SL1 to SL4, and bit lines BL1 to BL8.

Further, the nonvolatile semiconductor memory device 20 comprises:
An element isolation region 5 and bit line contacts 6a and 6b are provided. The element isolation region 5 is formed by LOCOS or STI, but may be formed by another method. Note that the nonvolatile semiconductor memory device 20 has a memory cell array structure called a NOR type because a plurality of memory cells are connected in parallel to bit lines.

In the nonvolatile semiconductor memory device 20, the gate of the memory cell M14 is connected to the word line WL1, the source of the memory cell M14 is connected to the source line SL1, the drain of the memory cell M14 is connected to the bit line BL8, The gate of the memory cell M24 is connected to the word line WL2, the source of the memory cell M24 is connected to the source line SL2, and the drain of the memory cell M24 is connected to the bit line BL8.
It is connected to the.

The gate of the memory cell M34 is connected to the word line WL3, the source of the memory cell M34 is connected to the source line SL2, the drain of the memory cell M34 is connected to the bit line BL7, and the gate of the memory cell M44 is connected. The source of the memory cell M44 is connected to the source line SL3, and the drain of the memory cell M44 is connected to the bit line BL7.

Further, the gate of memory cell M54 is connected to word line WL5, the source of memory cell M54 is connected to source line SL3, the drain of memory cell M54 is connected to bit line BL8, and the gate of memory cell M64 is connected. The memory cell M64 is connected to the word line WL6, the source of the memory cell M64 is connected to the source line SL4, and the drain of the memory cell M64 is connected to the bit line BL8.

That is, the bit lines BL7 and BL8 correspond to the column to which the memory cells M14 to M64 belong. In other words, a first set of memory cells is connected to a first bit line and in a column direction, ie, in a direction in which the first bit line extends,
A second set of memory cells adjacent to the first set of memory cells is connected to a second bit line. In this embodiment, a certain set includes two memory cells, and the two memory cells included in the certain set share one bit line contact.

For example, memory cell M14 and memory cell M24 form a first set, and these memory cells M14, M14,
M24 shares the bit line contact 6a, and the first set of memory cells M14 and M24 are connected to the first bit line BL8 via the bit line contact 6a. Also,
The memory cell M34 and the memory cell M44 form a second set, and the second set is adjacent to the first set in the column direction. Those memory cells M34 and M44 are connected to the bit line contact 6
b, the second set of memory cells M34 and M44 is connected to the second bit line BL7 via the bit line contact 6b.

The method of writing information to the nonvolatile semiconductor memory device 20 and the method of erasing information are described in the nonvolatile semiconductor memory device 1.
Same as 0.

Hereinafter, a method of reading information from nonvolatile semiconductor memory device 20 will be described with reference to FIG.

FIG. 11 is a diagram showing an example of a flowchart for reading information from the nonvolatile semiconductor memory device 20.

In step S11, a third voltage having the same polarity as the first voltage is applied to the unselected source lines, that is, unselected source lines. Note that the first voltage is
This is the voltage applied to the bit line selected in step S13 described later.

In step S12, a source line corresponding to an arbitrary memory cell to be selected is selected. Specifically, a voltage substantially equal to the potential of the semiconductor substrate is applied to the selected source line.

In step S13, a bit line corresponding to the arbitrary memory cell is selected. Specifically, a first voltage having a polarity that is reversely biased with respect to the semiconductor substrate is applied to the selected bit line.

In step S14, a word line corresponding to the arbitrary memory cell is selected. Specifically, a second voltage having the same polarity as the first voltage is applied to the selected word line.

According to the above-described steps, when information is read from a selected memory cell, if the non-selected memory cell has a lower threshold voltage, the non-selected memory cell having a lower threshold voltage Can be of the enhancement type. Therefore, it is possible to suppress a leak current flowing from the non-selected memory cell to the bit line connected to the selected memory cell.

When the selected memory cell is in the erased state, that is, when the selected memory cell has the lower threshold voltage, the selected memory cell can be set to the depletion state. . Therefore, the potential difference between the voltage applied to the gate of the selected memory cell and the threshold voltage increases, and the amount of current read from the selected memory cell can be increased.

In this embodiment, the processing does not need to be executed in the order of steps S11 to S14. That is, even if steps S11 to S14 are executed in an arbitrary order, the present embodiment has the above-described effects.

Further, the first voltage applied to the selected bit line and the third voltage applied to the non-selected source line may be substantially the same.

Hereinafter, a specific method for reading information from the memory cell M24 of the nonvolatile semiconductor memory device 20 will be described.

In FIG. 7 and FIG. 8, when the memory cell M24 surrounded by a broken line is selected, the semiconductor substrate potential is set to the ground potential (0 V), the word line WL2 is set to 3 V (second voltage), and the bit The line BL8 is set to 1 V (first voltage). Also, the other word lines WL1, WL3 to WL6 and the other bit lines BL1 to BL7 are set to 0V or OPEN state, and the source line SL2 is set to 0V. Further, the other source lines SL1, SL3, SL4 are set to 1V (third voltage). Although not shown, the potential of the well to which the memory cell belongs is set to 0V. If the memory cell M24
Is in the erased state, the threshold voltage is about -1 V, so that the memory cell M24 is turned on and the bit line B
A memory cell read current flows through L8. In this case, the read current of the memory cell M24 is set such that the threshold voltage of the memory cell of the conventional nonvolatile semiconductor memory device is 0.5.
V is larger than that in the case of V.

On the other hand, if the memory cell M24 is in a write state, the threshold voltage of the memory cell M24 is about 4 V, so that the memory cell M24 is turned off and no memory cell read current flows to the bit line BL8. The read operation is performed by the above-described current amount being detected by the sense amplifier.

In the second embodiment of the present invention, the non-selected memory cells M14, M54 and M64 connected to the same bit line BL8 as the selected memory cell M24 are formed by utilizing the back bias effect. The threshold voltage can be set to about 0.5V or more.

That is, the source line S of the unselected memory cell
By applying a voltage of 1 V to L1, SL3, and SL4, even if the threshold voltage of the non-selected memory cell becomes-
Even if it is 1 V, the threshold value of the unselected memory cell can be set to about 0.5 V or more due to the back bias effect. Therefore, the current flowing from the non-selected memory cells can be suppressed to almost zero.

When the selected memory cell is in the erased state, the threshold voltage (lower threshold voltage) of the memory cell in the erased state can be set to the depletion state. For this reason, the read current amount in the ON state in the selected memory cell increases. As a result, a sufficient ON-state memory cell read current can be ensured even at a low voltage, and the nonvolatile semiconductor memory device according to the second embodiment enables high-speed read at a low voltage.

In the second embodiment, the voltage applied to the bit line selected at the time of reading and the voltage applied to the non-selected source line are the same voltage. However, even if these voltages are different voltages, Good. (Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 12 is a schematic diagram of a memory cell array configuration of a nonvolatile semiconductor memory device 30 according to the third embodiment of the present invention. FIG. 13 is a schematic plan view showing a pattern layout of the nonvolatile semiconductor memory device 30.
That is, FIG. 13 illustrates an example of an array structure of the nonvolatile semiconductor memory device 30 illustrated in FIG. FIG.
4 is a diagram showing a cross section when the nonvolatile semiconductor memory device 30 shown in FIG. 13 is cut along a line EE.

The nonvolatile semiconductor memory device 30 includes memory cells M11 to M44 formed of MOS transistors, word lines WL1 to WL4, source lines SL1 to SL4, and bit lines BL1 to BL4.

Further, the nonvolatile semiconductor memory device 30
Element isolation regions 5A, 5B, bit line contacts 6a, 6
b, and well lines WEL1 to WEL4.
The element isolation regions 5A and 5B are formed by LOCOS or STI, but may be formed by another method.

As shown in FIG. 12, in the nonvolatile semiconductor memory device 30, the well line WEL1 is connected to the memory cells in the row to which the memory cells M11 to M14 belong, and the memory cell M
Well lines WEL are added to the memory cells of the row to which
2 is connected, the well line WEL3 is connected to the memory cell of the row to which the memory cells M31 to M34 belong, and the well line WE is connected to the memory cell of the row to which the memory cells M41 to M44 belong.
L4 is connected. That is, a memory cell in a certain row is connected to a well line corresponding to the certain row. The well lines are independent for each row.

In the nonvolatile semiconductor memory device 30, as shown in FIG. 12, a source line SL1 is connected to the sources of the memory cells in the row to which the memory cells M11 to M14 belong.
The source line SL2 is connected to the sources of the memory cells in the row to which the memory cells M21 to M24 belong, and the memory cells M31 to M24 are connected.
The source line SL is connected to the source of the memory cell in the row to which M34 belongs.
3 is connected, and the source line SL4 is connected to the source of the memory cell in the row to which the memory cells M41 to M44 belong. That is, in the nonvolatile semiconductor memory device 30, memory cells in a certain row do not share a source line with memory cells in another row.

A plurality of memory cells connected to the same word line and the same source line share one well line.

Hereinafter, the nonvolatile semiconductor memory device 3 of the present invention will be described.
The method of reading 0 will be described with reference to FIG.

Memory cell M14 surrounded by a broken line in FIG.
Is selected, the semiconductor substrate potential is set to the ground potential (0 V).
The word line WL1 is set at 3V (second voltage), and the bit line BL4 is set at 1V (first voltage). Well line W
EL1 is set to 0 V, and the other word lines WL2, WL3, WL
4, the source lines SL1 to SL4 are set to 0V, the bit lines BL1 to BL3 are set to 0V, and the other well lines WEL are set.
2 to WEL4 are set to -3 V (third voltage). Note that at least the well lines WEL1 to WEL4 are controlled by the decoder.

In the first and second embodiments described above, the back bias effect using the source line allows
The threshold voltage of the unselected memory cells could be increased. Even if an unselected memory cell has a lower threshold voltage, for example, -1 V, the lower threshold voltage can be set to about 0.5 V or more due to the back bias effect. On the other hand, in the third embodiment, a similar effect can be obtained by using a well line.

As described above, according to the third embodiment, by applying a negative voltage to the well line of a non-selected memory cell, that is, a voltage which becomes a forward bias with respect to the semiconductor substrate, Can be increased. That is, when an unselected memory cell is in an erased state, the threshold voltage of that memory cell can be set to a depletion state.

As a result, even when the voltage applied to the gate of the memory cell in the nonvolatile semiconductor memory device 30 is low, a sufficient amount of read current for reading information from the memory cell can be ensured.

Although the first to third embodiments have been described using the mask ROM, the floating gate electrode type, which is a nonvolatile semiconductor memory device that stores data using two different threshold voltages, is used. The present invention can be applied to a nonvolatile semiconductor memory device. In this case, only the memory cells shown in FIGS. 1, 7, and 12 are replaced with floating gate electrode type memory cells.

In the first to third embodiments, the threshold voltage in the erased state is set to the depletion state. However, it is not necessary to set the threshold voltage to the depletion state. In a conventional nonvolatile semiconductor memory device, it is necessary to set a threshold voltage in an erased state to about 0.5 V in order to suppress a leak current of an unselected memory cell. However, in this embodiment, since the leak current of the unselected memory cells can be reduced, the threshold voltage in the erased state can be set lower than 0.5 V.

Depending on the application, for example, it may be desired to set the threshold voltage in the erased state of the memory cell to, for example, about 0 V without reaching the depletion state. The present invention is applied to such a case.

In the first to third embodiments, the erased state is set to the lower threshold voltage. However, the write state may be set to the lower threshold voltage.

In the first to third embodiments, the threshold voltage in the written state is equal to or higher than the power supply voltage. It may be lower than the power supply voltage.

Although the first to third embodiments have been described using an N-type MOS transistor, a P-type MOS transistor may be used.

Note that the present invention may be implemented by combining the first embodiment and the second embodiment.

According to the present invention, since the low threshold voltage state can be changed to the depletion state, the difference between the threshold voltage in the write state and the threshold voltage in the erase state can be widened. It becomes easy to cope with the problem of the variation in the threshold voltage after writing or after erasing, which is peculiar to the storage device, and the multi-valued threshold voltage.

Further, the present invention can be applied to all memories that perform a storage operation, that is, a read operation by changing a current flowing through a memory cell. Note that the mask R
In the OM, there is also a method of storing information depending on the presence or absence of a bit line contact. In such a case, the present invention can be applied by replacing the write state with an infinitely high threshold voltage.

[0124]

According to the present invention, a configuration is employed in which the voltage applied to the source line or well line of the memory cells on the same bit line can be independently controlled, and the unselected memory cells on the same bit line can be controlled. Since the threshold voltage is controlled by applying a threshold voltage to the source line or well line and the threshold voltage is raised by the back bias effect, the lower threshold voltage can be set to the depletion state, and even at low voltage Since a memory cell read current amount can be secured, a nonvolatile semiconductor memory device that can perform a low-voltage high-speed read operation can be realized.

When at least a part of the lower threshold voltage state of the memory cell is in a depletion state,
The read current in that state can be increased,
The reading speed under low voltage can be further increased.

When the first voltage applied to the bit line and the third voltage applied to the unselected source lines are set to substantially the same voltage, the back bias effect is large and no current flows from the source line. Therefore, the highest speed reading performance can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a memory cell array configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing a pattern layout of the nonvolatile semiconductor memory device 10;

3 is a diagram showing a cross section when the nonvolatile semiconductor memory device 10 shown in FIG. 2 is cut along line AA.

4 is a diagram showing a cross section when the nonvolatile semiconductor memory device 10 shown in FIG. 2 is cut along a line BB.

FIG. 5 is a threshold voltage distribution diagram (a plurality of memory cells) of a memory cell in the nonvolatile semiconductor memory device 10;

FIG. 6 is a diagram showing an example of a flowchart for reading information from the nonvolatile semiconductor memory device 10;

FIG. 7 is a schematic diagram of a memory cell array configuration of a nonvolatile semiconductor memory device 20 according to a second embodiment of the present invention.

FIG. 8 is a schematic plan view showing a pattern layout of the nonvolatile semiconductor memory device 20.

9 is a diagram showing a cross section when the nonvolatile semiconductor memory device 20 shown in FIG. 8 is cut along line CC.

FIG. 10 is a diagram showing a cross section when the nonvolatile semiconductor memory device 20 shown in FIG. 8 is cut along a line DD.

FIG. 11 is a diagram showing an example of a flowchart for reading information from the nonvolatile semiconductor memory device 20.

FIG. 12 is a schematic diagram of a memory cell array configuration of a nonvolatile semiconductor memory device 30 according to a third embodiment of the present invention.

FIG. 13 is a schematic plan view showing a pattern layout of the nonvolatile semiconductor memory device 30.

14 is a diagram showing a cross section when the nonvolatile semiconductor memory device 30 shown in FIG. 13 is cut along a line EE.

FIG. 15 is a schematic diagram showing a memory cell array configuration of a conventional nonvolatile semiconductor memory device 500.

FIG. 16 shows a nonvolatile semiconductor memory device 500 shown in FIG.
FIG. 3 is a schematic plan view showing a pattern layout of FIG.

FIG. 17 is a threshold voltage distribution diagram (a plurality of memory cells) of a memory cell in the nonvolatile semiconductor memory device 500;

[Explanation of symbols]

 M14 to M44 Memory cells WL1 to WL4 Word lines SL1 to SL4 Source lines BL1 to BL4 Bit lines 5, 5X Element isolation regions 6a, 6b Bit line contacts

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (12)

[Claims] A plurality of memory cells arranged in a matrix on a semiconductor substrate; a plurality of word lines extending in a row direction; a plurality of source lines extending in the row direction; A plurality of memory cells belonging to a certain row, the plurality of memory cells belonging to a certain row being connected to a first source line of the plurality of the source lines, and A plurality of memory cells belonging to the non-volatile semiconductor memory are connected to a second source line of the plurality of source lines, and the first source line is electrically independent of the second source line. apparatus. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said first source line is insulated from said second source line by an element isolation region. 3. A plurality of memory cells arranged in a matrix on a semiconductor substrate; a plurality of word lines extending in a row direction; a plurality of source lines extending in the row direction; A non-volatile semiconductor memory device including a bit line, wherein a first set of a plurality of memory cells belonging to a certain column includes:
A second set of the plurality of memory cells belonging to the certain column is connected to a first bit line of the plurality of bit lines, and a second set of the plurality of memory cells belonging to the certain column is connected to a second bit line of the plurality of bit lines. The nonvolatile semiconductor memory device, wherein the first bit line is electrically independent of the second bit line. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said first set is adjacent to said second set in said column direction. 5. The nonvolatile semiconductor memory device according to claim 1, wherein each of said plurality of memory cells is a MOS transistor having a gate electrode, a gate insulating film, a drain region and a source region. . 6. The memory cell according to claim 1, wherein each of the plurality of memory cells is a floating gate electrode type MOS transistor having a control gate electrode, a floating gate electrode, a drain region and a source region. Nonvolatile semiconductor memory device. 7. The nonvolatile semiconductor memory device according to claim 1, wherein a memory cell having a lower threshold voltage among said plurality of memory cells is in a depletion state. 8. The non-volatile semiconductor storage device includes a plurality of first conductivity type wells extending in the row direction, and one of the plurality of memory cells is one of the plurality of first conductivity type wells. 3. The MOS transistor according to claim 1, further comprising a MOS transistor having a gate electrode, a gate insulating film, a drain region, and a source region thereon, wherein each of the plurality of first conductivity type wells is electrically independent. 4. Non-volatile semiconductor storage device. 9. The non-volatile semiconductor storage device includes a plurality of first conductivity type wells extending in the row direction, and one of the plurality of memory cells is one of the plurality of first conductivity type wells. On top, the control gate electrode, floating gate electrode,
3. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a MOS transistor having a gate insulating film, a drain region, and a source region, and each of the plurality of first conductivity type wells is electrically independent. 4. 10. A method for driving a nonvolatile semiconductor memory device for reading information stored in a memory cell selected from the plurality of memory cells, wherein a bit line corresponding to the selected memory cell includes: Applying a first voltage having a reverse bias to the semiconductor substrate; and applying a second voltage having the same polarity as the first voltage to a word line corresponding to the selected memory cell. Applying a third voltage having the same polarity as the first voltage to a source line corresponding to a memory cell other than the selected memory cell; and applying a third voltage having the same polarity as the first voltage to a source line corresponding to the selected memory cell. 5. The method of driving a nonvolatile semiconductor memory device according to claim 1, further comprising: applying a potential of said semiconductor substrate. 11. The method according to claim 10, wherein the first voltage and the third voltage are substantially the same voltage. 12. A method for driving a nonvolatile semiconductor memory device for reading information stored in a memory cell selected from the plurality of memory cells, wherein: a bit line corresponding to the selected memory cell includes: Applying a first voltage having a reverse bias to the semiconductor substrate; and applying a second voltage having the same polarity as the first voltage to a word line corresponding to the selected memory cell. Applying a third voltage having a polarity opposite to the first voltage to a well of the first conductivity type to which the selected memory cell does not belong; 10. The method of driving a nonvolatile semiconductor memory device according to claim 8, further comprising a step of applying a ground potential to a well of one conductivity type.