JPH11233511A - Improved passivation process for silicon devices, in particular flash eeprom memories - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an improved process for passivation of silicon electron devices. SOLUTION: The process is an improved process for passivation of silicon devices by depositing thereon a protective overcoat consisting of three layers; the first layer contacting the device surface is made of silicon oxy-nitride deposited by a plasma-enhanced chemical vapor deposition(PECVD) process using silane as the reactant gas, the second layer is made of silicon oxide deposited by a chemical vapor deposition process using tetraethylorthosilicate (TEOS) as the reactant gas, and the third layer is made of silicon oxy-nitride deposited by a plasma-enhanced chemical vapor deposition(PECVD) process using silane as the reactant gas, wherein thickness lies between 2500A and 3500A for the first layer, 5000A and 15000A for the second layer, and 4500A and 5500A for the third layer, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to silicon electronic devices, and more particularly, to an improved process for passivating electrically programmable fast access non-volatile memories known as flash EPROMs. In particular, the invention provides that a three-layer protective overcoat deposited on the surface of the device forms an effective chemical, physical and mechanical barrier and provides good planarity of the surface of the device, The device packaging process is less important with respect to device reliability.

[0002]

2. Description of the Related Art The manufacture of semiconductor devices involves:
It is known that the various elements of a manufactured device include a chemical process consisting of a series of steps that are made sequentially. The chemical process ends with passivating the device surface and packaging the device.

[0003] The passivation process provides for the deposition of a protective overcoat, also known as "PO", on the device surface, which acts as a chemical, physical, and mechanical barrier and diffuses any contaminants. And protects the device from moisture and mechanical stresses experienced by the device during and during the next device packaging process.

[0004] By Neal R. Mielke, "New EPR
In particular, two metallization levels are provided as disclosed in "OM Data Loss Mechanism", "Non-Volatile Semiconductor Memory: Technology, Design, and Applications", New York, IEEE, Inc., Edited by Chemming Hu (1991). For flash EPROM silicon devices, the passivation process to produce high quality devices provides for the deposition of a multi-layer protective overcoat.

The quality of flash EPROM memory is 1
It is determined by providing one or more specifically defined parameters. More specifically, Flash EP
An important parameter for evaluating the quality of a ROM memory is "data retention loss", known as DRL.
The DRL is a memory device that is subjected to severely stressed processing, such as high temperature processing.
Given by testing the ability to retain test data. Comparison of the charge stored on the memory device before and after such processing provides a measurement of the device DRL. A lower value of DRL indicates a longer lifetime of the stored charge and, therefore, better quality of the flash EPROM memory device.

As mentioned above, a passivation process that provides for the deposition of a multilayer protective overcoat allows good results to be obtained for DRL. In particular, for flash EPROM memory devices, an effective passivation process is a three-layer protective overcoat: a first layer of 4000 Angstrom thick silicon oxynitride, 10,000
Providing a deposition of a second layer of Å-thick silicon oxide and a third layer of 4000 Å-thick silicon oxynitride. The deactivation process comprises:
It was disclosed by S. Mistra, K. Hewes, and S. Ganturi in "Texas Instruments Technical Journal", Vol. 14, No. 1 Jan-Feb (1997).

[0007] Silicon oxynitride is chosen as the first layer because of its properties which are intermediate between those of pure silicon oxide (SiO ₂ ) and those of pure silicon nitride (Si ₃ N ₄ ).
In particular, oxynitrides have good passivation properties for protection from external factors and resistance to moisture, similar to pure nitrides, and similar to pure oxides, It is transparent to ultraviolet (UV) light used in the deep ultraviolet range (200-300 nm) for device erasure.

[0008] In addition, oxynitrides that are in direct contact with the final metallization level provide mobile ions with the higher potential barrier provided by pure oxides. These characteristics are
Important for minimizing DRL. A further advantage obtained by using oxynitrides compared to pure nitrides is that the concentration of free hydrogen atoms in the film is lower. In fact, in oxynitride films, hydrogen atoms combine with nitrogen, whereas in pure nitride films, they combine with silicon. As is known, the binding energy between nitrogen and hydrogen is equal to 81 kcal / mol, 71.5 kcal / mol
Is significantly higher than the binding energy between silicon and hydrogen equal to, so that the hydrogen is more strongly bonded, thus resulting in a lower concentration of hydrogen atoms in the oxynitride film compared to a pure nitride film. Therefore, "Proc. 18 ^th Int. Rel. Phys. Symp." By RC Sun et al. (1980
April), and KG Steiner, CS Pai, RM Stanton,
And VW Conference by CW Wilkins
3 ", ISMIC-102 / 93/0078 (8-9 June 1993), the use of oxynitrides further raises any reliability problems due to the effects of so-called hot carriers. Can be difficult.

The oxynitride of the first layer is deposited at low temperature and pressure by a plasma enhanced chemical vapor deposition (PECVD) process using silane as a reactive gas. The term "low temperature" also means below and below the temperature used for the dopant diffusion of the silicon substrate. The term "low pressure" also means below, not more than 33 Pa (Pascal). The layer obtained by such deposition is poorly conformal, i.e. it does not follow the shape of the base surface,
The sidewall coverage present in the waveform topography of the device is reduced. The thickness that can theoretically be obtained on the side wall is
About 30% thick of the layer deposited on the upper horizontal surface.

The requirement that the sidewall coating be made of sufficient thickness is to increase the moisture resistance and to prevent the diffusion of contaminants in the metallization, which can cause severe reliability problems for the device. With the goal. When the sidewall coating is thin, it is susceptible to cracks, which can further increase the reliability problem.

Thus, the conformality of the protective overcoat (co
Plasma enhanced using tetraethyl orthosilicate, or "TEOS", as the reaction gas at low temperatures and pressures to ensure proper filling of the corrugated topography of the device and proper sidewall coverage to improve the nformity The second layer is composed of silicon oxide deposited by a chemical vapor deposition (PECVD) process. The thickness theoretically obtained on the side wall by the deposition is:
About 50% thick of the layer deposited on the upper horizontal surface.

The third layer of the protective overcoat is composed of silicon oxynitride deposited at low temperature and low pressure by a plasma enhanced chemical vapor deposition (PECVD) process using silane as a reactive gas. The third layer is a physical barrier to moisture and mechanical stress due to the subsequent packaging process. Flash EP
The aforementioned passivation process for ROM memory devices involves:
It has been found that it has no negative impact on the functionality and quality of the device at the wafer level.

A subsequent packaging process for the device provides for the manufacture of a casing or package, usually in plastic, to house the device. The package can be of several types. In particular, a plastic lead chip carrier, or "PLC
Packages known as "C" are very inexpensive and are widely manufactured for this reason.

However, when the PLCC package is manufactured during the flash EPROM memory device packaging process, the passivation process described above causes defects mainly related to protective overcoat integrity and moisture resistance, This significantly reduces device reliability. Defects are revealed in reliability tests where the device is exposed to very aggressive temperature, pressure, humidity, and bias conditions, and during which time is required for the device to become defective. Thus, the above-described passivation process for flash EPROM devices significantly reduces device quality at the package level for PLCC packages.

This problem arises because of the interaction of the molding compound of the PLCC package with the device protective overcoat in the device surface area where there are deep recesses with a large height to width ratio for waveform topography. . The passivation process described above does not achieve proper filling of the deep recesses and does not reduce device waveform topography irregularities.

[0016] For this reason, the presence of sharp topography corners and sidewalls, especially in regions where there is no underlying metallization level, is due to the first silicon oxynitride layer forming the first layer of the protective overcoat. During deposition, creating a bump in the thickness of the deposited film corresponding to the top edge of said sidewall;
Thus, the aforementioned uneven shape of the thickness causes so-called "cusping" or "bread loafing".

Subsequent deposition of silicon oxide is more conformal than the previous one, but the irregularities in the thickness increase the value of the height-to-width ratio of the topographical depressions, thereby smoothing the device surface. Cannot be transformed. Thus, the deposition of silicon oxide creates outwardly open or closed tears and holes in the protective overcoat. In addition, PECV, the deposition process used
The nature of D, which utilizes highly reactive species that are trapped and expanding in holes, increases the generation of said holes.

The tears and holes in the protective overcoat are the areas where photoresist residues used in subsequent photolithography processes to open the connection pads are trapped, and the standard photoresist
It is not completely removed by the ashing process.

Further, a mold compound used for manufacturing a PLCC package is also trapped in the hole. The final process, including the packaging process, where the device is subjected to high mechanical and thermal stresses, causes uneven expansion of the material that causes the protective overcoat to crack, degrading the device quality and therefore reliability testing fall into. The holes, which can be interconnected via a tunnel, are revealed by mechanically removing the cap of the device PLCC package,
It becomes apparent that mold compound residues are trapped only in the areas of the device topography where sharp corners and sidewalls are present.

[0020]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method as described above for smoothing out irregularities in a topography and without reducing the functionality, quality and reliability of the device. It is to propose a passivation process adapted to ensure proper filling of the recesses of the waveform topography of the device, in particular of the flash EPROM memory device, and of the sidewalls.

It is a further object of the present invention to perform the low cost and reliable passivation process without changing the device design and by using standard equipment and procedures.

A specific subject of the present invention is an improved process for passivating silicon electronic devices based on the deposition of a three-layer protective overcoat, wherein the first layer in contact with the device surface is a silane. Using P as a reaction gas
The second layer is composed of silicon oxynitride deposited by an ECVD process, and the second layer is composed of silicon oxide provided by a chemical vapor deposition process using tetraethyl orthosilicate (TEOS) as a reaction gas.
Is composed of silicon oxynitride deposited by a PECVD process using silane as a reaction gas,
The passivation process may be such that the first layer of silicon oxynitride has a thickness between 2500 and 3500 angstroms and the second layer of silicon oxide has a thickness between 5000 and 15000 angstroms. Deposited by a chemical vapor deposition process (APCVD) at a pressure near atmospheric pressure, wherein the third layer of silicon oxynitride has a thickness between 4500 and 5500 angstroms.

Preferably, in accordance with the present invention, the near atmospheric pressure at which the chemical vapor deposition (APCVD) of the second layer is performed is between 33 Pa and 250 Pa;
More preferably, it is equal to Pa.

According to the present invention, the first silicon oxynitride
Has a thickness equal to 3000 angstroms, said second layer of silicon oxide has a thickness equal to 10000 angstroms, and a third layer of silicon oxynitride has a thickness equal to 5000 angstroms. Is preferred.

[0025] A further subject of the invention is a silicon layer with multi-level metallization, preferably with two-level metallization.
A process for manufacturing a flash EPROM memory device, wherein the passivation process with a three-layer protective overcoat is performed, preferably including a device packaging process for a PLCC type package.

[0026]

The invention will now be described, by way of example and not by way of limitation, according to preferred embodiments. The passivation process according to the present invention also maintains the aforementioned advantages,
A three-layer protective overcoat deposition of a first layer of oxynitride, a second layer of silicon oxide, and a third layer of silicon oxynitride is provided.

The first layer of silicon oxynitride is also deposited at low temperature and pressure by a PECVD process using silane as a reactive gas. The bread loafing effect is strongly related to the thickness of the first layer and is exacerbated by increasing thickness. To reduce the bread loafing effect, the thickness of the first layer is thinner than achieved in the prior art and equals 3000 Å in a preferred embodiment of the present invention. Such a deposition step is adapted to maintain the thickness of the sidewall coating between 1000 and 1500 angstroms, which is sufficient to ensure protection from moisture and prevent contaminant diffusion.

In a preferred embodiment, the thickness is 1000
The oxide of the second layer, equivalent to 0 Angstroms, may be deposited in a sub-atmospheric or atmospheric pressure chemical vapor deposition process ("Atmospheric Pressure Chemical Vapor Depositi").
on ": APCVD), deposited using TEOS as the reactive gas. The value of the pressure at which the APCVD process is performed is between 33 Pa and 250 Pa, and in a preferred embodiment equals 125 Pa. Said deposition, which is not carried out at low pressure, makes the oxide layer very effective for filling surface depressions and covering the sidewalls, since it has about 100% conformality.

The third layer of oxynitride is also deposited at low temperature and low pressure by a PECVD process using silane as a reactive gas. Such deposition occurs on surfaces that have been smoothed by a second prior deposition of highly conformal silicon oxide. The third layer of silicon oxynitride has a thickness of 5000 Angstroms in a preferred embodiment and is a physical barrier to moisture and mechanical stress due to the subsequent packaging process.

[0030] The passivation process according to the present invention is used to remove the recesses formed in the protective overcoat in the central region of the device.
90%, and 60% of those formed in the peripheral area, thereby significantly reducing device reliability issues, especially with PLCC packages.

The passivation process according to the present invention has been described with particular reference to the process of manufacturing a flash EPROM memory device having a two-level metallization and PLCC type package. However, without departing from the relevant scope of the invention, different devices and / or levels of metallization other than two and / or in the process of manufacturing devices with a package type other than PLCC may also be used. Please understand that it is applicable.

While the foregoing description describes preferred embodiments and suggests modifications for the present invention, those skilled in the art will depart from the pertinent scope as set forth in the appended claims. It should be understood that modifications and / or variations may be made without departing from the invention.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792 (72) Inventor Andrea Gunnerra Italy Pescara, Via Chiarini, 51 (72) Inventor Sudhansh Misla Florida, United States of America Orlando, Number 1623, Fairway Island Drive 13803

Claims (8)

[Claims] An improved process for passivating a silicon electronic device by depositing a three-layer protective overcoat thereon, wherein the first layer in contact with the device surface comprises reacting silane with a reactive gas. Enhanced Chemical Vapor Deposition (PE)
The second layer is made of silicon oxynitride deposited by a CVD) process, and the second layer is tetraethylorthosilicate (TEO).
S) is composed of silicon oxide provided by a chemical vapor deposition process using reactive gas as a reaction gas, and the third layer is formed of a plasma using silicon silane as a reaction gas.
The silicon oxynitride deposited by an enhanced chemical vapor deposition (PECVD) process, wherein the passivation process comprises the first of silicon oxynitride.
Has a thickness of between 2500 and 3500 Angstroms and the second layer of silicon oxide has a thickness of between 5000 and 15000 Angstroms and has a chemical vapor deposition process (APCVD) at near atmospheric pressure. ) Wherein said third layer of silicon oxynitride has a thickness between 4500 and 5500 Å. 2. The passivation process according to claim 1, wherein the chemical vapor deposition (APCV) for the second layer is performed.
D) The pressure close to the atmospheric pressure at which the process is performed is 33
Passivation process that is between Pa and 250 Pa. 3. The passivation process according to claim 2, wherein the chemical vapor deposition (APCV) for the second layer is performed.
D) The pressure close to the atmospheric pressure at which the process is performed is 12
Passivation process equal to 5 Pa. 4. A passivation process according to claim 1, wherein said first layer of silicon oxynitride has a thickness equal to 3000 Å and said passivation process comprises The second layer has a thickness equal to 10,000 Angstroms, and the third layer of silicon oxynitride is
Passivation process with a thickness equal to 5000 Angstroms. 5. A process for fabricating a silicon fast access electrically programmable non-volatile memory or flash EPROM device including multi-level metallization (metallization), comprising a device packaging process, wherein the process comprises: A process wherein a passivation process according to any of paragraphs 1-4 is provided. 6. A flash EPROM according to claim 5,
A process for manufacturing a device, wherein the device provides two levels of metallization. 7. A flash EP according to claim 5 or claim 6.
A process for manufacturing a ROM device, wherein a PLCC type package is manufactured in the device packaging process. 8. A process for passivating a silicon electrical device and manufacturing a silicon flash EPROM device substantially as described and described, respectively, according to the preceding claims 1-4 or 5-7. process.