JPH11222679A - Cvd apparatus and production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the corrosion of metallic parts and to prevent the degradation in product yield by coating the surfaces of the metallic parts of a CVD apparatus for executing gas cleaning of a reactor and piping with a halogen based gas with a metal compd. of low standard forming free energy to a specific thickness. SOLUTION: A plurality of wafers 1 placed on a susceptor 22 are arranged in the reactor section having an outer tube 21a for vacuum discharge and an inner tube 21b for gaseous raw material supply and are heated to a prescribed temp. by heaters 23, by which the deposition of Poly-Si films, etc., is executed. The halogen based gas, such as ClF3 , HF or NF3 , is supplied at need to this CVD apparatus to execute the gas cleaning of the reactor and the piping. At this time, the surfaces of the metallic parts, such as flanges 24a, 24b of the tubes and susceptor supplying plate 25, are coated with the metal compd. of NiF2 , etc., of <=600 kJ/mol in the standard forming free energy and 1 to 5 μm in thickness. As a result, the corrosion thereof is prevented and the contamination of the deposited films is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CVD apparatus used in a process of manufacturing a semiconductor integrated circuit and a method of manufacturing a semiconductor device using the same.

[0002]

2. Description of the Related Art As a method of forming a thin film used in a manufacturing process of a semiconductor integrated circuit, a CVD (Chemical Vapor Deposition) method is one of the generally and widely used methods. In the CVD method, a thin film is formed on a wafer by a chemical reaction of a source gas using heat or plasma. The features of the CVD method are that a thin film having high purity and excellent crystallinity can be obtained at a temperature considerably lower than the melting point of the film to be deposited, and that the thin film has good coverage on a substrate with respect to physical vapor deposition. It is in. At present, CVD, SiO ₂ , Poly-S
A thin film of i, Si ₃ N ₄ , W, WSi, TiN, Ta ₂ O ₅ or the like is formed.

The CVD apparatus includes a reactor for performing a film forming reaction, a gas supply device for supplying a raw material gas to the reactor, a gas supply pipe connecting the gas supply device and the reactor, an exhaust device for exhausting a reaction gas from the reactor, and a reactor and an exhaust gas. It is composed of an exhaust pipe connecting to the device. When the film forming reaction is performed at a constant pressure, a pressure adjusting valve is provided in the exhaust pipe.

[0004] By repeating the film forming reaction in this CVD apparatus, by-products of the film forming reaction are deposited on the inner wall of the reactor, the inner wall of the exhaust pipe or the pressure regulating valve. If the thickness of the reaction by-product exceeds a certain limit value, peeling occurs due to internal stress of the deposited film. If the fragments are carried on the wafer by the gas flow, device defects such as short-circuit and disconnection are caused on the semiconductor integrated circuit chip, and the problem that the production yield of the semiconductor chip is reduced is caused. Further, the accumulation on the wall surface of the exhaust pipe causes a problem that the exhaust pipe and the pressure adjustment valve are not able to perform normal exhaust and pressure adjustment.

[0005] In order to avoid these problems, it is necessary to remove the reaction by-products at regular time intervals. Conventionally, a CVD apparatus has been disassembled, and the deposited film has been removed by etching with a chemical solution containing various acids as a main component, followed by cleaning, drying, and assembling. This sweeping work,
For example, in the case of a vertical thermal CVD apparatus of SiO ₂ , cooling, disassembly, etching cleaning, assembly, adjustment, and film formation of the reactor are performed. This sweeping operation requires about two days, and is performed once every two to three weeks.
For this reason, the operation rate of the apparatus can be reduced by about 10
%.

To solve this problem, ClF ₃ , H
A method of removing a film-forming reaction by-product adhering to the inner wall of the chamber and the inner wall of the pipe without disassembling the apparatus by flowing a highly corrosive halogen-based gas such as F or NF ₃ has been studied.

However, as a side effect of gas cleaning, the surface of the metal component reacts with halogen or oxygen to generate a compound which easily generates particles or a compound having a high vapor pressure, and the particles are carried on the gas flow and carried on the wafer. Or the particles are scattered by evaporation and are deposited on the wafer, thereby causing a problem that particles are deposited on the wafer or metal contamination of the wafer occurs.

In order to solve these problems, Japanese Patent Laid-Open No. 5-3
Attempts have been made to increase the resistance to corrosive gases by forming a nickel passivation film on the surface of metal components as described in 02177.

[0009]

In the invention described in the above prior art, the thickness of the fluorinated passivation film of nickel is very thin, about 20 nm to about 30 nm. Therefore, when raising and lowering the reactor temperature and performing maintenance of the apparatus. There is a problem in that the parts sometimes rub against each other, the nickel passivation film on the surface of the metal parts wears, and corrosion occurs.

An object of the present invention is to reduce the temperature of the reactor even if the temperature of the reactor of the CVD apparatus is repeatedly increased and decreased and the parts are replaced.
An object of the present invention is to provide a CVD apparatus capable of preventing corrosion of a metal part of a CVD apparatus in cleaning with a halogen-based gas such as F ₃ , HF, and NF ₃ .

Another object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent a reduction in manufacturing yield due to metal contamination or generation of particles.

[0012]

In order to achieve the above object, in a CVD apparatus for performing gas cleaning, the standard free energy of formation is less than -600 kJ / mol.
In addition, the surface of the metal component is covered with a material having a thickness of 1 μm or more and 5 μm or less.

In order to achieve the above object, in a CVD apparatus for performing gas cleaning, the surface of a metal component is covered with a NiF ₂ film having a thickness of 1 μm or more and 5 μm or less.

In order to achieve the above object, the present invention uses the above-mentioned CVD apparatus in the manufacture of a semiconductor device.

Ni is the most corrosion resistant material among metals. When this Ni is exposed to a corrosive gas such as ClF ₃ , HF or NF ₃ , NiO which is an oxide, NiCl ₂ which is a chloride, or NiF ₂ which is a fluoride is produced by the action of H ₂ O present in the reaction system. Generated. Of these Ni compounds,
NiO generates black particles because it is brittle and easily peeled off. The vapor pressure of NiCl ₂ is 0.1P at about 500 ° C.
a, so that it is scattered by evaporation. On the other hand, the vapor pressure of NiF ₂ is four orders of magnitude lower than that of NiCl ₂ and forms a dense passive film.

The index of chemical stability of these Ni compounds is given by the standard free energy of formation. Standard free energy of formation of NiO is -211 kJ / mol, NiC
While the standard free energy of formation of l ₂ is −259 kJ / mol, the standard free energy of formation of NiF ₂ is −
604 kJ / mol, indicating that NiF ₂ is the most chemically stable substance. Therefore, this NiF ₂
Is formed on the surface of the metal component in advance, so that Cl
Even when exposed to corrosive gases such as F ₃ , HF, and NF ₃ , generation of particles and scattering of metal compounds can be prevented.

In a batch processing type CVD apparatus which is mainly used in a mass production line, the reactor temperature is raised to a film forming temperature before film formation, and is lowered to near room temperature after film formation. As described above, since the temperature is repeatedly increased and decreased for each film formation, friction occurs due to a difference in thermal expansion coefficient between the quartz susceptor on which the wafer is mounted and the metal susceptor support plate supporting the quartz susceptor. N
The iF ₂ film was worn and the corrosion was enhanced by gas cleaning.

Further, even when gas cleaning is performed in a mass production CVD apparatus, parts replacement work is performed periodically. Specifically, lower the reactor temperature to near room temperature,
Replacement work of the jig attached inside the reactor is performed. When replacing a part attached in contact with a metal part, the part cannot be prevented from rubbing with the metal part.

In order for the above-mentioned NiF ₂ film to withstand abrasion due to this rubbing, it is necessary to increase the thickness of the NiF ₂ film to prevent the entry of corrosive gas. It is considered that a film thickness of 1 μm or more is necessary for this purpose. On the other hand, NiF ₂
The film expands about twice in volume when Ni is fluorinated, and has internal stress of compression. This internal stress increases as the film thickness increases, and the film tends to peel off. The limit of the film thickness is considered to be about 5 μm.

Whether or not a metal compound reacts with a halogen-based gas can be known from the difference in Gibbs free energy involved in the reaction. The reaction between a metal compound and a halogen-based gas can be generally represented by the following reaction formula.

[0021]

Embedded image MeAL + XYM → MeXN + [Other Reaction Products] (1) where MeAL is an arbitrary metal compound, XYM is a halogen-based gas, MeXN is a metal halide, and a subscript L,
M and N represent real numbers. In this reaction equation, if ΔG, which is the value obtained by subtracting the sum of the Gibbs free energies of the reactants shown on the left side from the sum of the Gibbs free energies of the reaction products shown on the right side, is positive, the reaction proceeds. If there is, it turns out that the reaction does not progress. As a result of examining various substances, if the standard free energy of formation of the metal compound is lower than -600 kJ / mol,
It was found that it did not react with the halogen-based gas. As a known example, the standard free energy of formation of NiF ₂ described above is -604 kJ / mol, and
The standard free energy of formation of the AlF ₃ film described in JP-A-7-273053 is -1425 kJ / mol, and none of the substances reacts with the halogen-based gas.

A specific calculation example will be described for Al ₂ O ₃ . The standard free energy of formation of Al ₂ O ₃ is -1582 k
J / mol, and it can be inferred that it does not react with the halogen-based gas. For example, the reaction between Al ₂ O ₃ and HF, which is one of the halogen-based gases, can be represented by the following reaction formula.

[0023]

Al ₂ O ₃ + 6HF → 2AlF ₃ + 3H ₂ O (2) The Gibbs free energy of each substance in this reaction formula at 527 ° C. is as follows.

Al ₂ O ₃ : -1796 kJ / mol HF: -438 kJ / mol AlF ₃ : -1629 kJ / mol H ₂ O: -383 kJ / mol From the above values, the difference ΔG in Gibbs free energy is
Can be calculated by

[0025]

ΔG = (2 × (−1629) + 3 × (−383)) − (− 1796 + 6 × (−438)) = 17 kJ / mol (1) This ΔG is a positive value, and Al ₂ O ₃ does not react with HF.

In the present invention, the standard free energy of formation is -600 kJ / mo on the surface of the metal part of the CVD apparatus.
A film is formed using a metal compound having a value lower than l and a thickness of 1 μm to 5 μm. Thereby, peeling is less likely to occur at the time of component replacement, and the effect of preventing corrosion of the metal component by the cleaning gas can be maintained.

In addition, the metal parts of the CVD apparatus are 1 μm thick.
By covering with a NiF ₂ film having a thickness of not less than m and not more than 5 μm, peeling does not easily occur at the time of replacement of parts, and the effect of preventing corrosion of metal parts by the cleaning gas can be maintained.

By manufacturing a semiconductor device using a CVD device having the NiF ₂ film formed on the surface of a metal component,
A semiconductor device can be manufactured with a high manufacturing yield.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 shows a batch processing type CV for forming a poly-Si film according to a first embodiment of the present invention.
The D device will be described.

The reactor for performing the film forming reaction comprises a quartz tube 21 and a flange 24 for supporting the quartz tube. The quartz tube 21 includes an outer tube 21a for maintaining a vacuum and an inner tube 21b for uniformly flowing a source gas. A susceptor 22 for mounting a plurality of wafers 1 inside the inner tube 21b, a susceptor support plate 25 for supporting the susceptor, and a heater 23 for heating these are provided. A gas supply pipe 31 and valves 32v, 33v, 36v,
SiH ₄ feeder 32s, PH ₃ feeder 3 via 38v
3 s, an N ₂ supply device 36 s and a ClF ₃ supply device 38 s are connected, and a conductance valve 42 and an exhaust device 43 for controlling the pressure inside the outer tube 21 a are connected to the flange 24 b via an exhaust pipe 41. .

Of the components of the CVD apparatus, the flanges 24a and 24b and the susceptor support plate 25 were made of metal in order to obtain strength and processing accuracy. Since these metal parts become high in temperature near 400 ° C. due to radiation from the heater 23, a NiF ₂ film was formed on the surface of the base material to prevent corrosion by the cleaning gas. The method for forming the NiF ₂ film will be described below.

First, the case where a metal other than pure nickel such as stainless steel is used as the base material will be described. Nickel plating or nickel alloy plating such as NiP plating is performed on the surface of the metal base material to a thickness of about 20 μm. This is baked out at a temperature of 150 ° C. for one hour in an atmosphere of an inert gas such as Ar, and then heated to a temperature of 500 ° C. and an F ₂ gas is caused to flow, so that NiF
_Two films were formed. When pure nickel is used for the base material, A
After the atmosphere was replaced with an inert gas atmosphere such as r, the mixture was heated to 500 ° C., F ₂ gas was flowed, and a NiF ₂ film was formed on the surface of the base material.

[0033] In order to know the optimum film thickness of the NiF ₂ film, film thickness susceptor support plate 25 rub against the susceptor 22 is caused to form a NiF ₂ film of 10μm from 0.1 [mu] m, working in actual mass production line The temperature of the reactor was raised and lowered and gas cleaning was performed under conditions close to the conditions described above, and the surface of the metal component was observed. The procedure is described below.

As a pseudo film forming operation, the susceptor 22 on which 150 8-inch wafers 1 are placed is placed in the inner tube 21b heated to 580 ° C., which is the film forming temperature of the Poly-Si film by using the heater 23. Insert and wait until thermal equilibrium is reached, then withdraw susceptor 22 and pull
The operation of waiting until cooled to a temperature of ° C. was performed. This pseudo film forming operation was repeated 30 times in total.

Thereafter, gas cleaning was performed in the following procedure. After the outer tube 21a, the inner tube 21b, and the susceptor 22 are heated to 580 ° C. by using the heater 23, the valves 36v and 38v are opened.
N ₂ feeder 36s and ClF ₃ feeder 38s feed N ₂
And ClF ₃ at 300 SCCM and 2700 S, respectively.
The gas was supplied at the flow rate of CCM, and the exhaust amount was controlled by the conductance valve 43 so that the pressure in the outer tube 21a became 100 Pa. This gas cleaning was performed for 90 minutes. After that, the pseudo film forming operation described above was performed. This simulated film formation operation and gas cleaning operation are performed 100 times.
This was repeated twice, and then the surface of the susceptor support plate 25 was visually observed. Table 1 shows the results.

[0036]

[Table 1]

In the susceptor support plate 25 having a NiF ₂ film thickness of 0.5 μm or less, a black discolored portion was observed in a part of the susceptor 22 in contact with the susceptor 22. Further, a tape coated with an adhesive was adhered to the site and peeled off, and it was observed that particle-like fragments were attached to the adhesive of the tape. When the composition of the particles was analyzed by an energy dispersive X-ray method, it was found that the particles were nickel oxide. In contrast, Ni
No discoloration was observed in the samples having a F ₂ film thickness of 1 μm to 5 μm, and no adhesion of particles to the tape was observed. However, when the thickness of the NiF ₂ film is 10μm sample of the formation of the NiF ₂ film, already because the cracks occurred were excluded from the scope of the evaluation. This is considered to be due to the internal stress in the compression direction during the formation of the NiF ₂ film.

In this embodiment, a batch processing type thermal CVD apparatus for forming a Poly-Si film has been described.
SiO ₂ other than i _{layer, O 3 -SiO 2, O 3} -PSG, O 3
_{-BPSG, Si 3 N 4, W} , WSi, TiN, Ta 2 O 5
Similar effects can be obtained in a thermal CVD apparatus for forming a thin film such as the above.

According to the present embodiment, corrosion of the metal component surface could be prevented by covering the surface of the metal component of the CVD apparatus with the NiF ₂ film of 1 μm or more and 5 μm or less.

(Embodiment 2) Next, a single wafer processing type CVD apparatus for forming a SiO ₂ film according to a second embodiment of the present invention will be described with reference to FIG.

The reactor section for performing the film forming reaction comprises a quartz tube 21 and flanges 24a and 24b supporting the quartz tube 21 from both sides. The quartz tube 21 has a susceptor 22 for mounting the wafer 1 therein and a heater 23 for heating them. The gas supply pipe 31 and the valves 34v, 35v, 36v,
38v, TEOS supply via 39v 34s, the He supply 35s, N ₂ supply 36 s, ClF ₃ feeder 38s
And an HF feeder 39s, and a conductance valve 42 and an exhaust device 43 for controlling the pressure inside the quartz tube 21 are connected to the flange 24b via an exhaust pipe 41. A transfer chamber 52 is connected to the flange 24b via a gate valve 51, and a transfer arm 53 for mounting the wafer 1 on the susceptor 22 is provided inside the transfer chamber 52.

Of the components of the CVD apparatus, gas supply pipe 31, valves 34v, 35v, 36v, 38v, 3
9v, the flanges 24a and 24b, the exhaust pipe 41 and the conductance valve 42 were heated to 90 ° C. or higher to prevent TEOS from condensing. These parts were made of metal to obtain strength and processing accuracy. In order to prevent corrosion of these metal parts by the cleaning gas, NiP plating was performed on the surface of stainless steel as a base material, and a NiF ₂ film was formed by fluorination thereof.

[0043] In order to confirm the effect of the film thickness of the NiF ₂ film, a thickness of the flange 24a to rub against the susceptor 22 is caused to form a NiF ₂ film of 0.5μm and 1 [mu] m, in conditions close to the actual mass production process Simulated maintenance work and gas cleaning were performed, and the surface of the metal component was observed. The procedure is described below.

As a simulated maintenance work, the quartz tube 21
The susceptor 22 was removed and mounted without heating, and gas cleaning was performed in the following procedure. The quartz tube 21 and the susceptor 22 was heated to 750 ° C. using a heater 23, a heated state, after opening the valve 36v and 38v, N ₂ supply 36s and ClF ₃ N ₂ and ClF ₃ from feeder 38s Are supplied at flow rates of 500 SCCM and 1000 SCCM, respectively, and the exhaust amount is controlled by the conductance valve 43 so that the pressure in the quartz tube 21 becomes 200 Pa. Under these conditions, ClF ₃ gas was flowed for 500 minutes. After repeating the pseudo-maintenance work and the gas cleaning 100 times, the corrosion state of the portion where the susceptor 22 rubs was visually observed.

As a result, as shown in Table 2, when the thickness of the NiF ₂ film was 0.5 μm, the NiF ₂ film was scratched by rubbing with the susceptor 22, the portion turned black, and the tape was stuck and peeled off. As a result, the generation of particles was confirmed, but when the thickness of the NiF ₂ film was 1 μm, no discoloration was observed at the scratched portion, and no generation of particles was observed.

[0046]

[Table 2]

Further, as can be easily predicted from the first embodiment, when the thickness of the NiF ₂ film is larger than 5 μm, the NiF ₂ film peels off due to internal stress at the time of formation and cannot be applied to a CVD apparatus.

In this embodiment, a single-wafer processing type thermal CVD apparatus for forming an SiO ₂ film has been described. However, O ₃ -SiO ₂ , O ₃ -PSG, O ₃ -BPSG, Poly ₃ other than the SiO ₂ film are used.
_{-Si, Si 3 N 4, W} , WSi, TiN, a thermal CVD apparatus for forming a thin film such as Ta ₂ O _5, and a similar effect also in the plasma CVD apparatus for forming a thin film of SiO ₂ or the like to obtain .

According to this embodiment, the surface of the metal part of the CVD apparatus is covered with the NiF ₂ film having a thickness of 1 μm or more and 5 μm or less, thereby preventing the corrosion of the metal part surface and the generation of particles. We were able to.

(Embodiment 3) Next, as a third embodiment of the present invention, a stacked capacitor in which an information storage capacitive element is arranged above a memory cell selecting MISFET will be described.
DRAM (Dyna) with memory cells of Capacitor structure
An example in which the present invention is applied to the manufacture of a mic (Random Access Memory) will be described. In this memory cell, the lower electrode and the upper electrode of the information storage capacitance element are made of Poly-Si and TiN, respectively, and the capacitance insulating film is made of Ta ₂ O ₅ . The interlayer insulating film for separating the information storage capacitor from the bit line formed thereon is made of SiO ₂ .

In order to form this memory cell, first, as shown in FIG. 3, a p-type impurity (boron) is ion-implanted into the main surface of a semiconductor wafer 1 made of, for example, p-type single crystal silicon. After forming the well 2, the well-known LO
The field oxide film 3 is formed in the element isolation region on the surface of the p-type well 2 by the COS method, and then the gate oxide film 4 is formed in the element formation region. Next, a p-type impurity (boron) is ion-implanted into the p-type well 2 including the lower portion of the field oxide film 3 to form a p-type channel stopper layer 5 for element isolation.

Next, as shown in FIG.
The gate electrode 6 of the memory cell selecting MISFET is formed thereon. This gate electrode 6 is connected to the word line W of the memory cell.
Also serves as L. The gate electrode 6 (word line WL) is formed on the p-type well 2 by Poly-Si (polycrystalline silicon) by the CVD method.
A film (or a polycide film in which a polycrystalline silicon film and a refractory metal silicide film are laminated) and a SiO ₂ film 7 are deposited. The CVD apparatus described in Example 1 and Example 2 was used for forming the Poly-Si film and the SiO ₂ film 7. Next, the film formation will be described.

First, the formation of a Poly-Si film will be described with reference to FIG. Quartz tube 2 heated to about 580 ° C
The 150 6-inch wafers 1 are placed on the susceptor 22 in the 1. Then, after opening the valve 32v and 33v, SiH ₄ supply 32s and PH ₃ from feeder 33s SiH ₄ and PH ₃ were each supplied at a flow rate of 1000SCCM and 5～100SCCM, the pressure in the outer tube 21a is 50Pa The exhaust amount is controlled by the conductance valve 43 so as to be as follows. Then, SiH
About 4n the Poly-Si film on the wafer 1 by ₄ of the thermal decomposition reaction
It can be formed at a film forming rate of m / min.

Next, the formation of the SiO ₂ film will be described with reference to FIG. Using a transfer arm 53 from a transfer chamber 52 to a susceptor 22 in a quartz tube 21 heated to about 750 ° C., two 6-inch wafers 1 are passed through a gate valve 51.
Put. Then, after opening the valve 32 and the valve 34, TEOS and He are supplied at a flow rate of 100 SCCM from the TEOS supply unit 34s and the He supply unit 35s, respectively, and the conductance valve 43 controls the pressure in the quartz tube 21 to 100 Pa. Control the displacement. Then, an SiO ₂ film can be formed on the surface of the wafer 1 at a deposition rate of about 30 nm / min by a thermal decomposition reaction of TEOS.

Next, these films are patterned and formed by etching using a photoresist as a mask.

Next, as shown in FIG. 5, an n-type impurity (phosphorus) is ion-implanted into the p-type well 2 to form an n-type semiconductor region 8 (source region, drain region) of the memory cell selecting MISFET. Thereafter, as shown in FIG. 6, a sidewall spacer 9 is formed on the side wall of the gate electrode 6 (word line WL), and then a SiO ₂ film 10 is deposited on the entire surface of the p-type well 2 by the CVD method. The CVD apparatus described in Example 1 was used for depositing the SiO ₂ film 10. The side wall spacer 9 is formed by patterning an SiO ₂ film deposited on the entire surface of the p-type well 2 by a CVD method by a reactive ion etching method.

Next, as shown in FIG. 7, the connection hole 11 was formed by etching the SiO ₂ film 10 and the gate oxide film 4 on one of the source region and the drain region of the memory cell selecting MISFET. After that, the SiO ₂ film 10
A Poly-Si film 12 having a thickness of about 200 nm is formed on the upper surface of the substrate. The CVD apparatus described in Example 1 was used for forming the Poly-Si film 12.

Next, as shown in FIG. 8, the poly-Si film 12 is patterned by dry etching using a photoresist as a mask to form a lower electrode 12A of the information storage capacitor. The lower electrode 12A is connected to one of the source region and the drain region (the n-type semiconductor region 8) of the memory cell selecting MISFET through the connection hole 11.

Next, as shown in FIG. 9, the lower electrode 12A
A Ta ₂ O ₅ film 13 having a thickness of about 200 nm is deposited on the upper surface of the substrate.

Next, as shown in FIG. 10, Ta ₂ O ₅ film 1
A TiN film 14 having a thickness of about 300 nm is deposited on the upper part of FIG. Next, as shown in FIG. 11, the TiN film 14 and the underlying Ta ₂ O ₅ film 13 are patterned by dry etching using a photoresist as a mask, thereby forming the upper electrode 14A of the information storage capacitor, the capacitor insulation. Membrane (Ta
₂ O ₅ film 13) and the information storage capacitor of a stacked structure of the upper electrode 14A is configured to obtain.

Next, as shown in FIG. 12, an SiO ₂ film 15 having a thickness of about 500 nm is deposited on the information storage capacitor.

Thereafter, as shown in FIG. 13, the SiO ₂ film 15, the SiO ₂ film 10 and the gate oxide film 4 are etched to form the source region of the memory cell selecting MISFET.
A connection hole 16 is formed above the other of the drain regions (n-type semiconductor region 8). Subsequently, W is inserted into the connection hole 16.
After the plug 17 is formed by embedding a film or a Poly-Si film, a W film deposited on the SiO ₂ film 15 by a CVD method or a sputtering method is patterned to form a bit line BL.

Note that an upper wiring is formed above the bit line BL via an interlayer insulating film, and a passivation film is further formed thereon, but these are not shown.

As a result of comparing the manufacturing yield of the DRAM manufactured as described above with that of the conventional example, it was found that the manufacturing yield of the DRAM was improved from 50% to 55% by using the CVD apparatuses of the first and second embodiments. Was completed.

According to this embodiment, the DRAM manufactured as described above does not generate particles due to corrosion of metal parts in gas cleaning of the CVD apparatus.
The production yield of the semiconductor device can be improved.

[0066]

According to the present invention, the surface of a metal part of a CVD apparatus has a standard free energy of formation of -600 kJ / mo.
By covering with a metal compound having a value lower than 1 and a thickness of 1 μm or more and 5 μm or less, for example, a NiF ₂ film, corrosion of metal parts in gas cleaning can be prevented, and metal contamination or generation of particles on a wafer can be prevented. Can be prevented. Further, by applying this CVD apparatus to the manufacture of a semiconductor device, the manufacturing yield of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 shows a batch-process type CVD according to a first embodiment of the present invention.
Sectional drawing which shows the structure of an apparatus.

FIG. 2 is a sectional view showing the structure of a single wafer processing type CVD apparatus according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a principal part of a semiconductor wafer showing a method of manufacturing a DRAM according to a third embodiment of the present invention.

FIG. 4 is an essential part cross sectional view of a semiconductor wafer showing a method of manufacturing a DRAM according to a third embodiment of the present invention;

FIG. 5 is an essential part cross sectional view of a semiconductor wafer, showing a method of manufacturing a DRAM according to a third embodiment of the present invention;

FIG. 6 is an essential part cross-sectional view of a semiconductor wafer showing a method of manufacturing a DRAM according to a third embodiment of the present invention.

FIG. 7 is an essential part cross sectional view of a semiconductor wafer showing a method of manufacturing a DRAM according to a third embodiment of the present invention;

FIG. 8 is an essential part cross sectional view of a semiconductor wafer showing a method of manufacturing a DRAM according to a third embodiment of the present invention;

FIG. 9 is an essential part cross sectional view of a semiconductor wafer, illustrating a method of manufacturing a DRAM according to a third embodiment of the present invention;

FIG. 10 is an essential part cross sectional view of a semiconductor wafer, illustrating a method of manufacturing a DRAM according to a third embodiment of the present invention;

FIG. 11 is an essential part cross sectional view of a semiconductor wafer, illustrating a method of manufacturing a DRAM according to a third embodiment of the present invention;

FIG. 12 is an essential part cross sectional view of a semiconductor wafer, illustrating a method of manufacturing a DRAM according to a third embodiment of the present invention;

FIG. 13 is an essential part cross sectional view of a semiconductor wafer showing a method of manufacturing a DRAM according to a third embodiment of the present invention;

[Explanation of symbols]

1 ... wafer, 2 ... p-type well, 3 ... field oxide film,
4 ... gate oxide film, 5 ... p-type channel stopper layer, 6 ...
Gate electrode, 7: SiO ₂ film, 8: n-type semiconductor region (source region, drain region), 9: sidewall spacer, 10: SiO ₂ film, 11: connection hole, 12: Poly-S
i film, 12A: lower electrode, 13: Ta ₂ O ₅ film, 14: T
iN film, 14A: upper electrode, 15: SiO ₂ film, 16:
Connection hole, 17 plug, 21 quartz tube, 21a
Outer tube, 21b inner tube, 22 susceptor, 23 heater, 24a flange, 24b flange, 25 susceptor support plate, 31 gas supply piping, 3
2v ... valve, 32s ... SiH ₄ supply, 33v ... valve, 33s ... PH ₃ supply, 34v ... valve, 34s ...
TEOS supply, 35v ... valve, 35s ... the He supply, 36v ... valve, 36 s ... N ₂ supply, 38v ... valve, 38s ... ClF ₃ supply, 39v ... valve, 39
s: HF feeder, 41: exhaust pipe, 42: conductance valve, 43: exhaust device, 51: gate valve, 52
... Transfer chamber, 53 ... Transfer arm.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Norihiro Uchida 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd.

Claims (3)

[Claims] 1. A reactor for performing a film forming reaction, a gas supply unit for supplying a source gas, and an exhaust device for exhausting a reaction gas from the reactor, and in particular, a gas supply of a halogen-based gas for the purpose of gas cleaning of the reactor and piping. The standard free energy of formation is-
A CVD apparatus characterized in that the surface of a metal component is covered with a metal compound having a value of less than 600 kJ / mol and a thickness of 1 μm or more and 5 μm or less. 2. A reactor for performing a film forming reaction, a gas supply device for supplying a source gas, and an exhaust device for exhausting a reaction gas from the reactor, and in particular, a gas supply of a halogen-based gas for the purpose of gas cleaning of the reactor and piping. A CVD apparatus, comprising: a NiF ₂ film having a thickness of 1 μm or more and 5 μm or less; 3. A method for manufacturing a semiconductor device, comprising using the CVD apparatus according to claim 1.