JPH11219958A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can remarkably reduce base-collector capacitance. SOLUTION: A step of removing a first insulating film 16 at the bottom of an opening 22 to expose the surface of a silicon layer 14 of a first conductivity type and to form eave parts of a first polycrystalline silicon layer 18 is carried out in two stages by anisotropic etching and isotropic etching, so that, when the amounts of removal of the first insulating film 16 by the respective etching operations are set, the etched depth of the film 16 in a vertical direction and the amount of retreat in a horizontal can be controlled independently of each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a self-aligned bipolar transistor using an epitaxial growth technique for forming a base layer.

[0002]

2. Description of the Related Art In recent years, a method of manufacturing a bipolar transistor has been proposed in which the base layer is formed by an epitaxial growth method in order to reduce the thickness of the base layer in response to a demand for high-speed operation of the bipolar transistor. When a bipolar transistor is manufactured by using the epitaxial growth method, the problem of channeling caused by the conventional ion implantation method, the problem of enhanced diffusion due to ion implantation damage, and the like are solved, and an extremely thin base layer is realized.

When a bipolar transistor is manufactured by an epitaxial growth method, the thickness and the impurity concentration of the base layer can be controlled completely independently, and the head junction bipolar transistor can be formed by using a SiGe alloy for the base layer. It also has the advantage that it can be realized.

An example of a method for manufacturing a self-aligned bipolar transistor in which a base layer is formed by a selective epitaxial growth method is IEEE Transact.
ion on Electron Devices V
OL. 41, No. 8, August, 1994, p.
p. There is a technology disclosed in 1373-1378.
Hereinafter, the manufacturing method will be described based on the steps shown in FIGS.

First, as shown in FIG. 3A, an N ⁺ -type buried diffusion layer 52 is formed on a P-type silicon
^An N ⁻ type silicon layer 54 is sequentially formed on the ⁺ type buried diffusion layer 52.

Further, a silicon oxide film 56 and a first polycrystalline silicon layer 58 are sequentially formed on the N ⁻ type silicon layer 54. Next, after doping boron in the first polycrystalline silicon layer 58, a silicon nitride film 60 is formed on the first polycrystalline silicon layer 58.

The next silicon nitride film 60 and the first polycrystalline silicon layer 58 are patterned by a well-known lithography technique and anisotropic dry etching technique to form an emitter opening 62 (FIG. 3B). Next, a sidewall 64 made of silicon nitride is formed on the side wall of the emitter opening 62.
Is formed, the silicon oxide film 56 at the bottom of the emitter opening 62 is removed by isotropic wet etching until the surface of the N ⁻ type silicon layer 54 is exposed, and the silicon oxide film 56 is receded from the end of the emitter opening 62. As a result, part of the N ⁻ type silicon layer 54 is exposed (FIG. 3C).

Next, as shown in FIG. 4D, a P-type base layer 68 is formed on the N ^- type silicon layer 54 by using a selective chemical vapor deposition technique. At this time, a second polycrystalline silicon layer 70 having a thickness similar to that of the P-type base layer 68 is simultaneously grown from the eaves of the first polycrystalline silicon layer 58.
The P-type base layer 68 and the first polycrystalline silicon layer 58 are connected via the polycrystalline silicon layer 70 of FIG.

Next, after a sidewall 72 made of silicon oxide is further formed on the side wall of the sidewall 64 made of silicon nitride, an N ⁺ -type polycrystalline silicon 74 is formed on the entire surface of the substrate, and patterning is performed. Next, after a silicon oxide film 76 is formed on the entire surface of the substrate, a heat treatment is performed to form an N ⁺ -type emitter layer 78 on the surface of the P-type base layer 68.

Thereafter, openings, metallization, and the like for making contact with the base, emitter, and collector are performed to form electrodes, wirings, and the like, thereby obtaining a bipolar transistor (not shown).

[0011]

However, in the above-described method of manufacturing a semiconductor device, the silicon oxide film 56 at the bottom of the emitter opening 62 is removed, and the N ^- type silicon layer 54 is removed.
Is performed by isotropic wet etching, the silicon oxide film 56 is removed by being receded in the lateral direction by a distance substantially equal to its thickness.

More practically, since the adhesion between the side wall 64 made of silicon nitride and the silicon oxide film 56 is not perfect, the etching proceeds rapidly along this interface, and the lateral width exceeding the vertical etching depth is increased. Retreat in the direction occurs.

As described above, when the amount of recession of the silicon oxide film 56 in the lateral direction is increased, the junction area between the base and the collector of the transistor is increased, and the junction capacitance between the base and the collector is increased. There is a problem in that the base-collector capacitance, which is an obstacle to operating the transistor at high speed, is increased.

Further, it becomes a part of the base collector capacitance.
When the thickness of the silicon oxide film 56 is increased in order to reduce the capacitance between the first polysilicon layer 58 and the N ⁻ type silicon layer 54 via the silicon oxide film 56, Since the increase in the amount of retreat is more remarkable, the base-collector capacitance as a whole cannot be reduced.

The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a base-collector capacitance is significantly reduced.

[0016]

According to a first aspect of the present invention, a first conductive type silicon layer is formed on a semiconductor substrate, and the first conductive type silicon layer is formed on the first conductive type silicon layer. A first step of forming a first insulating film on the first insulating film, and a second step of forming a first polycrystalline silicon layer containing an impurity of a second conductivity type different from the first conductivity type on the first insulating film. A third step of forming a second insulating film on the first polycrystalline silicon layer; and forming a part of the second insulating film and a part of the first polycrystalline silicon layer in the first insulating layer. A fourth step of forming an opening by removing the film until the surface of the film is exposed; and a fifth step of forming a sidewall made of a third insulating film on a side wall of the opening.
A step of removing a part of the first insulating film at the bottom of the opening by anisotropic etching, and a step of removing the first insulating film remaining after the sixth step. The first conductive type silicon layer is removed by isotropic etching until the surface of the first conductive type silicon layer is exposed, and is removed by a predetermined length from the end of the opening along the surface of the first conductive type silicon layer. A step of forming an eave portion made of a first polycrystalline silicon layer, and a semiconductor layer containing a second conductivity type impurity at least in part on the exposed first conductivity type silicon layer. An eighth step of selectively growing and simultaneously growing a second polycrystalline silicon layer from the eaves of the first polycrystalline silicon layer.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the semiconductor layer containing at least a part of the impurity of the second conductivity type is made of silicon. .

According to the method of manufacturing a semiconductor device according to the first and second aspects, the first insulating film at the bottom of the opening is removed to remove the first insulating film.
The step of exposing the surface of the conductive silicon layer and forming an eave portion made of the first polycrystalline silicon layer is performed in two steps using anisotropic etching and isotropic etching,
By setting the removal amount of the first insulating film by each etching, the vertical etching depth and the horizontal retreat amount of the first insulating film are independently controlled.
By increasing the thickness of the first insulating film, a first insulating film is interposed between the first polycrystalline silicon layer serving as an extraction electrode of the base region and the first conductivity type silicon layer serving as the collector region. The base-collector junction capacitance can be reduced while reducing the formed capacitance, and the base-collector capacitance can be greatly reduced as a whole.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the semiconductor layer containing at least a part of the second conductivity type impurity is made of silicon germanium. I do.

According to the method of manufacturing a semiconductor device according to the third aspect, the same effects as those of the first and second aspects can be obtained for a semiconductor device (heterojunction bipolar transistor) using silicon germanium as a base layer.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

[0022] First, the N ⁺ -type sense Me included diffusion layer 12 formed on the silicon substrate 10 P-type as shown in FIG. 1 (A), on the subsequent N ⁺ -type sense Me included diffusion layer 12 N ^- Formed silicon layers 14 are sequentially formed.

Next, on the N ^- type silicon layer 14, a film thickness of 200
A silicon oxide film 16 and a first polycrystalline silicon layer 18 having a thickness of about nm are formed. Further, after boron ions are implanted into the first polycrystalline silicon layer 18 at about 5 × 10 ²⁰ cm ⁻³ and annealing is performed, a silicon nitride film 20 is formed on the first polycrystalline silicon layer 18.

Next, the silicon nitride film 20 and the first polycrystalline silicon layer 18 are patterned by a known lithography technique and anisotropic dry etching technique to form an emitter opening 22 (FIG. 1B). ).

Next, as shown in FIG. 1C, a sidewall 24 made of silicon nitride is
To form Next, reactive ion etching (RIE)
The silicon oxide film 16 at the bottom of the emitter opening 22 is removed to a thickness of about 100 nm by anisotropic etching. At this time, the etching of the silicon oxide film 16 proceeds in the vertical direction, but hardly occurs in the horizontal direction.

Next, as shown in FIG. 2D, the remaining silicon oxide film 16 is isotropically etched using a hydrofluoric acid solution of about 5% (% by weight) to form a bottom portion of the emitter opening 22. Of the silicon oxide film 16 is removed until the surface of the N ⁻ type silicon layer 14 is exposed, and 100 nm from the opening end.
A degree of removal is performed so as to retreat along the surface of the N ⁻ type silicon layer 14 to expose a part of the bottom surface of the first polycrystalline silicon layer 3 to form an eave portion.

Next, as shown in FIG. 2E, a film in which at least a portion of the N ⁻ type silicon layer 14 is doped with a high concentration of boron is formed on the N ⁻ type silicon layer 14 serving as a collector region by using a selective chemical vapor deposition technique. A base layer 26 having a thickness of about 120 nm is formed.
At this time, a second polycrystalline silicon layer 28 having a thickness similar to that of the base layer 18 is grown from the eaves of the first polycrystalline silicon layer 18, and a base is formed via the second polycrystalline silicon layer 28.
Layer 26 and first polysilicon layer 18 are connected.

Next, as shown in FIG. 2F, after forming a side wall 30 made of silicon oxide on the side wall of the side wall 24 made of silicon nitride, an N ⁺ -type polycrystalline silicon layer 32 is formed on the entire surface of the substrate. And patterning is performed. Further, after a silicon oxide film 34 is formed on the entire surface of the substrate, a heat treatment is performed. By this heat treatment, phosphorus diffuses from the N ⁺ type polycrystalline silicon layer 32 to the surface of the base layer 26, and N ⁺ A mold emitter region 36 is formed.

Thereafter, by performing metallization and the like on the opening for making contact with the base, the emitter and the collector, electrodes, wirings and the like are formed, and a bipolar transistor is obtained (not shown).

According to the embodiment of the present invention, the silicon oxide film at the bottom of the emitter opening is removed to expose the surface of the N ^- type silicon layer, thereby forming an eave portion made of the first polycrystalline silicon layer. The process is performed in two steps using anisotropic etching and isotropic etching, and by setting the removal amount of the silicon oxide film by each etching, the etching depth in the vertical direction of the silicon oxide film and the horizontal Since the amount of receding is controlled independently, the thickness of the silicon oxide film is increased so that the first polycrystalline silicon layer serving as an extraction electrode of the base region and the N ⁻ -type silicon layer serving as the collector region are separated. The base-collector junction capacitance can be reduced while reducing the capacitance formed through the silicon oxide film between them, and the base-collector capacitance can be greatly reduced as a whole. You.

In the embodiment of the present invention, the present invention
An example in which the present invention is applied to a PN type bipolar transistor has been described.
The present invention can be applied to a bipolar transistor.

Further, the present invention can be applied to a heterojunction type bipolar transistor using silicon germanium as a base layer.

[0033]

As described above, according to the method of manufacturing a semiconductor device according to the first or second aspect, the first portion at the bottom of the opening is formed.
The step of exposing the surface of the first conductivity type silicon layer by removing the insulating film and forming an eave portion made of the first polycrystalline silicon layer is performed by using anisotropic etching and isotropic etching. It is performed in stages, and by setting the removal amount of the first insulating film by each etching, the vertical etching depth and the horizontal retreat amount of the first insulating film are controlled independently. By increasing the thickness of the first insulating film, a first insulating film is interposed between the first polycrystalline silicon layer serving as an extraction electrode of the base region and the first conductivity type silicon layer serving as the collector region. The base-collector junction capacitance can be reduced while reducing the formed capacitance, and the base-collector capacitance can be greatly reduced as a whole.

According to the method of manufacturing a semiconductor device according to the third aspect, the same effects as those of the first and second aspects can be obtained for a semiconductor device (heterojunction bipolar transistor) using silicon germanium as a base layer.

[Brief description of the drawings]

FIG. 1 is a process chart showing the contents of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process chart showing the contents of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process chart showing the contents of a conventional method for manufacturing a semiconductor device.

FIG. 4 is a process chart showing the contents of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 10 P-type silicon substrate 12 N ⁺ -type embedded diffusion layer 14 N ^-- type silicon layer (first conductivity type silicon layer) 16 silicon oxide film (first insulating film) 18 first polycrystalline silicon layer 20 silicon Nitride film (second insulating film) 22 Emitter opening (opening) 24 Side wall made of silicon nitride (side wall made of third insulating film) 26 P-type base layer (semiconductor layer) 28 Second polycrystal Silicon layer 30 Side wall made of silicon oxide 32 N ⁺ -type polycrystalline silicon layer 34 Silicon oxide film 36 N ⁺ -type emitter region

Claims (3)

[Claims] A first step of forming a silicon layer of a first conductivity type on a semiconductor substrate, and further forming a first insulating film on the silicon layer of the first conductivity type; A second step of forming a first polysilicon layer containing an impurity of a second conductivity type different from the first conductivity type on the film, and forming a second insulating film on the first polysilicon layer A third step of removing the second insulating film and a part of the first polycrystalline silicon layer until the surface of the first insulating film is exposed to form an opening; A fifth step of forming a sidewall made of a third insulating film on a side wall of the opening; and a sixth step of removing a part of the first insulating film at the bottom of the opening by anisotropic etching. And removing the first insulating film remaining after completion of the sixth step by isotropic etching to the first conductivity type. The first polycrystalline silicon is removed until the surface of the first silicon layer is exposed, and is removed by a predetermined length from the end of the opening along the surface of the first conductivity type silicon layer. A seventh step of forming an eave portion made of a layer, and selectively growing a semiconductor layer containing at least part of a second conductivity type impurity on the exposed first conductivity type silicon layer, An eighth step of growing a second polycrystalline silicon layer from an eaves portion of the first polycrystalline silicon layer. 2. The method according to claim 1, wherein the semiconductor layer containing at least a part of the second conductivity type impurity is made of silicon. 3. The method according to claim 1, wherein the semiconductor layer including at least a part of the second conductivity type impurity is made of silicon germanium.