JPH11219586A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit in which occurrence of a noise can be prevented when cut-off control of an output current is performed at the time of switching an operation mode or the like. SOLUTION: In an internal power source voltage dropping circuit 1, internal power source voltage int. Vcc is supplied from a pMOS transistor 12 of a VDC2 for standby and pMOS transistors 16, 18, 20 of a VDC3 for active at the time of an active state, when supplying internal power source voltage int. Vcc from the VDC3 for active is stopped at the time of a standby state, the pMOS transistors 16, 18, 20 are turned off in order, an output current from the VDC3 for active is decreased by stages and cut off, supplying the internal power source voltage int. Vcc from the VDC3 for active is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an internal power supply circuit which converts a power supply voltage supplied from the outside into a predetermined voltage and supplies the same to an internal circuit.

[0002]

2. Description of the Related Art FIG. 10 is a circuit diagram showing an example of a conventional semiconductor integrated circuit. In FIG. 10, DRA
The internal power supply step-down circuit used in M is shown as an example. In FIG. 10, an internal power supply step-down circuit 200 generates an internal power supply voltage int.Vcc by stepping down an external power supply voltage Vcc supplied from a power supply terminal and supplies the internal power supply voltage to each internal circuit of the semiconductor integrated circuit. . In a DRAM, the current consumption is extremely small in a standby state in which only data stored in the memory is held. In the standby state, the memory activates the current capacity of the internal power supply supplied from the internal power supply step-down circuit 200 to each unit. Make it much smaller than in the state.

[0003] From this, the internal power supply step-down circuit 200
Is a step-down power supply circuit for standby (hereinafter referred to as standby VDC) 201 having a small current supply capability, an active step-down power supply circuit (hereinafter referred to as VDC) 202 having a large current supply capability, and a reference voltage Vref. And a reference voltage generation circuit 203 for generating and outputting. Standby VDC 201 and active VDC
In C202, the voltage value of the internal power supply voltage int.Vcc is determined by the reference voltage Vref input from the reference voltage generation circuit 203. That is, the internal power supply step-down circuit 200
Is the reference voltage V input from the reference voltage generation circuit 203.
The voltage value of the internal power supply voltage int.Vcc is controlled and output so as to be ref.

[0004] The standby VDC 201 includes a differential amplifier 211 and a p-channel MOS transistor (hereinafter referred to as pM
212).
The active VDC 202 includes a differential amplifier 215 and a pM
OS transistors 216 and 217 are formed.
In the standby VDC 201, the differential amplifier 211
Is connected to the gate of the pMOS transistor 212, the drain of the pMOS transistor 212 is connected to the non-inverting input of the differential amplifier 211, and the connection forms the output of the standby VDC 201. Further, the inverting input of the differential amplifier 211 is connected to the reference voltage generating circuit 203 to receive the reference voltage Vref, the source of the pMOS transistor 212 is connected to the power supply terminal, and the power supply voltage Vcc is applied.

In the active VDC 202, the output of the differential amplifier 215 is connected to the gate of a pMOS transistor 216, the drain of the pMOS transistor 216 is connected to the non-inverting input of the differential amplifier 215, and the connection is It is connected to the source of the transistor 217. The inverting input of the differential amplifier 215 is connected to the reference voltage generation circuit 203 to receive the reference voltage Vref, the source of the pMOS transistor 216 is connected to the power supply terminal, and the power supply voltage Vcc is applied.

The gate of the pMOS transistor 217 is
An external row address strobe signal (hereinafter, / RAS)
Signal is input to an external input terminal / RAS (hereinafter, referred to as a / RAS terminal). In addition, /
The / in the RAS indicates the inversion of the signal level, and indicates that the signal is low active. Furthermore,
The drain of the pMOS transistor 217 outputs the output of the active VDC 202 and the standby VD
Connected to the output of C201, this connection forms the output of the internal power supply step-down circuit 200.

In such a configuration, the standby V
The pMOS transistor 212 of the DC 201 and the pMOS transistor 216 of the active VDC 202 are formed with different gate sizes.
The S transistor 216 is a pMOS transistor 212
It is formed so that a sufficiently larger current flows.

For this reason, in the active state, L
The low level / RAS signal is output from the pMOS transistor 21
7, the pMOS transistor 217 is turned on to be in a conductive state, and the pMOS transistor 212 is turned on.
And 216, the internal power supply step-down circuit 20
0, the internal power supply voltage int.Vcc is output. On the other hand, in the standby state, the high level / RAS signal is input to the gate of the pMOS transistor 217, the pMOS transistor 217 is turned off and turned off, and the current is supplied only from the pMOS transistor 212. And the internal power supply voltage int.Vcc is output.

[0009]

However, at the time of switching from the active state to the standby state, a large current flowing from the pMOS transistor 216 is turned off to turn off the pMOS transistor 217, thereby turning off the internal power supply step-down circuit 200. In order to block the output from flowing, the drain voltage of the pMOS transistor 216 rises, and accordingly, the power supply voltage Vcc also rises.

As described above, the pMOS transistor 217
Every time the power supply voltage Vcc is turned off and turned off, noise is generated in the power supply voltage Vcc, and the effect of the noise appears on each internal circuit to which the power supply voltage Vcc is applied. In the case of the internal power supply step-down circuit 200, the reference voltage generation circuit 203 also converts the power supply voltage Vcc to the reference voltage Vre.
Since f is generated and noise appears in the reference voltage Vref due to the noise, there is a problem that the internal power supply voltage int.Vcc is not constant due to the influence of noise.

[0011] Such a noise problem does not occur only during normal operation, but also occurs when shifting from the normal operation mode to the test mode. The internal power supply circuit in the DRAM includes a substrate voltage generation circuit and a boosted voltage generation circuit in addition to the internal power supply voltage step-down circuit 200. The substrate voltage generation circuit generates and outputs a bias voltage of the semiconductor substrate, and applies a negative substrate voltage Vbb to the semiconductor substrate. The boosted voltage generation circuit boosts an external power supply voltage Vcc supplied from a power supply terminal, generates a boosted voltage Vpp, and supplies the generated voltage to each unit.

In the test mode, each part is tested by using the power supply voltage Vcc or an externally applied voltage without using the voltages output from the internal power supply step-down circuit, the substrate voltage generation circuit and the boosted voltage generation circuit. I do. FIG. 11 is a schematic block diagram showing a conventional configuration example of an internal power supply circuit of a semiconductor integrated circuit. In FIG. 11, DR
An internal power supply circuit used in AM is shown as an example.

In FIG. 11, an internal power supply circuit 220
The internal power supply step-down circuit 200, the substrate voltage generation circuit 221 and the boost voltage generation circuit 222 shown in FIG.
Output switching circuits 225 to 227 are connected to outputs of the boosted voltage generation circuit 222. The output switching circuit 225 switches between the output of the internal power supply step-down circuit 200 and the external input terminal Ia to which the power supply voltage Vcc is applied. The output switching circuit 226 outputs the output of the substrate voltage generation circuit 221 and a predetermined voltage from the outside. The output switching circuit 227 switches between the output of the boosted voltage generation circuit 222 and the external input terminal Ic to which a predetermined voltage is applied from the outside.

The output switching circuits 225 to 227 are the same circuit, and will be described using the output switching circuit 225. The output switching circuit 225 includes n-channel MOS transistors (hereinafter, referred to as nMOS transistors) 231 and 232 and an inverter circuit 233. The drain of the nMOS transistor 231 is connected to the external input terminal Ia to which the power supply voltage Vcc is applied. The source of the nMOS transistor 231 and the source of the nMOS transistor 232 are connected. Is formed.

The drain of the nMOS transistor 232 is connected to the output of the internal power supply step-down circuit 200, and the gate is connected to the output of the inverter circuit 233. Also,
The gate of the nMOS transistor 231 is connected to the input of the inverter circuit 233, and a signal TEST instructing a transition from the normal operation to the test mode operation is connected to the connection.
(Hereinafter, referred to as a TEST signal).

In such a configuration, during normal operation, a low-level TEST signal is input, and the nMOS transistor 231 is turned off to be in a non-conductive state.
The S transistor 232 is turned on to be in a conductive state. From this, the nMOS transistor 232 includes:
At maximum, VDC 201 for standby in active state
The current output from the active VDC 202 flows. Here, when a high-level TEST signal is input and the test mode is entered, the nMOS transistor 231 is turned on and turned on, and the nMOS transistor 232 is turned off and turned off.

Therefore, when the test mode is changed from the normal operation to the test mode, if the maximum current flows through the nMOS transistor 232, the pMOS transistor 2 shown in FIG.
The same problem as when turning off 17 occurs. This is because the output current of the substrate voltage generation circuit 221 is cut off by the output switching circuit 226 during the test mode, and the output current of the boosted voltage generation circuit 222 is
A similar problem occurs when the light is blocked by the switch 27.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and it is an object of the present invention to provide a semiconductor integrated circuit capable of preventing generation of noise when controlling the cutoff of output current when switching operation modes. The aim is to obtain a circuit.

[0019]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention has an internal power supply circuit which generates a predetermined voltage based on a power supply voltage applied from the outside and supplies it to each internal circuit. A reference voltage generating section for generating and outputting a predetermined reference voltage, and generating a predetermined internal power supply voltage from an external power supply voltage based on the reference voltage from the reference voltage generation section and outputting the generated internal power supply voltage to each circuit A first internal power supply circuit section, a first internal power supply voltage generating section for generating a predetermined internal power supply voltage from an external power supply voltage based on a reference voltage from a reference voltage generating section and outputting the predetermined internal power supply voltage to each circuit together with the first internal power supply circuit section; A second internal power supply circuit having a higher current supply capability than the power supply circuit, wherein the second internal power supply circuit outputs an output current when the current consumption of each circuit supplying the internal power supply voltage decreases. Reduce the internal power It is intended to stop the output of the pressure.

Further, a semiconductor integrated circuit according to the present invention comprises:
2. The second internal power supply circuit unit according to claim 1, wherein the second internal power supply circuit outputs a differential amplifier to which the output internal power supply voltage and a predetermined reference voltage are input, and each signal generated by delaying an input signal to a different time. A delay circuit section, and an output circuit section for changing an output current for supplying an internal power supply voltage in accordance with an output voltage of the differential amplifier and each signal from the delay circuit section; When the current consumption of each of the circuits supplied is reduced, a predetermined signal is input from the outside, and the output circuit section outputs an output current according to each of the delay signals having different delay amounts output from the delay circuit section. The output of the internal power supply voltage is stopped in a stepwise manner.

Further, a semiconductor integrated circuit according to the present invention comprises:
2. The differential amplifier according to claim 1, wherein the second internal power supply circuit unit supplies the output power supply voltage and a predetermined reference voltage to the differential amplifier, and supplies the internal power supply voltage according to the output voltage of the differential amplifier. An output circuit section for changing an output current for shutting down, and a cutoff control circuit section for performing cutoff control of an output current from the output circuit section, wherein the cutoff control circuit section is supplied with an internal power supply voltage. When a predetermined signal input from the outside is input when the current consumption of each circuit is reduced, the output current output from the output circuit section is reduced stepwise to shut off the output to the outside. .

Further, according to the semiconductor integrated circuit of the present invention,
The control according to claim 3, wherein the cutoff control circuit unit outputs each signal generated by delaying the input signal at a different time, and the respective delay signals output from the delay circuit unit perform operation control. Multiple MOs with different gate sizes
An S transistor, and the delay circuit unit turns on each MOS transistor to make it conductive, outputs an output current from the output circuit unit to each circuit, and when the predetermined signal is input from the outside, a drain current Are turned off in order from the MOS transistor having the largest value to make it non-conductive, the output current output from the output circuit section is reduced stepwise, and the output to the outside is cut off.

Further, a semiconductor integrated circuit according to the present invention comprises:
2. The differential amplifier according to claim 1, wherein the second internal power supply circuit unit supplies the output power supply voltage and a predetermined reference voltage to the differential amplifier, and supplies the internal power supply voltage according to the output voltage of the differential amplifier. And an output circuit for changing an output current for inputting a predetermined signal externally input when the current consumption of each circuit to which the internal power supply voltage is supplied becomes small. Then, the output current is continuously reduced to stop the output of the internal power supply voltage.

Further, the semiconductor integrated circuit according to the present invention is
2. The differential amplifier according to claim 1, wherein the second internal power supply circuit unit supplies the output power supply voltage and a predetermined reference voltage to the differential amplifier, and supplies the internal power supply voltage according to the output voltage of the differential amplifier. An output circuit section for changing an output current for performing the operation, a cutoff control circuit section for cutting off an output to the outside with respect to an output current from the output circuit section when a predetermined signal is input from the outside, and a cutoff control circuit section. When the output current is interrupted, a bypass circuit for bypassing the output voltage of the output circuit for a predetermined time and reducing the rise of the output voltage is provided.

Further, a semiconductor integrated circuit according to the present invention comprises:
7. The power supply circuit according to claim 6, wherein the second internal power supply circuit further includes a voltage application circuit that applies an external power supply voltage to the output of the second internal power supply circuit for a predetermined time when the output current is cut off by the cutoff control circuit. Things.

Further, the semiconductor integrated circuit according to the present invention is
An internal power supply circuit section that generates a predetermined voltage based on a power supply voltage applied from the outside and supplies the generated voltage to each circuit; and, when a predetermined signal is input, an output voltage from the internal power supply circuit section to each circuit. An output switching circuit section for interrupting the supply and supplying a predetermined voltage applied from the outside to each circuit, wherein the output switching circuit section outputs an output current from the internal power supply circuit section when a predetermined signal is input. To reduce the output voltage from the internal power supply circuit.

Further, a semiconductor integrated circuit according to the present invention is
9. A plurality of output switching circuit units according to claim 8, wherein the output switching circuit unit outputs each signal generated by delaying the input signal at a different time, and the plurality of operation control units are controlled by the respective delay signals output from the delay circuit unit. An internal voltage control circuit unit for controlling the output of the output voltage from the internal power supply circuit unit to each circuit, and a plurality of MOs whose operations are controlled by the respective delay signals output from the delay circuit unit.
An external voltage control circuit unit comprising an S transistor and controlling output of a voltage applied from the outside to each circuit;
When a predetermined signal is input, the delay circuit unit sequentially turns off each MOS transistor of the internal voltage control circuit unit to make it nonconductive, and at the same time, each MOS transistor of the external voltage control circuit unit.
The transistors are turned on in order to make them conductive, and the output current output from the internal power supply circuit is gradually reduced to cut off the output to the outside, and the current input from the outside is gradually increased to reduce the external current. Is supplied to each circuit.

Further, a semiconductor integrated circuit according to the present invention comprises:
In any one of claims 8 and 9, the internal power supply circuit section is an internal power supply step-down circuit that steps down a power supply voltage supplied from the outside, generates a predetermined internal power supply voltage, and supplies the generated internal power supply voltage to each circuit.

Further, a semiconductor integrated circuit according to the present invention comprises:
10. The substrate voltage according to claim 8, wherein the internal power supply circuit generates and outputs a bias voltage for the semiconductor substrate from a power supply voltage supplied from the outside, and applies a predetermined substrate voltage to the semiconductor substrate. It is a generating circuit.

Further, a semiconductor integrated circuit according to the present invention
In any one of claims 8 and 9, the internal power supply circuit section is a boosted voltage generation circuit that boosts a power supply voltage supplied from the outside to generate a predetermined boosted voltage and supplies the boosted voltage to each circuit.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG.
1 is a circuit diagram showing an example of a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, the DRA
The internal power supply step-down circuit used in M is shown as an example.

In FIG. 1, an internal power supply step-down circuit 1 steps down an external power supply voltage Vcc supplied from a power supply terminal to generate an internal power supply voltage int.Vcc, and supplies it to each internal circuit of the semiconductor integrated circuit. Things. In a DRAM, the current consumption is extremely small in a standby state only for holding data stored in the memory. In the standby state, the memory activates the current capacity of the internal power supply supplied from the internal power supply step-down circuit 1 to each unit. Make it much smaller than in the state.

From this, the internal power supply step-down circuit 1 is provided with a standby step-down power supply circuit (hereinafter, referred to as a small step-down power supply circuit) having a small current supply capability.
A standby VDC 2 and an active step-down power supply circuit (hereinafter referred to as active
C) and a reference voltage generating circuit 4 for generating and outputting a reference voltage Vref. Standby V
In the DC2 and the active VDC3, the voltage value of the internal power supply voltage int.Vcc is determined by the reference voltage Vref input from the reference voltage generation circuit 4. That is, the internal power supply step-down circuit 1 controls and outputs the voltage value of the internal power supply voltage int.Vcc so as to be the reference voltage Vref input from the reference voltage generation circuit 4. Note that the standby VDC 2
Constitutes a first internal power supply circuit, and the active VDC 3 constitutes a second internal power supply circuit.

The standby VDC 2 is connected to the differential amplifier 11
And a p-channel MOS transistor (hereinafter, referred to as a pMOS transistor) 12. In the standby VDC 2, the output of the differential amplifier 11 is pM
The gate of the OS transistor 12 is connected, the drain of the pMOS transistor 12 is connected to the non-inverting input of the differential amplifier 11, and the connection forms the output of the standby VDC 2. Further, the inverting input of the differential amplifier 11 is
The reference voltage Vref is input to the reference voltage generation circuit 4, the source of the pMOS transistor 12 is connected to the power supply terminal, and the power supply voltage Vcc is applied.

The active VDC 3 is a differential amplifier 1
5, pMOS transistors 16 to 20, n-channel type M
An OS transistor (hereinafter, referred to as an nMOS transistor) 21 to 23 and a delay circuit 25 are formed. The output of the differential amplifier 15 is the gate of the pMOS transistor 16, the source of the pMOS transistor 17, and the nMOS
The differential amplifier 15 is connected to the source of the transistor 21.
Is connected to the reference voltage generation circuit 4 and receives the reference voltage Vref. pMOS transistor 16
And the drain of the nMOS transistor 21
The power supply terminal is connected to the power supply voltage Vcc, and pMO
The drain of the S transistor 16 is connected to the non-inverting input of the differential amplifier 15, and the gate of the nMOS transistor 21 is connected to the delay circuit 25.

The gates of the pMOS transistor 17 and the nMOS transistor 22 are connected to each other, and the connection is connected to the delay circuit 25. The drain of the pMOS transistor 17 and the nMOS transistor 2
2 are connected to each other, and the connection is connected to the gate of the pMOS transistor 18. The source of the pMOS transistor 18 and the drain of the nMOS transistor 22 are connected to a power supply terminal, respectively, to which a power supply voltage Vcc is applied. The gate of the pMOS transistor 18
Further, the source of the pMOS transistor 19 is connected,
The drain of the MOS transistor 18 is connected to the non-inverting input of the differential amplifier 15.

The gates of the pMOS transistor 19 and the nMOS transistor 23 are connected to each other, and the connection is connected to the delay circuit 25. The drain of the pMOS transistor 19 and the source of the nMOS transistor 23 are connected.
Connected to the gate. pMOS transistor 20
And the drain of the nMOS transistor 23 are connected to a power supply terminal, respectively, to which a power supply voltage Vcc is applied.

The drain of the pMOS transistor 20 is connected to the non-inverting input of the differential amplifier 15, and the drains of the pMOS transistors 16, 18, and 20 are connected to the differential amplifier 15
Is connected to the output of the active VDC 3 and is connected to the output of the standby VDC 2 to form the output of the internal power supply step-down circuit 1. Note that p
The MOS transistors 16 to 20 and the nMOS transistors 21 to 23 form an output circuit.

FIG. 2 is a diagram showing a circuit example of the delay circuit 25. In FIG. 2, the delay circuit 25 includes inverter circuits 31 to 36 and capacitors 37 to 42. The inverter circuits 31 to 36 are connected in series, an input of the inverter circuit 31 forms an input of the delay circuit 25, and an external row address strobe signal (hereinafter, //).
RAS signal) is input to an external input terminal / RAS
(Hereinafter, referred to as a / RAS terminal).

The connection between the output of the inverter circuit 31 and the input of the inverter circuit 32 is connected to a power supply terminal to which a power supply voltage Vcc is applied via a capacitor 37 and is grounded via a capacitor 38. The output of the inverter circuit 32 is connected to the input of the inverter circuit 33 and to the gates of the pMOS transistor 19 and the nMOS transistor 23 in FIG. 1, and outputs a signal φ1 obtained by delaying the / RAS signal. In addition, / in / RAS indicates the inversion of the signal level, and indicates that the signal is low active.

The connection between the output of the inverter circuit 33 and the input of the inverter circuit 34 is connected to the power supply terminal to which the power supply voltage Vcc is applied via the capacitor 39 and is grounded via the capacitor 40. The output of the inverter circuit 34 is connected to the input of the inverter circuit 35 and to the gates of the pMOS transistor 17 and the nMOS transistor 22 in FIG. 1, and outputs a signal φ2 obtained by delaying the signal φ1. Similarly, the inverter circuit 3
The connection between the output of the inverter 5 and the input of the inverter circuit 36 is connected to a power supply terminal to which the power supply voltage Vcc is applied via a capacitor 41 and is grounded via a capacitor 42. The output of the inverter circuit 36 is the nMOS of FIG.
It is connected to the gate of transistor 21 and outputs signal φ3 obtained by delaying signal φ2.

FIG. 3 is a timing chart showing an operation example of the delay circuit 25 shown in FIG. An operation example of the internal power supply step-down circuit 1 will be described with reference to FIGS.
As can be seen from FIG. 3, for the change in the signal level of the / RAS signal, the signal φ1 has the smallest delay, the signal φ2 has the smallest delay, and the signal φ3 has the largest delay.
/ RAS signal is high and signals φ1 to φ3 are high
In the standby state at the h level, the nMOS transistors 21 to 23 are turned on to be in a conductive state.
The MOS transistors 16, 18, and 20 are turned off and become non-conductive, and the pMOS transistors 17 and 19 are turned off and become non-conductive. From this, the active V
The supply of the internal power supply voltage int.Vcc from the DC3 is stopped, and the supply of the internal power supply voltage int.Vcc is performed only from the standby VDC2.

Next, when the / RAS signal falls from the high level to the low level and changes from the standby state to the active state, first, the signal φ1 falls from the high level to the low level and the pMOS transistor 19 turns on. At the same time, the nMOS transistor 23 is turned off and becomes non-conductive. Subsequently, the signal φ2 falls from the high level to the low level, and the pMOS transistor 17 is turned on to turn on, and the nMOS transistor 22 is turned off to turn off.

Subsequently, the signal φ3 falls from the high level to the low level, and the nMOS transistor 21 is turned off and turned off, so that the pMOS transistor 16 is turned on and the pMOS transistor 16,
The internal power supply voltage int.Vcc is supplied from 18 and 20.

Here, when the / RAS signal rises from the Low level to the High level and changes from the active state to the standby state, first, the signal φ1 rises from the Low level to the High level and the pMOS transistor 19 is turned off and non-conductive. State and nMOS
Since the transistor 23 is turned on and becomes conductive,
The pMOS transistor 20 turns off and becomes non-conductive. At this point, the internal power supply voltage int.Vcc has been supplied from the pMOS transistors 16 and 18. afterwards,
Since the signal φ2 rises from the Low level to the High level, the pMOS transistor 17 is turned off and turned off, and the nMOS transistor 22 is turned on and turned on, so that the pMOS transistor 18 is turned off and turned off. Become. At this point, the internal power supply voltage int.
Vcc is supplied only from the pMOS transistor 16.

Thereafter, the signal φ3 rises from the Low level to the High level, and the nMOS transistor 21 is turned on and turned on. Therefore, the pMOS transistor 16 is turned off and turned off, and the internal voltage from the active VDC 3 is reduced. The supply of the power supply voltage int.Vcc stops, and the internal power supply voltage int.V only from the standby VDC2.
Supply of cc is performed. As described above, when transitioning from the active state to the standby state, the active VDC 3
When the supply of the internal power supply voltage int.Vcc from the
The MOS transistors 16, 18, and 20 are sequentially turned off to gradually decrease the output current from the active VDC 3, thereby stopping the supply of the internal power supply voltage int.Vcc.

As described above, in the semiconductor integrated circuit according to the first embodiment, when the internal power supply voltage down converter 1 is in the active state, the pMOS transistor 12 of the standby VDC 2 and the pMOS transistors 16, 18, and 20 of the active VDC 3 The internal power supply voltage int.Vcc is supplied, and the active VDC 3
When the supply of the internal power supply voltage int.Vcc from the
The MOS transistors 16, 18, and 20 are sequentially turned off to gradually reduce the output current from the active VDC 3 and cut off the internal power supply voltage from the active VDC 3.
The supply of int.Vcc was stopped. Thus, when shifting from the active state to the standby state, it is possible to prevent the occurrence of noise with respect to the power supply voltage Vcc when performing the cutoff control of the output current, thereby improving the reliability.

Embodiment 2 In the first embodiment, a pMOS for supplying an output current in the active VDC 3
The output current from the active VDC 3 is reduced stepwise by providing a plurality of transistors.
The pMOS transistor that supplies the output current at
In the meantime, the output current output from the pMOS transistor may be cut off or output stepwise, and this is referred to as a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 4, an internal power supply step-down circuit used in a DRAM is shown as an example, and the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted and only the differences from FIG. 1 will be described. . 4 is different from FIG. 1 in that the circuit configuration of the active VDC 3 in FIG. 1 is changed. Therefore, the active VDC 3 in FIG.
1, and the internal power supply step-down circuit 1 of FIG.

In FIG. 4, the internal power supply step-down circuit 55
A standby VDC 2 having a small current supply capability, an active VDC 51 having a large current supply capability, and a reference voltage V
and a reference voltage generating circuit 4 for generating and outputting ref. VDC2 for standby and VD for active
In C51, the voltage value of the internal power supply voltage int.Vcc is determined by the reference voltage Vref input from the reference voltage generation circuit 4, and the internal power supply step-down circuit 55 becomes the reference voltage Vref input from the reference voltage generation circuit 4. Thus, the voltage value of the internal power supply voltage int.Vcc is controlled and output. The active VDC 51 forms a second internal power supply circuit.

The active VDC 51 is a differential amplifier 1
5, pMOS transistors 61 to 63 and delay circuit 64
It is formed with. The output of the differential amplifier 15 is a pMOS
The drain of the pMOS transistor 61 is connected to the non-inverting input of the differential amplifier 15, and the connection is connected to the sources of the pMOS transistors 62 and 63. The inverting input of the differential amplifier 15 is connected to the reference voltage generation circuit 4 to receive the reference voltage Vref, the source of the pMOS transistor 61 is connected to the power supply terminal, and the power supply voltage Vcc is applied.

In the pMOS transistors 62 and 63, each gate is connected to the delay circuit 64, and each drain is connected to form the output of the active VDC 51, and is connected to the output of the standby VDC 2, and Represents the output of the internal power supply voltage down converter 55. As the pMOS transistor 62, a transistor whose current supply capability is sufficiently larger than that of the pMOS transistor 63 is used. The pMOS transistor 61 forms an output circuit, and the pMOS transistors 62 and 63 and the delay circuit 64 form a cutoff control circuit.

FIG. 5 is a diagram showing a circuit example of the delay circuit 64. In FIG. 5, the delay circuit 64 includes inverter circuits 71 to 74 and capacitors 75 to 78. The inverter circuits 71 to 74 are connected in series. The input of the inverter circuit 71 forms the input of the delay circuit 64, and is connected to the / RAS terminal to which the / RAS signal is input from the outside. The connection between the output of the inverter circuit 71 and the input of the inverter circuit 72 is connected to a power supply terminal to which the power supply voltage Vcc is applied via a capacitor 75 and is grounded via a capacitor 76.

The output of the inverter circuit 72 is connected to the input of the inverter circuit 73 and to the gate of the pMOS transistor 62 shown in FIG. 4, and outputs a signal φ4 obtained by delaying the / RAS signal. The connection between the output of the inverter circuit 73 and the input of the inverter circuit 74 is connected to a power supply terminal to which the power supply voltage Vcc is applied via a capacitor 77 and is grounded via a capacitor 78.
The output of the inverter circuit 74 is connected to the gate of the pMOS transistor 63 in FIG. 4, and outputs a signal φ5 obtained by delaying the signal / RAS.

In such a configuration, the active V
An operation example of the DC 51 will be described. The delay circuit 6
The timing chart showing the operation example 4 is the same as that of FIG. 3 except that the signal φ1 is changed to the signal φ4, the signal φ2 is changed to the signal φ5, and the signal φ3 is eliminated. The signal φ4 has a smaller delay amount than the signal φ5 with respect to the change in the signal level of the / RAS signal. In the standby state in which the / RAS signal is at the high level and the signals φ4 and φ5 are both at the high level, the pMOS transistors 62 and 63 are both turned off and become non-conductive. Therefore, the supply of the internal power supply voltage int.Vcc from the active VDC 51 is stopped, and the internal power supply voltage int.V only from the standby VDC 2 is stopped.
Supply of cc is performed.

Next, when the / RAS signal falls from the high level to the low level and changes from the standby state to the active state, first, the signal φ4 falls from the high level to the low level and the pMOS transistor 62 turns on. Turns on and the internal power supply voltage int.
Vcc supply begins. After that, the signal φ5 falls from the High level to the Low level, the pMOS transistor 63 is turned on and becomes conductive, and the internal power supply voltage int.Vcc is supplied via the pMOS transistors 62 and 63.

Here, when the / RAS signal rises from the low level to the high level and changes from the active state to the standby state, first, the signal φ4 rises from the low level to the high level, and the pMOS transistor 62 is turned off to turn off. After that, the signal φ5 rises from the Low level to the High level, and the pMOS transistor 63 is turned off to be in a non-conductive state. In this way, the supply of the internal power supply voltage int.Vcc from the active VDC 51 is stopped, and the standby VDD
The internal power supply voltage int.Vcc is supplied only from C2.

As described above, the semiconductor integrated circuit according to the second embodiment has a current supply capability when the supply of the internal power supply voltage int.Vcc from the active VDC 51 is stopped when shifting from the active state to the standby state. Of the internal power supply voltage int.Vcc by turning off the pMOS transistor 62 having a large current and turning off the pMOS transistor 63 having a small current supply capability to gradually reduce the output current from the active VDC 51. Was stopped. This makes it possible to prevent the occurrence of noise with respect to the power supply voltage Vcc when performing the cutoff control of the output current when shifting from the active state to the standby state, thereby improving reliability.

Embodiment 3 In the first and second embodiments, when transitioning from the active state to the standby state, the output current from the active VDC is gradually reduced and cut off, but the output current from the active VDC is reduced. It is also possible to cut off continuously by reducing it. Such a configuration is referred to as a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a semiconductor integrated circuit according to the third embodiment of the present invention. In FIG. 6, an internal power supply step-down circuit used in a DRAM is shown as an example, and the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here, and only different points from FIG. 1 will be described. . 6 is different from FIG. 1 in that the circuit configuration of the active VDC 3 of FIG. 1 is changed. Therefore, the active VDC 3 of FIG.
1, and accordingly, the internal power supply step-down circuit 1 of FIG.

In FIG. 6, the internal power supply step-down circuit 85
A standby VDC 2 having a small current supply capability, an active VDC 81 having a large current supply capability, and a reference voltage V
and a reference voltage generating circuit 4 for generating and outputting ref. VDC2 for standby and VD for active
In C81, the voltage value of the internal power supply voltage int.Vcc is determined by the reference voltage Vref input from the reference voltage generation circuit 4, and the internal power supply step-down circuit 85 becomes the reference voltage Vref input from the reference voltage generation circuit 4. Thus, the voltage value of the internal power supply voltage int.Vcc is controlled and output. The active VDC 81 forms a second internal power supply circuit.

The active VDC 81 is a differential amplifier 1
5, an inverter circuit 91, a pMOS transistor 92,
93, capacitors 94 and 95, and a resistor 96. The output of the differential amplifier 15 is connected to the gate of the pMOS transistor 92 and the drain of the pMOS transistor 93. In the pMOS transistor 92, the source is connected to the power supply terminal and the power supply voltage Vcc is applied, the drain is connected to the non-inverting input of the differential amplifier 15, and the connection forms the output of the active VDC 81 and the standby VDC2. Connected to the output of the internal power supply step-down circuit 85.

The input of the inverter circuit 91 is / RA
The output of the inverter circuit 91 is connected to the gate of the pMOS transistor 93 via the resistor 96. Further, in the pMOS transistor 93, the gate is connected to a power supply terminal via a capacitor 94, to which the power supply voltage Vcc is applied and grounded via a capacitor 95, and the source is connected to the power supply terminal, and the power supply voltage Vcc is Has been applied. The inverter circuit 91, the pMOS transistors 92 and 93, the capacitor 9
4, 95 and the resistor 96 form an output circuit section.

In such a configuration, in the active state, a low-level / RAS signal is input from the / RAS terminal, the pMOS transistor 93 is turned off and becomes non-conductive, and the pMOS transistor 92 of the active VDC 81 and the standby VDC 2 Of the internal power supply voltage int.V
cc is output. Here, when transitioning from the active state to the standby state, a high level //
When the RAS signal is input, the gate voltage of the pMOS transistor 93 gradually decreases and the gate voltage of the pMOS transistor 92 gradually increases according to the time constant of the capacitor 95 and the resistor 96. As a result, the current supplied from the pMOS transistor 92 continuously decreases, and then the current supply from the pMOS transistor 92 stops, and the current is supplied only from the standby VDC 2 to output the internal power supply voltage int.Vcc. You.

Next, when transitioning from the standby state to the active state, a low-level / RAS signal is input from the / RAS terminal, the gate voltage of the pMOS transistor 93 gradually increases, and the pMOS transistor 93 is turned off and cut off. The operation of the pMOS transistor 92 is controlled by the output voltage from the differential amplifier 15, the output current is supplied, and the internal power supply voltage int.Vcc is output. In this way, currents are output from the standby VDC 2 and the active VDC 81, respectively, and the internal power supply voltage
int.Vcc is output.

As described above, when the semiconductor integrated circuit according to the third embodiment shifts from the active state to the standby state, the output current from the active VDC 81 is continuously reduced and cut off, and The supply of the internal power supply voltage int.Vcc was stopped. From this, when shifting from the active state to the standby state, it is possible to prevent the occurrence of noise with respect to the power supply voltage Vcc when performing the cutoff control of the output current,
Reliability can be improved.

Embodiment 4 In the first to third embodiments, noise is not generated when the current supply from the active VDC is stopped. However, the noise generated when the current supply from the active VDC is stopped is supplied to the power supply. A bypass circuit may be provided so as not to affect the voltage Vcc, and such a circuit is referred to as a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing an example of a semiconductor integrated circuit according to the fourth embodiment of the present invention. In FIG. 7, an internal power supply step-down circuit used in a DRAM is shown as an example, and the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here, and only different points from FIG. 1 will be described. . 7 is different from FIG. 1 in that the circuit configuration of the active VDC 3 in FIG. 1 is changed. Therefore, the active VDC 3 in FIG.
01, and accordingly, the internal power supply step-down circuit 1 of FIG.

In FIG. 7, internal power supply step-down circuit 105
Comprises a standby VDC 2 having a small current supply capability, an active VDC 101 having a large current supply capability, and a reference voltage generating circuit 4 for generating and outputting a reference voltage Vref. In the standby VDC 2 and the active VDC 101, the internal power supply voltage int.Vcc is supplied by the reference voltage Vref input from the reference voltage generation circuit 4.
Is determined, and the internal power supply step-down circuit 105 controls and outputs the voltage value of the internal power supply voltage int.Vcc so that the reference voltage Vref input from the reference voltage generation circuit 4 is obtained. The active VDC 101 forms a second internal power supply circuit.

The active VDC 101 includes a differential amplifier 15, pMOS transistors 111 to 114, a resistor 11
5, 116 and a one-shot pulse generation circuit 117. The output of the differential amplifier 15 is connected to the gate of the pMOS transistor 111, the drain of the pMOS transistor 111 is connected to the non-inverting input of the differential amplifier 15, and the connection is made to the pMOS transistor 112
, And 113. In the pMOS transistor 113, the drain is grounded via the resistor 115, and the gate is the one-shot pulse generation circuit 11
7 is connected to the output. The inverting input of the differential amplifier 15 is connected to the reference voltage generating circuit 4 to receive the reference voltage Vref, the source of the pMOS transistor 111 is connected to the power supply terminal, and the power supply voltage Vcc is applied.

In the pMOS transistor 112, the gate is connected to the / RAS terminal, the drain is connected to the drain of the pMOS transistor 114, and the connection is
The output of the active VDC 101 and the output of the internal power supply step-down circuit 1 connected to the output of the standby VDC 2
05 is output. pMOS transistor 114
In FIG. 7, the source is connected to the power supply terminal via the resistor 116, the power supply voltage Vcc is applied, and the gate is connected to the output of the one-shot pulse generation circuit 117.

The one-shot pulse generation circuit 117
Is connected to the / RAS terminal. Note that pMO
The S transistor 111 forms an output circuit section, the pMOS transistor 112 forms a cutoff control circuit section, and the pMOS transistor 113, the resistor 115, and the one-shot pulse generation circuit 117 form a bypass circuit. Furthermore, pMOS
The transistor 114, the resistor 116, and the one-shot pulse generation circuit 117 form a voltage application circuit.

In such a configuration, when the / RAS signal is at the high level in the standby state, the pMOS
The transistors 112 to 114 are turned off and are turned off. For this reason, the supply of the internal power supply voltage int.Vcc from the active VDC 101 is stopped, and the standby VDD
The internal power supply voltage int.Vcc is supplied only from C2.
Next, when the / RAS signal falls from the High level to the Low level and changes from the standby state to the active state, the pMOS transistor 112 is turned on and becomes conductive, and the internal power supply voltage int. Feeding takes place.

Here, when the / RAS signal rises from the low level to the high level and changes from the active state to the standby state, the one-shot pulse generation circuit 117 outputs a low-level one-shot pulse signal, and the pMOS transistor 112 The pMOS transistors 113 and 114 are turned on and turned on while the one-shot pulse signal is being input from the one-shot pulse generation circuit 117, while being turned off and turned off. When the one-shot pulse signal is no longer input from the one-shot pulse generation circuit 117, the pMOS transistors 113 and 114 are turned off again and become non-conductive.

As described above, the pMOS transistor 112
Is turned off and becomes non-conductive, the pMOS transistor 113 is turned on for a predetermined time,
The connection between the drain of the transistor 111 and the source of the pMOS transistor 112 is grounded via a resistor 115, and the pMOS transistor 114 is turned on for a predetermined period, so that the output of the active VDC 101 is connected to the power supply voltage Vcc via a resistor 116. It was applied.

As described above, in the semiconductor integrated circuit according to the fourth embodiment, when the supply of the internal power supply voltage int.Vcc from the active VDC 101 is stopped when shifting from the active state to the standby state, the pMOS transistor 113 is used. By turning on for a predetermined time, pM
The connection between the drain of the OS transistor 111 and the source of the pMOS transistor 112 is grounded via a resistor 115, and the pMOS transistor 114 is turned on for a predetermined period, whereby the output of the active VDC 101 is connected to the power supply voltage Vcc via a resistor 116. Was applied.
Therefore, when the pMOS transistor 112 is turned off, the generated noise can be bypassed to the ground and the internal power supply voltage int.Vcc output from the internal power supply voltage down circuit 105 can be prevented from lowering. At the time of transition from the active state to the standby state, it is possible to prevent generation of noise with respect to the power supply voltage Vcc at the time of performing output current cutoff control, thereby improving reliability.

Embodiment 5 In the first to fourth embodiments, the influence of noise generated in the internal power supply step-down circuit during normal operation is prevented.
A fifth embodiment of the present invention is directed to an internal power supply circuit of a semiconductor integrated circuit in which the influence of noise generated when shifting from a normal operation mode to a test mode is prevented. FIG. 8 is a schematic block diagram showing a circuit example of a semiconductor integrated circuit according to the fifth embodiment of the present invention. In addition,
FIG. 8 shows an example of an internal power supply circuit used in a DRAM, and the internal power supply step-down circuit in the internal power supply circuit is shown as an example of the internal power supply step-down circuit 1 of the first embodiment. The same applies to each of the internal power supply step-down circuits according to the second to fourth embodiments, and a description thereof will be omitted.

In FIG. 8, an internal power supply circuit 120 includes an internal power supply step-down circuit 1, a substrate voltage generation circuit 121 for generating and outputting a bias voltage for the semiconductor substrate and applying a negative substrate voltage Vbb to the semiconductor substrate, and a power supply terminal. A boosted voltage generating circuit 122 and an output switching circuit 12 which boost a supplied external power supply voltage Vcc to generate a boosted voltage Vpp and supply it to each section.
3 to 125 are provided. Output switching circuits 123 to 125 are connected to the outputs of the internal power supply step-down circuit 1, the substrate voltage generation circuit 121, and the boosted voltage generation circuit 122, respectively.

The output switching circuit 123 is connected to an external input terminal I1 to which the output of the internal power supply step-down circuit 1 and the power supply voltage Vcc are applied.
The output switching circuit 124 switches between the output of the substrate voltage generating circuit 121 and an external input terminal I2 to which a predetermined voltage is applied from the outside.
Switches between the output of the boosted voltage generation circuit 122 and an external input terminal I3 to which a predetermined voltage is applied from the outside. The output switching circuit 123 operates during the normal operation.
The internal power supply voltage int.Vcc output from the circuit is output to each circuit, and a predetermined test mode signal TEST (hereinafter, TEST) is output.
When this signal is input, the power supply voltage Vcc applied to the external input terminal I1 is output to each circuit instead of the internal power supply voltage int.Vcc output from the internal power supply voltage step-down circuit 1.

The output switching circuit 124 outputs the substrate voltage Vbb output from the substrate voltage generation circuit 121 to each circuit during normal operation, and outputs a predetermined voltage from the substrate voltage generation circuit 121 when a predetermined TEST signal is input. Substrate voltage Vbb
Instead, a voltage externally applied to the external input terminal I2 is output to each circuit. The output switching circuit 125 outputs the boosted voltage Vpp output from the boosted voltage generation circuit 122 to each circuit during normal operation, and outputs the boosted voltage Vpp from the boosted voltage generation circuit 122 when a predetermined TEST signal is input. A voltage externally applied to the external input terminal I3 instead of the boosted voltage Vpp is output to each circuit.

FIG. 9 is a circuit diagram showing a circuit example of the output switching circuit 123. In FIG. 9, the output switching circuit 123
Are nMOS transistors 131 to 136, inverter circuits 137 to 139, a diode 140, and a delay circuit 1
41. The output of the internal power supply step-down circuit 1 is connected to the anode of the diode 140,
The drains of the S transistors 131 to 133 are respectively connected, and the connection is connected to the cathode of the diode 140. The sources of the nMOS transistors 131 to 136 are connected to each other, and the connection forms the output of the output switching circuit 123 and the output of the internal power supply circuit 120.

The nMOS transistors 134 to 13
6 are connected to each other, and the connection is connected to the external input terminal I1. nMOS transistor 1
The inverter circuits 137 to 1 are provided at the gates of 31 to 133, respectively.
39 are connected correspondingly, and the inverter circuit 137 is connected.
To 139 and the nMOS transistor 134 to
Each gate of 136 is connected to the delay circuit 141. The nMOS transistors 131 to 133, the inverter circuits 137 to 139, and the diode 140 form an internal voltage control circuit, and the nMOS transistors 134 to 133
136 is an external voltage control circuit unit. Also, delay circuit 1
41 is the same circuit as the delay circuit 25 shown in FIG.
Since the TEST signal is input to the input of the delay circuit 25, the description of the circuit example of the delay circuit 141 is omitted.

The delay circuit 141 outputs signals φ6 to φ8 in response to an input signal, and the signal φ6 has the smallest delay and the signal φ7 has the smallest delay in response to a change in the signal level of the input signal. , The signal φ8 has the largest delay amount. nMOS
The gate of the transistor 134 and the inverter circuit 137
, The signal φ6 is input from the delay circuit 141, the gate of the nMOS transistor 135 and the input of the inverter circuit 138 are input with the signal φ7 from the delay circuit 141, and the gate of the nMOS transistor 136 and the input of the inverter circuit 139. Has a delay circuit 14
Signals .phi.8 are input from 1 respectively. The signal φ6 corresponds to the signal φ1 in FIG. 2, the signal φ7 corresponds to the signal φ2 in FIG. 2, and the signal φ8 corresponds to the signal φ3 in FIG.

During normal operation, for example, a low-level signal is input to the input of the delay circuit 141, and the low-level signals φ6 to φ8 are output from the delay circuit 141. From this, the nMOS transistor 131
133 turn on to turn on, and the nMOS transistors 134 to 136 turn off to turn off. Therefore, the output switching circuit 123 outputs the internal power supply voltage int.Vcc output from the internal power supply step-down circuit 1.

Here, when changing from the normal operation to the test mode operation, for example, a high level TEST signal is input to the delay circuit 141. The input of the delay circuit 141 is L
When the signal φ6 rises from the low level to the high level, first, the signal φ6 rises from the low level to the high level, and the nMOS transistor 131 is turned off and turned off, and the nMOS transistor 134 is turned on and turned on.

Subsequently, the signal φ7 changes from the low level to the high level.
After rising to the h level, the nMOS transistor 132
Is turned off to turn off, and the nMOS transistor 135 turns on to turn on. Subsequently, the signal φ8 rises from the Low level to the High level, the nMOS transistor 133 is turned off and turned off, and the nMOS transistor 136 is turned on and turned on.
The power supply voltage Vcc applied to the external input terminal I1 is output instead of int.Vcc.

When the operation changes from the test mode operation to the normal operation, the input of the delay circuit 141 is changed from the high level to the low level.
The signal φ6 first falls from a high level to a low level, turning on the nMOS transistor 131 to turn on, and turning off the nMOS transistor 134 to turn off.

Subsequently, the signal φ7 changes from the High level to the Lo level.
The nMOS transistor 132 falls to the w level.
Is turned on to turn on, and the nMOS transistor 135 is turned off to turn off. Subsequently, the signal φ8 falls from the high level to the low level, and the nMOS transistor 133 is turned off and turned off, and the nMOS transistor 136 is turned on and turned on. Voltage
int.Vcc is output.

The output switching circuits 124 and 125
Since the output switching circuit 123 is basically the same as the output switching circuit 123, the description thereof is omitted. However, in the output switching circuit 124,
When the voltage applied to the external input terminal I2 is higher than the substrate voltage Vbb, a diode is connected to the output of the substrate voltage generating circuit 121 in the forward direction similarly to the output switching circuit 123, and the voltage applied to the external input terminal I2 Is smaller than the substrate voltage Vbb, the voltage applied from the external input terminal I2 is applied to the nMOS transistors 134 to 136 via the diodes.
Is applied to each drain.

Similarly, in the output switching circuit 125, when the voltage applied to the external input terminal I3 is higher than the boosted voltage Vpp, a diode is connected to the output of the boosted voltage generating circuit 122 in the forward direction similarly to the output switching circuit 123. If the voltage applied to the external input terminal I3 is smaller than the boosted voltage Vpp, the voltage applied from the external input terminal I3 is applied to the drains of the nMOS transistors 134 to 136 via diodes. .

As described above, the semiconductor integrated circuit according to the fifth embodiment outputs from internal power supply voltage down converter 1, substrate voltage generating circuit 121, and boosted voltage generating circuit 122 when shifting from the normal operation to the test mode operation. Each output current is gradually reduced and cut off, and each input current input from each of the external input terminals I1 to I3 is gradually increased so that the internal power supply voltage int.
bb and the boosted voltage Vpp are respectively switched to corresponding predetermined externally input voltages and output from the internal power supply circuit 120. From this, when shifting from the normal operation to the test mode operation, generation of noise with respect to the power supply voltage Vcc at the time of performing cutoff control of each output current from the internal power supply step-down circuit, the substrate voltage generation circuit, and the boost voltage generation circuit. Can be prevented, and the reliability can be improved.

[0092]

According to the first aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
When the internal power supply voltage is supplied from the internal power supply circuit section and the second internal power supply circuit section, and the supply of the internal power supply voltage from the second internal power supply circuit section is stopped, the output current from the second internal power supply circuit section is stepped. Then, the supply of the internal power supply voltage from the second internal power supply circuit unit is stopped.
From this, when the current consumption of each circuit supplying the internal power supply voltage becomes small, the power supply voltage or the like when the cutoff control of the output current from the second internal power supply circuit part having a large current supply capability is performed. Generation of noise can be prevented, and reliability can be improved.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the second internal power supply circuit section includes a differential amplifier, a delay circuit section, and an output circuit section. When the current consumption of each circuit to which the internal power supply voltage is supplied decreases, a predetermined signal is input from the outside, and the output circuit unit responds to each delay signal having a different delay amount output from the delay circuit unit. Thus, the output current is reduced stepwise to stop the output of the internal power supply voltage. From this,
When the current consumption of each circuit that supplies the internal power supply voltage decreases, the generation of noise with respect to the power supply voltage or the like when the cutoff control of the output current from the second internal power supply circuit part having a large current supply capability is performed. Can be prevented, and the reliability can be improved.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the second internal power supply circuit section includes a differential amplifier, an output circuit section, and a cutoff control circuit section. When a predetermined signal input from the outside is input when the current consumption of each circuit to which the internal power supply voltage is supplied becomes small, the output current output from the output circuit unit is gradually changed. The output was cut off to reduce the output. From this, when the current consumption of each circuit supplying the internal power supply voltage becomes small, the power supply voltage or the like when the cutoff control of the output current from the second internal power supply circuit part having a large current supply capability is performed. Generation of noise can be prevented, and reliability can be improved.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, the cutoff control circuit section includes a delay circuit section and a plurality of MOS transistors having different gate sizes, and the delay circuit section includes: Each of the MOS transistors is turned on to make it conductive, and the output current from the output circuit section is output to each circuit. When the above-mentioned predetermined signal is input from the outside, the MOS transistors with the largest drain current are turned off in order to turn off. In this state, the output current output from the output circuit unit is reduced in a stepwise manner to cut off output to the outside. From this, when the current consumption of each circuit supplying the internal power supply voltage becomes small, the power supply voltage or the like when the cutoff control of the output current from the second internal power supply circuit part having a large current supply capability is performed. Generation of noise can be prevented, and reliability can be improved.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the second internal power supply circuit section includes a differential amplifier and an output circuit section, and the output circuit section includes an internal power supply voltage. When a predetermined signal that is input from the outside is input when the current consumption of each circuit in which the power supply is performed is reduced, the output current is continuously reduced so that the output of the internal power supply voltage is stopped. did. From this, when the current consumption of each circuit supplying the internal power supply voltage becomes small, the power supply voltage or the like when the cutoff control of the output current from the second internal power supply circuit part having a large current supply capability is performed. Generation of noise can be prevented, and reliability can be improved.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the second internal power supply circuit section includes a differential amplifier and an internal power supply voltage corresponding to an output voltage of the differential amplifier. An output circuit section for changing an output current for supplying
A cut-off control circuit that cuts off an output to the outside with respect to an output current from the output circuit when a predetermined signal is input from outside; and an output voltage of the output circuit when the cut-off control circuit cuts off the output current. A bypass circuit that bypasses for a predetermined time and reduces the rise of the output voltage. For this reason, it is possible to bypass generated noise to the ground when performing the cutoff control of the output current from the second internal power supply circuit unit having a large current supply capability, and to supply the internal power supply voltage to each circuit. When the current consumption becomes smaller, it is possible to prevent the occurrence of noise with respect to the power supply voltage and the like when performing the cutoff control of the output current from the second internal power supply circuit unit having a large current supply capability, thereby improving the reliability. Can be planned.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the sixth aspect, the second internal power supply circuit section outputs the output of the second internal power supply circuit section when the output current is cut off by the cutoff control circuit section. A voltage application circuit unit for applying an external power supply voltage for a predetermined period is further provided. Accordingly, it is possible to prevent a decrease in the internal power supply voltage output from the first internal power supply circuit unit when performing the cutoff control of the output current from the second internal power supply circuit unit having a large current supply capability. When the current consumption of each circuit supplying the power supply voltage decreases, the generation of noise with respect to the power supply voltage or the like when performing the cutoff control of the output current from the second internal power supply circuit unit having a large current supply capability is further reduced. This can be reliably prevented, and the reliability can be further improved.

According to the semiconductor integrated circuit of the present invention, when a predetermined signal is inputted, the output current outputted from the internal power supply circuit is reduced stepwise by the output switching circuit to cut off the external current. The input current input from the external power supply is gradually increased, and the output voltage from the internal power supply circuit section is switched to a predetermined voltage input from the outside and supplied to each circuit. Thus, when switching the output voltage from the internal power supply circuit to a predetermined voltage input from the outside, it is possible to prevent the generation of noise with respect to the power supply voltage and the like when controlling the cutoff of the output current from the internal power supply circuit. And reliability can be improved.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit according to the eighth aspect, the output switching circuit section includes a delay circuit section, an internal voltage control circuit section, and an external voltage control circuit section. When a predetermined signal is input, the delay circuit section gradually reduces the output current output from the internal power supply circuit section to cut off output to the outside, and gradually reduces the current input from the outside. The voltage applied from the outside is increased and supplied to each circuit. Thus, when switching the output voltage from the internal power supply circuit to a predetermined voltage input from the outside, it is possible to prevent the generation of noise with respect to the power supply voltage and the like when controlling the cutoff of the output current from the internal power supply circuit. And reliability can be improved.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to any one of the eighth and ninth aspects, specifically, the internal power supply circuit section reduces a power supply voltage supplied from the outside to a predetermined internal power supply. It is an internal power supply step-down circuit that generates a voltage and supplies it to each circuit.When switching the internal power supply voltage from the internal power supply step-down circuit to a predetermined voltage input from the outside,
It is possible to prevent the occurrence of noise with respect to the power supply voltage or the like when performing the cutoff control of the output current from the internal power supply step-down circuit, thereby improving the reliability.

According to the eleventh aspect of the present invention, in the semiconductor integrated circuit according to any one of the eighth and ninth aspects, specifically, the internal power supply circuit section determines a bias voltage of the semiconductor substrate from a power supply voltage supplied from the outside. A substrate voltage generation circuit that generates and outputs a predetermined substrate voltage to a semiconductor substrate, and switches the substrate voltage from the substrate voltage generation circuit to a predetermined voltage input from the outside. In this case, it is possible to prevent the occurrence of noise with respect to the power supply voltage or the like when performing the output current cutoff control, and to improve the reliability.

According to a twelfth aspect of the present invention, in the semiconductor integrated circuit according to any one of the eighth and ninth aspects, specifically, the internal power supply circuit portion boosts a power supply voltage supplied from the outside to a predetermined boosted voltage. A boosted voltage generating circuit that generates a voltage and supplies it to each circuit.When switching the boosted voltage from the boosted voltage generating circuit to a predetermined voltage input from the outside, the boosted voltage generating circuit performs cutoff control of the output current from the boosted voltage generating circuit. Generation of noise with respect to a power supply voltage or the like at the time of performing the operation can be prevented, and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a circuit example of a delay circuit 25 in FIG. 1;

FIG. 3 is a timing chart illustrating an operation example of the delay circuit 25 illustrated in FIG. 2;

FIG. 4 is a circuit diagram showing an example of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a circuit example of a delay circuit 64 in FIG. 4;

FIG. 6 is a circuit diagram showing an example of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing an example of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 8 is a schematic block diagram illustrating a circuit example of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

9 is a circuit diagram showing a circuit example of the output switching circuit 123 in FIG.

FIG. 10 is a circuit diagram showing a conventional example of an internal power supply step-down circuit in a semiconductor integrated circuit.

FIG. 11 is a schematic block diagram showing a conventional configuration example of an internal power supply circuit of a semiconductor integrated circuit.

[Explanation of symbols]

1, 55, 85, 105 Internal power supply step-down circuit, 2 Standby VDC, 3, 51, 81, 101 Active VDC, 4 Reference voltage generation circuit, 15 Differential amplifier, 25, 64, 141 Delay circuit, 117 One shot Pulse generation circuit, 120 internal power supply circuit,
121 substrate voltage generation circuit, 122 boost voltage generation circuit, 123-125 output switching circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8242 (72) Inventor Masahiro Orito 2-6-2 Otemachi, Chiyoda-ku, Tokyo Mitsubishi Electric Engineering Co., Ltd.

Claims (12)

[Claims] 1. A semiconductor integrated circuit having an internal power supply circuit for generating a predetermined voltage based on a power supply voltage applied from the outside and supplying the generated voltage to internal circuits, a reference for generating and outputting a predetermined reference voltage A voltage generator, a first internal power supply circuit for generating a predetermined internal power supply voltage from an external power supply voltage based on the reference voltage from the reference voltage generator, and outputting the internal power supply voltage to each circuit; A predetermined internal power supply voltage is generated from an external power supply voltage on the basis of a reference voltage from the external power supply, and is output to each circuit together with the first internal power supply circuit. The current supply capability is greater than that of the first internal power supply circuit. A second internal power supply circuit, wherein the second internal power supply circuit reduces the output current and reduces the output of the internal power supply voltage when the current consumption of each circuit supplying the internal power supply voltage decreases. Characterized by stopping Semiconductor integrated circuit that. 2. The second internal power supply circuit section includes a differential amplifier to which the output internal power supply voltage and a predetermined reference voltage are input, and outputs each signal generated by delaying an input signal to a different time. A delay circuit unit that changes an output current for supplying an internal power supply voltage in accordance with an output voltage of the differential amplifier and each signal from the delay circuit unit. When the current consumption of each circuit to which the internal power supply voltage is supplied decreases, a predetermined signal is input from the outside, and the output circuit unit responds to each delay signal having a different delay amount output from the delay circuit unit. 2. The semiconductor integrated circuit according to claim 1, wherein the output current is reduced stepwise to stop outputting the internal power supply voltage. 3. A differential amplifier to which the output internal power supply voltage and a predetermined reference voltage are input, and wherein the second internal power supply circuit section controls the internal power supply voltage in accordance with the output voltage of the differential amplifier. An output circuit for changing an output current to be supplied; and a cutoff control circuit for performing cutoff control of the output current from the output circuit. The cutoff control circuit receives an internal power supply voltage. When a predetermined signal that is input from the outside is input when the current consumption of each circuit is reduced, the output current output from the output circuit unit is gradually reduced to shut off the output to the outside. The semiconductor integrated circuit according to claim 1, wherein: 4. The shutoff control circuit section outputs a signal generated by delaying an input signal at a different time, and controls operation by each delay signal output from the delay circuit section. A plurality of MOS transistors having different gate sizes, wherein the delay circuit unit turns on each MOS transistor to make it conductive, outputs an output current from the output circuit unit to each circuit, and externally outputs the predetermined current. When a signal is input, the MOS transistors with larger drain currents are sequentially turned off to turn off the MOS transistors, and the output current output from the output circuit section is reduced stepwise to shut off output to the outside. 4. The semiconductor integrated circuit according to claim 3, wherein 5. A differential amplifier to which the output internal power supply voltage and a predetermined reference voltage are input, and wherein the second internal power supply circuit section controls the internal power supply voltage in accordance with the output voltage of the differential amplifier. An output circuit for changing an output current for supply, wherein the output circuit receives a predetermined signal input from the outside when the current consumption of each circuit to which the internal power supply voltage is supplied becomes small. 2. The semiconductor integrated circuit according to claim 1, wherein when input, the output current is continuously reduced to stop outputting the internal power supply voltage. 6. A differential amplifier to which the output internal power supply voltage and a predetermined reference voltage are input, and wherein the second internal power supply circuit section controls the internal power supply voltage in accordance with the output voltage of the differential amplifier. An output circuit for changing an output current to be supplied; a cutoff control circuit for cutting off an output of the output current from the output circuit to the outside when a predetermined signal is input from the outside; 2. The semiconductor integrated circuit according to claim 1, further comprising: a bypass circuit unit that bypasses an output voltage of the output circuit unit for a predetermined time when the output current is interrupted for a predetermined time and reduces an increase in the output voltage. 7. The second internal power supply circuit further includes a voltage application circuit for applying an external power supply voltage to the output of the second internal power supply for a predetermined period when the output current is cut off by the cutoff control circuit. The semiconductor integrated circuit according to claim 6, further comprising: 8. An internal power supply circuit section for generating a predetermined voltage based on a power supply voltage applied from the outside and supplying the generated voltage to each circuit, and an output voltage from the internal power supply circuit section when a predetermined signal is input. And an output switching circuit unit for interrupting supply to each circuit and supplying a predetermined voltage applied from the outside to each circuit. A semiconductor integrated circuit for reducing an output current from a power supply circuit unit and cutting off an output voltage from an internal power supply circuit unit. 9. The output switching circuit section outputs a signal generated by delaying an input signal at a different time, and an operation control is performed by each delay signal output from the delay circuit section. An internal voltage control circuit section comprising a plurality of MOS transistors for controlling output of an output voltage from the internal power supply circuit section to each circuit; and a plurality of operation control sections each of which is controlled by each delay signal output from the delay circuit section. An external voltage control circuit unit configured of a MOS transistor for controlling output of a voltage applied from the outside to each circuit, wherein the delay circuit unit receives the predetermined signal and the internal voltage control circuit unit At the same time, the respective MOS transistors of the external voltage control circuit section are sequentially turned on to be in the conductive state, and the internal The output current output from the source circuit unit is stepwise reduced to cut off the output to the outside, and the current input from the outside is stepwise increased to supply the voltage applied from the outside to each circuit. 9. The method according to claim 8, wherein
3. The semiconductor integrated circuit according to claim 1. 10. The internal power supply step-down circuit according to claim 8, wherein the internal power supply circuit section is an internal power supply step-down circuit that steps down a power supply voltage supplied from the outside, generates a predetermined internal power supply voltage, and supplies it to each circuit. Or a semiconductor integrated circuit according to claim 9. 11. The semiconductor device according to claim 1, wherein the internal power supply circuit is a substrate voltage generation circuit that generates and outputs a bias voltage of the semiconductor substrate from a power supply voltage supplied from the outside and applies a predetermined substrate voltage to the semiconductor substrate. 10. The semiconductor integrated circuit according to claim 8, wherein: 12. The boosted voltage generating circuit according to claim 8, wherein the internal power supply circuit is a boosted voltage generating circuit which boosts a power supply voltage supplied from the outside to generate a predetermined boosted voltage and supplies the boosted voltage to each circuit. A semiconductor integrated circuit according to claim 9.