JPH11214623A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a stable operation with low power consumption by combining delay circuits operating with constant voltage irrespective of power voltage from an outer terminal, generating the timing signal of a level corresponding to power voltage and controlling an inner circuit. SOLUTION: Delay circuits DL1-3 constituting a first timing generation circuit are operated by inner clamping voltage obtained by dropping power voltage to about 2.5 V so that the delay time of the operation voltage is not affected by power voltage supplied from an outer terminal, the fluctuation of 2.7-3.6 V, for example. Level conversion circuits LOGC1&LVC-LOGC3&LVC provided with logic functions constituting a second timing generation circuit to which the input N1 and the delay signals N2-N4 of the respective delay circuits DL1-3 are transmitted convert levels corresponding to signal levels corresponding to precharge/sense amplifier/discharge circuits which correspond to precharge/ sense amplifier/discharge operations and operate with power voltage and they form timing signals CT1-3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective when used in a one-chip microcomputer having a timing generation circuit for forming a timing signal corresponding to an edge of a clock signal. is there.

[0002]

2. Description of the Related Art In a memory or a digital integrated circuit, a basic clock signal is delayed so that an internal circuit forms a timing signal required for operation. An inverter circuit is used for a delay circuit formed in a semiconductor integrated circuit device.

[0003]

In the delay circuit using the above-mentioned inverter circuit, the delay time changes according to the fluctuation of the power supply voltage. That is, the power supply voltage of a digital circuit using a semiconductor integrated circuit device generally allows a voltage fluctuation of about ± 10%, and the delay time also fluctuates in accordance with such a voltage fluctuation. In the timing generation circuit, the timing is designed in consideration of the worst case in which the fluctuation of the power supply voltage is considered, so that a problem that high-speed operation is hindered arises.

An object of the present invention is to provide a semiconductor integrated circuit device provided with a timing generation circuit which realizes stable operation with low power consumption. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a timing generation circuit that realizes stable operation while simplifying the circuit. Still another object of the present invention is to provide a semiconductor integrated circuit device having a level conversion circuit with a logic function. Still another object of the present invention is to provide a semiconductor integrated circuit device provided with a timing generation circuit that realizes operation verification with a simple configuration while realizing stable operation. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. In other words, the internal circuit is controlled by combining a delay circuit operated with a constant voltage made independent of the power supply voltage supplied from the external terminal, and generating a timing signal having a level corresponding to the power supply voltage.
The timing signal is formed by a level conversion circuit with a logic function that receives the delay signal.

[0006]

FIG. 1 is a block diagram showing one embodiment of a single-chip microcomputer to which the present invention is applied. Each circuit block in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The single-chip microcomputer of this embodiment comprises a central processing unit CPU, a clock generation circuit CPG, a data transfer controller (data transfer device) DTC, an interrupt controller INT, and a read-only memory ROM storing programs and the like. Random access memory RA used for temporary storage, etc.
M, FEEROM (Flash Electrically Eraseable & Programmable Read Only Memory) used for storage of data or the like requiring non-volatility,
Timer (ITU), serial communication interface SCI, A / D (analog / digital) converter, input / output ports IOP1 to IOP1
It is composed of each function block or function module of IOP9.

The above-described functional blocks or functional modules are interconnected by an internal bus. The internal bus is
It includes a control bus for transmitting a read signal and a write signal in addition to an address bus and a data bus, and may further include a bus size signal (WORD) or a system clock. The functional blocks or functional modules are read / written by the central processing unit CPU or the data transfer controller DTC via the internal bus. Although not particularly limited, the bus width of the internal bus is made up of 16 bits.

In the single-chip microcomputer of this embodiment, although not particularly limited, the power supply terminals include the ground potential Vss, the power supply voltage Vcc, the analog ground potential AVss, the analog power supply voltage AVcc, and the analog reference voltage Vcc.
ref and other dedicated control terminals such as a reset RES, a STBY STBY, mode controls MD0 and MD1, clock inputs EXTAL and XTAL are provided.

Each input / output port is also used as an input / output terminal of an address bus, a data bus, a bus control signal or a timer, a serial communication interface SCI, and an A / D converter. That is, the timer, the serial communication interface SCI, and the A / D converter have input / output signals, respectively, and are input / output to / from the outside through terminals that are also used as input / output ports.

The compare match signal, overflow signal, and underflow signal of the timer are supplied to the A / D converter as a start signal (A / D conversion start trigger). The interrupt signal is output from the A / D converter, the timer, and the serial communication interface SCI, and the interrupt controller INT receives the interrupt signal and supplies an interrupt request signal to the central processing unit CPU based on the designation of a predetermined register or the like. Or the data transfer controller DT
It controls whether to give a start request signal to C. Such switching is performed by a predetermined bit of the interrupt controller.

As described in "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. or Japanese Patent Application No. 4-137954, a plurality of data transfer devices DTC are activated by one activation. It is possible to transfer a unit of data, a so-called block transfer mode. These have a source address register, a destination address register, a block size counter, a block size holding register, and a block transfer counter, and can perform data transfer in block units.

FIG. 2 is a schematic block diagram showing one embodiment of the FEEPROM. X address signal XA
Is supplied to an X address buffer (X Add Latch) 4,
Here, the fetched address signal is latched. The Y address signal YA is supplied to the Y address buffer (X Add Counte
r) 5 Although not particularly limited, the Y address buffer 5 includes a counter and can read stored information for a maximum of one word line in synchronization with a clock signal. Control signal input circuit (Control SignalInput)
Reference numeral 6 determines operation modes such as writing, reading, and batch erasure specified by the clock signal CKM and the control signal, and generates a timing signal necessary for the determination.

The X address signal taken into the X address buffer 4 is supplied to an X decoder (XDecoder) 2 where it is decoded and selects one word line of the memory array 1. Although not particularly limited, in each of the write operation, the erase operation, and the read operation, the X decoder 2 includes a main word line (SiD) connected to the gate of the selection MOSFET and a word line (SiD) connected to the control gate of the storage transistor. Word Line) and a source selection line (SiS) selection signal corresponding to the main word line (SiD) are formed. Since the potentials of these selection signals are different depending on the respective modes, they have an output circuit that outputs a selection / non-selection level of a voltage corresponding to the operation mode. The voltages necessary for these operation modes are formed by an internal voltage generating circuit (Internal Voltage) 8.

The memory array is provided with storage transistors each having a control gate and a floating gate in a stacked structure at intersections of word lines and data lines.
A data line connected to the drain of the storage transistor is connected to a main data line (Global
Bit Line). Although not particularly limited, the data line is connected to drains of a plurality of storage transistors via the selection MOSFET. Similarly, these 1
The sources of the storage transistors constituting one block are connected to a common source line (Common Source line) through a selection MOSFET.
Line).

The main data line selected by the column switch is connected to the input of the sense amplifier. As will be described later, the sense amplifier sets the high level / low level read to the main data line connected to the selected memory cell to the precharge potential of the unselected main data line not connected to the memory cell as a reference voltage. It is something to sense. A latch circuit is provided at the output of the sense amplifier, and the sense output is held by the latch circuit.

A column switch (Y Gate) 5 connects two main data lines to input / output terminals of a sense amplifier by a selection signal formed by decoding an address signal formed by the Y address buffer 5. The Y decoder for forming the selection signal is included in the column switch 5.
The Y address buffer 5 can also take in a designated address signal as a head value, generate an address signal synchronized with the clock signal CLM by a counter, and perform a continuous read operation. The data terminal D is used to input and output data composed of a plurality of bits.
The signal is decoded by a control logic circuit included in the control signal input circuit 6, and a timing signal and potential setting required for the operation are performed by the control logic circuit. The control signal input circuit 6 also includes a timing generation circuit using a delay circuit as described later.

FIG. 3 is a block diagram for explaining the read operation of the FEEPROM. FIG. 2A shows a pair of data lines D and / D and a word line WL.
1, WL2, the memory cells MC1 and MC2, and the sense amplifier are exemplarily shown as representatives. Therefore,
Data line and source line selection MOSF as shown in FIG.
ET, main data lines, column switches, and the like are omitted.

The memory cell MC1 or the like performs the writing or erasing by injecting or releasing the charge of the floating gate to have a large threshold voltage with respect to the selected level of the word line, and a small threshold. Value voltage. For example, when the word line WL1 is set to the selected level and a read signal is obtained from the memory cell MC1 to the data line D, the data line / D paired with the read signal is also selected by the column switch. Then, the read current source corresponding to the selected data line D is turned on by the signal R1, and the read current is injected. As a result, if the threshold voltage of the memory cell MC1 is lower than the selected level of the word line WL1 and is in the on state, the potential of the data line D becomes the precharge voltage regardless of the supply of the read current. To a low level.

On the other hand, if the threshold voltage of the memory cell MC1 is off because it is higher than the selected level of the word line WL1, the read current is changed to a high level by the supply of the read current. I do. At this time, the read current source is deactivated on the data line / D by the signal R2, and the data line / D is maintained at the precharge potential. As a result, the high level / low level of the selected data line D changes with reference to the precharge voltage of the data line / D, and the two singles that are activated by the sense amplifier active signal (CT2). It is amplified by the end differential amplifier circuit.

The data lines D and / D have a precharge M
OSFETs Q1 and Q2 are provided, and the data lines D and / D are connected to the power supply voltage VCC by a precharge signal (CT1).
Precharge to the side. The data lines D and / D are provided with discharge MOSFETs Q3 and Q4, and the data lines D and / D are discharged to the circuit ground potential by a discharge signal (CT3).

As shown in FIG. 2B, the discharge signal CT3 changes from the high level to the low level, the MOSFETs Q3 and Q4 are turned off, and before and after the precharge operation is completed, the precharge signal CT1 is changed. The level of the MOSFET Q changes from low to high.
1 and Q2 are turned on. Thereby, the data line D
And / D change from a discharge level such as the ground potential of the circuit to a precharge level corresponding to the power supply voltage VCC.

The precharge signal CT1 changes from a high level to a low level to complete the precharge operation, and the sense amplifier active signal CT2 changes from a low level to a high level to activate the sense amplifier.
At the same time, the readout current is applied to the selected data line D.
, A potential difference corresponding to the above-mentioned stored information of the memory cell MC1 is generated in the data lines D and / D, and the potential difference is amplified by the sense amplifier.

In the amplification operation of the sense amplifier,
If the operation period of the sense amplifier is lengthened to keep the current Id flowing, a DC current of 2 × Id continues to flow during that time to increase power consumption. Therefore, in this embodiment, the operation period of the sense amplifier is set to the output side latch circuit LCH.
The high-level period of the sense amplifier active signal CT2 is controlled so as to end the operation when the amplified signal required for the operation is obtained. After the sense amplifier active signal CT2 is set to low level, the decharge signal C2
T3 is set to a high level to discharge the data lines D and / D to a low level such as the ground potential of the circuit. The latch circuit LCH performs a latch operation in response to the timing signal CT4, and captures and holds the output of the sense amplifier at the timing when the latch circuit LCH is set to the high level.

The erasing operation of the memory cell MC1 and the like is performed in units of blocks divided by the selection MOSFET, and 10 V is applied to the word lines WL1 and WL2 in the block.
And a negative voltage such as -9 V is applied to the P-type well potential and the source where the memory cell MC1 and the like are formed. As a result, a tunnel current flows from the P-type well to the floating gate to inject charges, thereby increasing the threshold voltage. At this time, the memory cell is connected to the word line W
It is turned on by 10V of L1 and selected M to prevent the negative voltage of the source from being transmitted to the main bit line.
The OSFET is turned off so that the negative voltage is applied only to the memory cells of the block to be erased. This eliminates undesired stress applied to the memory cells of the non-erased block.

The write operation is performed by applying -9 V to the word line WL1.
, And the potential of the unselected word line is 0 V
To A voltage of 6 V is applied to a data line connected to a memory cell to be written, and charges accumulated in the floating gate are discharged to a drain by a tunnel current to lower a threshold voltage. Unselected data lines are left open or ground potential to prevent the above-mentioned tunnel current from being generated.

FIG. 4 is a block diagram showing one embodiment of the timing generation circuit according to the present invention. The timing generation circuit shown in FIG.
The precharge signal CT1, the sense amplifier active signal CT2, and the discharge signal CT3 shown in FIG. 3 are formed by the second timing generation circuit.

In this embodiment, in order to prevent the above-mentioned timing signals CT1 to CT3 from being affected by the above-mentioned fluctuation of the power supply voltage, in other words, while achieving high-speed operation and low power consumption. In order to secure a necessary operation margin, the delay circuits DL1 to DL3 constituting the first timing generation circuit have their operation voltages centered on a power supply voltage VCC supplied from an external terminal, for example, 3.3V or 3V. 2.7V-3.
The power supply voltage VCC is operated by an internal clamp voltage reduced to, for example, about 2.5 V so that the delay time is not affected by the fluctuation of 6 V. On the other hand, the power supply of the precharge circuit and the sense amplifier uses an external power supply voltage in consideration of the supply capability.

The control circuit CONT determines the operation mode based on the control signal, and if the read mode is determined, opens the gate to transmit the clock signal CKM to the inputs of the serially formed delay circuits DL1 to DL3. . Although not particularly limited, the gate is also operated by the internal clamp voltage. The input N1 of each of the delay circuits DL1 to DL3 and the delay signals N2 to N4 are transmitted to level conversion circuits LOGC1 & LVC to LOGC3 & LVC having a logic function constituting a second timing generation circuit. Level conversion circuit LOGC having these logical functions
The precharge circuits 1 & LVC to LOGC3 & LVC receive the delay signals N1 to N4 having signal levels corresponding to the constant voltage, respond to the precharge operation, the sense amplifier operation and the discharge operation, and operate at the power supply voltage VCC. , The signal level corresponding to the sense amplifier and the discharge circuit, and
T1 to CT3 are formed.

Although not particularly limited, the delay circuit DL1
To DL3 are provided with a control terminal c.
The delay time is switched by a control signal supplied from the NT to the control terminal c. Although not particularly limited, the operation mode is a test mode for verifying the operation margin of the internal circuit, and the time margin of each of the timing signals CT1 to CT3 is set to a stricter condition by the supply of the control signal. It is used for verifying operation margins of a charge circuit, a sense amplifier, and a discharge circuit.

FIG. 5 is a waveform chart for explaining the operation of the timing generation circuit. FIG. 3A shows a case where the clock signal CKM is set to a high frequency such as 60 MHz, and FIG.
The case where KM is set to a relatively low frequency such as 30 MHz is shown.

The memory cell access is instructed by the low level of the memory select signal / MS, and the word line WL is selected in response to the high level of the clock signal CKM. On the basis of the rising edge of the clock signal CKM, the timing generation circuit changes the timing signal CT1 from the low level to the high level after 3 ns to start the precharge operation. At the same time, the timing signal CT3 is set to the low level to end the discharge operation. Therefore, the data lines D and / D perform a precharge operation such that they rise from the ground potential of the circuit toward the power supply voltage VCC at the same level.

After 5 ns from the rising edge of the clock signal CKM, the timing signal CT4 is set to the low level to release the latch operation. As a result, the latch operation of the latch circuit is released, and it becomes possible to capture an amplified signal from the sense amplifier. After 6 ns with reference to the rising edge of the clock signal CKM, the timing signal CT1 is changed to the low level to end the precharge operation. Although not shown, the supply of the read current to the selected data line is started before or after the end of the precharge operation.

After 7 ns with reference to the rising edge of the clock signal CKM, the timing signal CT2 is set to the high level to activate the sense amplifier. At this timing, the sense amplifier starts operating to amplify the level difference between the data lines D and / D as described above. After 14 ns with respect to the rising edge of the clock signal CKM, the timing signals CT3 and CT4 are set to the high level to start the discharge operation and the latch operation. And
After 15 ns with reference to the rising edge of the clock signal CKM, the timing signal CT2 is set to the low level to stop the operation of the sense amplifier, and the current 2 × I
Stop d from flowing.

The above series of operations is performed by setting the frequency of the clock signal CKM to ３０ of 30 MHz as shown in FIG.
Each circuit performs the same operation as described above with the same time setting based on the rising edge of the clock signal CKM. Thus, for example, when the timing control is performed such that the sense amplifier is activated by the clock signal CKM, the sense amplifier is consumed in the above example in accordance with the operating frequency of the clock signal CKM. The current increases twice.
On the other hand, when the respective operation timings are controlled for a fixed time in synchronization with the edge of the clock signal CKM as described above, it is possible to consume only a necessary period without depending on the frequency of the clock signal CKM. It will be.

Further, in this embodiment, since the delay circuit for setting the timing operates at a constant voltage obtained by stepping down the power supply voltage VCC, the power supply voltage varies or the power supply voltage of the system in which the power supply voltage is mounted is reduced. Without being affected by the read signal amount of the memory cell as described above,
Operation control can be performed at an optimal timing corresponding to the sensitivity of the sense amplifier and the like, and there is no need to set an extra time margin in consideration of the voltage fluctuation, so that the operation frequency can be increased. In other words, a high-speed read operation is enabled.

FIG. 6 is a block diagram showing an embodiment of the level conversion circuit with logic function LOG1 & LVC included in the timing generation circuit. This circuit forms a timing signal responsive only to the rising edge of the clock signal CKM. FIG. 1A shows a specific circuit. FIG. 3B shows a timing waveform for explaining the operation. The input signal N1 and its inverted signal N1N are used as the first signal, and the delayed signal N2 delayed by the delay circuit DL1 and its inverted signal N2N are used as the second signal. These two signals are combined, and corresponding to the rising edge of the first signal, the delay circuit D
An output signal OUT having a pulse width corresponding to the delay time of L1 is formed.

The input signal N1 and its inverted delayed signal N2N are supplied to a NAND gate circuit to realize the above-described logic function. That is, the input signal N1 is a P-channel MOSFET Q10 and an N-channel MOSFET
The inverted delay signal N is supplied to the gate of the FET Q15.
2N is supplied to the gates of the P-channel MOSFET Q12 and the N-channel MOSFET Q14. The N-channel MOSFETs Q14 and Q15 are connected in series, and the P-channel MOSFETs Q10 and Q1
2 are connected in a substantially parallel form, thereby forming a NAND gate configuration.

In this embodiment, in order to add a level conversion function, a P-channel type M receiving the input signal N1 is used.
A P-channel MOSFET Q11 is inserted in series between OSFET Q10 and output node A. The inverted input signal N1N is supplied to the gate of the N-channel MOSFET Q16 whose source is connected to the ground potential, and is supplied to the gate of the P-channel MOSFET Q13 provided between the drain and the power supply voltage VCC. The signal at the output node A of the NAND gate circuit is supplied. The signals at the output nodes B of the MOSFETs Q13 and Q16 are supplied to the gate of the P-channel MOSFET Q11. As a result, the two circuits are latched to perform a level conversion operation.

When the input signal N1 goes high, the N-channel MOSFET Q15 turns on, and the N-channel MOSFET Q15 is turned on by the low level of the inverted signal N1N.
SFET Q16 is turned off. At this time, since the inverted delay signal N1DN is at the high level, the N-channel MOSFET Q14 is in the ON state,
Output node A changes to low level in response to the ON state of SFET Q15.

When the output node A changes to the low level, the P-channel MOSFET Q13 turns on, and the output node B rises to the voltage VCC to the high level. Therefore, the P-channel MOSFET Q1
1 is in the cutoff state. Thereby, the input signal N1
Is a constant voltage equal to or lower than the power supply voltage VCC, so that the MOSFETs Q10, Q11 and Q14 can be turned on even if the P-channel MOSFET
And a low level such as the ground potential of the circuit can be formed without passing a direct current through the path of Q15.

When the inverted delay signal N1DN changes to low level with a delay time delay, the N-channel MOSFET Q
14 is turned off, and the P-channel MOSFET Q
12 is turned on. As a result, the node A changes from a low level to a high level corresponding to the voltage VCC. In response to the output node A changing to a high level such as the power supply voltage VCC, a P-channel MOSFET
ETQ13 is cut off. Therefore, output node B maintains the high level in a high impedance (floating) state. Therefore, the off state of the P-channel MOSFET Q11 is maintained.

Thereafter, when the input signal N1 changes to low level and the inverted signal N1N changes to high level, the N-channel MOSFET Q16 is turned on, and the output node B is set to low level. As a result, the P-channel MOSFET Q11 is turned on to operate as a two-input NAND gate circuit. However, the inverted input signal N1 is delayed with respect to the low level of the input signal N1.
Since 1DN goes high, the output node A
The channel type MOSFETs Q10 and Q11 maintain a high level such as the power supply voltage VCC. Node A above
Is a MOSFE which also operates at the power supply voltage VCC.
The output signal OUT is inverted through a T inverter circuit.
(CT1) is output.

With this configuration, a timing signal having a pulse width corresponding to the delay time can be formed. Moreover, even if the input signal N1 and its delay signal N2 have a small amplitude corresponding to the internal clamp voltage, an output signal whose level has been converted to the power supply voltage VCC as described above can be formed. That is, compared to the case where the same circuit function is realized by combining the NAND gate circuit and the level conversion circuit as described above, variation in delay time and the number of circuit elements can be reduced.

FIG. 7 is a block diagram showing an embodiment of the level converter with logic function LOG2 & LVC included in the timing generator. In this circuit, a pulse signal having a constant pulse width is formed like the sense amplifier active signal. FIG. 1A shows a specific circuit. FIG. 3B shows a timing waveform for explaining the operation. The input signal N2 and its inverted delayed signal N2DN are used as the first signal, and the delayed signal N3 delayed by the delay time set by the delay circuit and its inverted delayed signal N3DN are used as the second signal. The inverted delay signals N2DN and N3DN are delay signals formed from an inverter circuit provided inside the delay circuit or an intermediate portion of the next-stage delay circuit. These four signals are combined to form an output signal OUT having a pulse width corresponding to the phase difference between the first signal and the second signal, that is, the delay time of the delay circuit.

The input signal N2 and its inverted delayed signal N2DN are supplied to a NAND gate circuit to realize the above-described logic function. That is, the input signal N2 is composed of the P-channel MOSFET Q21 and the N-channel MOSFET
The inverted delay signal N is supplied to the gate of the FET Q27.
2DN is supplied to the gates of the P-channel MOSFET Q20 and the N-channel MOSFET Q26. The N-channel MOSFETs Q26 and Q27 are connected in series, and the P-channel MOSFETs Q20 and Q27 are connected in series.
21 are connected in parallel to form a NAND gate configuration.

Similarly, the delay signal N3 and its inverted delay signal N3DN are also supplied to the NAND gate circuit. That is, the delay signal N3 is output from the P-channel MOSFET Q24
And the gate of the N-channel MOSFET Q30, and the inverted delay signal N3DN is
It is supplied to the gates of the SFET Q23 and the N-channel MOSFET Q29. The above N-channel type MOSFET
Q29 and Q30 are connected in series, and the P-channel MOSFETs Q23 and Q24 are connected in parallel to form a NAND gate.

Then, in order to provide a level conversion function,
P-channel MOSFETs Q22 and Q25 are provided at the P-channel MOSFET and the output nodes A and B in the two NAND gate circuits, and an N-channel MOSFET is connected to the output node and the ground potential of the circuit.
Q28 and Q31 are provided. Above P-channel type MO
The gates of the SFET Q22 and the N-channel MOSFET Q28 and the gates of the P-channel MOSFET Q25 and the N-channel MOSFET Q31 are shared, and the signals of the other output nodes B and A are supplied to each other. An N.sub.N for initial setting is provided between the output node B and the ground potential of the circuit.
A channel type MOSFET Q32 is provided, and the output node B is reset to the ground potential of the circuit by a signal i3 generated when power is turned on.

As described above, in the initial state where the output node A is at the high level and the output node B is at the low level, the P-channel MOSFET Q22 on the output node A side is turned on, and the P-channel MOSFET on the output node B side is turned on.
The ETQ 25 is turned off. That is, the input signal N2
Output node A is connected to power supply voltage V by P-channel MOSFET Q20 which is turned on by the low level of DN.
High level like CC, P channel type M
OSFET Q25 is turned off.

When the input signal N2 goes high, the N-channel MOSFET 15 is turned on, and a current path is formed by the N-channel MOSFET Q26 which is turned on by the high level of the inverted signal N2DN. From the high level to the low level. At this time, when the output node A changes to low level, the P-channel MOSFET Q25 is turned on, and the output node B changes to high level through the P-channel MOSFET Q24 which is turned on by the low level of the delay signal N3. That is, the output node A and the output node B are quickly switched between the high level and the low level by the positive feedback loop of the latch circuit as described above. Delayed inverted delay signal N2DN
Becomes low level, and the N-channel MOSFET Q2
6 is turned off and the P-channel MOSFET Q20 is turned on, but the output nodes A and B remain unchanged.

When the input signal N3 goes high with a delay of the delay time, the N-channel MOSFET 30 is turned on, and the N-channel MOSFET Q2 turned on by the high level of the inverted signal N3DN.
9, a current path is formed to change the output node B from high level to low level. At this time, when the output node B changes to low level, the P-channel MOS
The FET Q22 is turned on and the P-channel type M is turned on by the low level of the signal N2DN.
The output node A is changed to the high level through the OSFET Q20. That is, the output nodes A and B
As described above, the positive feedback loop in the latch circuit operates to switch between the high level and the low level at high speed. With a delay, the inverted delay signal N3DN becomes low level, and the N-channel MOSFET Q29 is turned off and the P-channel MOSFET Q23 is turned on, but the output nodes A and B do not change.

As described above, the inverted delay signals N2DN and N3DN are switched by the latch circuit at a high speed when the signals N2 and N3 change to the high level, and the input signals are switched by the latch circuit. P-channel type M which is turned on weekly by the high level of N2, N2DN, N3, N3DN.
This prevents a direct current from constantly flowing between the OSFET and the N-channel MOSFET.

FIG. 8 is a circuit diagram showing an embodiment of the delay circuit. FIG. 3A shows a unit circuit having a fixed delay time, and includes CMOS inverter circuits N3 and N3.
4 are connected in cascade, and a capacitor C1 for adjusting the amount of delay is provided therebetween. (B) shows a unit circuit having a variable delay time. In the figure, the same CM as above
A MOSFET Q that is switch-controlled by a control signal c is provided between the OS inverter circuits N5 and N6 to selectively connect the capacitor C2 similar to the above. That is, when the switch MOSFETQ is turned on and the capacitor C2 is connected, the switch MO
A larger delay amount can be obtained as compared with the case where the SFET Q is turned off.

The delay circuits DL1 to DL3 are constructed by combining FIGS. 8A and 8B. When the test mode is set by the control circuit CONT of FIG. 4, the control signal c is generated, and the switch MOSFET of FIG. The read operation is performed under strict operating conditions, for example, by shortening the set delay time or shortening the delay time for setting the time difference between the timing signals CT1 and CT2. By performing a test under such severe conditions, operation is guaranteed in an actual memory operation.

The operation and effect obtained from the above embodiment are as follows. (1) By combining a delay circuit operated at a constant voltage independent of a power supply voltage supplied from an external terminal and generating a timing signal having a level corresponding to the power supply voltage to control an internal circuit, The effect that a stable operation can be realized with power consumption can be obtained.

(2) a memory array composed of a plurality of memory cells in which memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines; a precharge circuit for precharging the data lines; The timing signal includes a sense amplifier that amplifies a read signal read to the data line, and the timing signal is an operation period of the precharge circuit and the sense amplifier based on a rising or falling edge of a predetermined clock signal. Is controlled, low power consumption independent of the operating frequency, high-speed operation independent of the power supply voltage, and a stable operation margin can be obtained.

(3) By setting the frequency of the clock signal in accordance with the intended use, it is possible to obtain the effect of realizing low power consumption in the sense amplifier while expanding the intended use.

(4) The delay circuit has a function of switching the delay time by a control signal, and this function is used for verifying the operation of the circuit, thereby ensuring a highly reliable operation. The effect that can be returned.

(5) The use of an external power supply having a high current supply capability as the precharge supply power supply and the power supply of the sense amplifier can provide an effect that higher reliability operation can be guaranteed.

(6) The first input signal is supplied to the gate, and the first P-channel MOSFET and the first P-channel MOSFET are respectively provided between the first output node and the power supply voltage and between the output node and the ground potential of the circuit. N-channel MOSFE
T, an inverted signal of the first signal is supplied to a gate, a second N-channel MOSFET provided between a second output node and a ground potential of the circuit, the power supply voltage and the first output Between the first output node and the ground potential of the circuit.
SFET, first N-channel MOSFET and CM
A second P-channel MOSFET and a second N-channel MOSFET connected to an OS logic configuration and having a gate supplied with a second input signal; the first output node and the first P-channel MOSFET; A third P-channel MOSFET having a gate connected to the second output node;
And a fourth P-channel MOSFET having a gate connected to the first output node, wherein the first and second input signals are connected to the power supply voltage. Circuit which forms an output signal of a level corresponding to the power supply voltage in synchronization with a change timing from one level of the first input signal to the other level of the first input signal as a small signal level to the first output node Can be obtained, and by providing the level conversion circuit with a logic function, the circuit scale can be reduced and an effect of generating a highly accurate timing signal can be obtained.

(7) A first CMOS logic circuit receiving a first input signal and its inverted delayed signal, a second CMOS logic circuit receiving a second input signal and its inverted delayed signal, First and second MOSFETs of the first conductivity type provided in parallel with the first conductivity type logic MOSFET of the second CMOS logic circuit in the serial configuration
And a second conductivity type first and second MOSFET provided in parallel with the second conductivity type logic MOSFET in parallel with the first and second CMOS logic circuits.
And the gates of the first and second MOSFETs of the first conductivity type and the first and second MOSFETs of the second conductivity type are connected in common, respectively, and the other CMOSs are connected to each other.
Cross-connect with the output of a logic circuit, wherein the first and second input signals and the respective inverted delay signals have a small signal level with respect to the power supply voltage and correspond to a time difference between the first and second input signals. Pulse, and a level conversion circuit with a logic function that forms an output signal of a level corresponding to the power supply voltage can be obtained. Further, by providing the level conversion circuit with a logic function, the circuit scale can be reduced, and Thus, an effect that a highly accurate timing signal can be generated can be obtained.

(8) The operation of the memory circuit operating at the power supply voltage as described in (2) above is controlled using the timing signal generated by the level conversion circuit with logic function of (6) and (7). Thus, an effect that a high-speed and stable operation can be realized can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the internal circuit to which the timing signal generated by the timing generation circuit is supplied includes the flash EEPROM as described above.
In addition to M, it can be widely used as a memory circuit such as an EPROM, a mask ROM, or a static RAM, or various digital circuits in which an operation sequence is executed by a timing signal. In the level conversion circuit with logic function, the internal circuit is operated at the step-down voltage for low power consumption, and the input / output signal is a signal corresponding to the power supply voltage level to obtain compatibility with an external device. It can be widely used for various semiconductor integrated circuit devices.

[0064]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, by combining a delay circuit operated at a constant voltage independent of a power supply voltage supplied from an external terminal and generating a timing signal at a level corresponding to the power supply voltage to control the internal circuit, low power consumption is achieved. A stable operation can be realized with electric power.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied.

FIG. 2 is a schematic block diagram showing one embodiment of the FEEPROM of FIG. 1;

FIG. 3 is a configuration diagram for explaining a read operation of the FEEPROM of FIG. 2;

FIG. 4 is a block diagram showing one embodiment of a timing generation circuit according to the present invention.

FIG. 5 is a waveform chart for explaining the operation of the timing generation circuit of FIG. 4;

6 is a configuration diagram showing one embodiment of a level conversion circuit with logic function LOG1 & LVC included in the timing generation circuit of FIG. 4;

7 is a configuration diagram showing one embodiment of a level conversion circuit with logic function LOG2 & LVC included in the timing generation circuit of FIG. 4;

FIG. 8 is a circuit diagram showing one embodiment of the delay circuit of FIG. 4;

[Explanation of symbols]

CPU: Central processing unit, CPG: Clock generation circuit, D
TC: data transfer device, RAM: random access
Memory, ROM: Read only memory, FEEP
ROM: Flash Electrically Eraseable &
Programmable read only memory, IOP1
ＩIOP9: input / output port, INT: interrupt controller, SCI: serial communication interface, 1 ... memory array, 2 ... X decoder, 3 ... column switch (sense and latch), 4 ... X address buffer, 5 ... Y address buffer, 6. Control signal input circuit
7: input / output buffer, 8: internal voltage generation circuit. MC1,
MC2: memory cell, Q1 to Q32: MOSFET, N
1 to N6: CMOS inverter circuit, C1, C1: capacitor, DL1 to DL3: delay circuit, CONT: control circuit, LOG1 & LVC to LOG3 & LVC: level conversion circuit with logic function.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazumi Suzukawa 5-22-1, Kamisumihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Inventor Masamichi Fujito 5-chome, Josuihoncho, Kodaira-shi, Tokyo 22-1 Inside Hitachi Microcomputer System Co., Ltd. (72) Inventor Hiroshi Shinagawa 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (12)

[Claims] A first timing generating circuit that is operated at a constant voltage made independent of a power supply voltage supplied from an external terminal to generate a first timing signal; and a first timing generating circuit formed by the timing generating circuit. A second timing signal that combines the first timing signal and generates a second timing signal having a level corresponding to the power supply voltage; and an operation performed by the second timing signal formed by the second timing generation circuit. A semiconductor integrated circuit device comprising: an internal circuit to be controlled. 2. The semiconductor integrated circuit device according to claim 1, wherein said first timing generation circuit includes a plurality of delay element arrays. 3. A memory array comprising a plurality of memory cells arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines; a precharge circuit for precharging the data lines; 2. The semiconductor integrated circuit device according to claim 1, further comprising a sense amplifier for amplifying a read signal read to said data line. 4. The system according to claim 3, wherein the second timing signal controls an operation period of the precharge circuit and the sense amplifier based on a rising or falling edge of a predetermined clock signal. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 4, wherein the frequency of said clock signal is set according to its use. 6. The semiconductor integrated circuit according to claim 1, wherein said first timing signal has a function of switching a delay amount by a control signal, and said function is used for verifying a circuit operation. Circuit device. 7. The semiconductor integrated circuit device according to claim 3, wherein the power supply of the precharge circuit is the power supply voltage. 8. The semiconductor integrated circuit device according to claim 3, wherein the power supply to the sense amplifier is the power supply voltage. 9. The second timing generation circuit, wherein a first input timing signal is supplied to a gate, and a first input node is provided between a first output node and a power supply voltage and between the output node and a ground potential of the circuit. 1 P-channel MOS
FET, a first N-channel MOSFET, and a second N-channel MOSFET provided between the second output node and the ground potential of the circuit, the gate being supplied with an inverted signal of the first input timing signal. Between the power supply voltage and the first output node and between the first output node and the ground potential of the circuit.
Channel type MOSFET and first n-channel type M
A second P-channel MOSFET and a second N-channel MOS connected to an OSFET and a CMOS logic configuration, the gates of which are supplied with a second input timing signal;
FET, the first output node, and the first P-channel type MO
A third P-channel MOSF inserted in series with the SFET and having a gate connected to the second output node;
ET; and a fourth P-channel MOSFET provided between the second output node and the power supply voltage and having a gate connected to the first output node. The timing signal includes a level conversion circuit with a logic function for forming an output signal of a level corresponding to the power supply voltage from the first output node as a small signal level corresponding to the constant voltage. 1 a semiconductor integrated circuit device. 10. The second timing generation circuit includes: a first CMOS logic circuit receiving a first input timing signal and an inverted delay signal thereof; and a second CMOS logic circuit receiving a second input timing signal and an inverted delay signal thereof. And a first conductivity type first and second MOSFET provided in parallel with the first conductivity type logic MOSFET in series with the first and second CMOS logic circuits. A second conductivity type first and second MOSFET provided in parallel with the second conductivity type logic MOSFET in parallel with the first and second CMOS logic circuits; The gates of the first and second MOSFETs of one conductivity type and the gates of the first and second MOSFETs of the second conductivity type are commonly connected to each other to exchange the output of the other CMOS logic circuit. Wherein the first and second input timing signals and the respective inverted delay signals have a small signal level corresponding to the constant voltage from the output terminal of the first or second CMOS logic circuit and have a level corresponding to the power supply voltage. 2. The semiconductor integrated circuit device according to claim 1, further comprising a level conversion circuit with a logic function for forming an output signal. 11. A first input signal is supplied to a gate, and a first P-channel MOSFET and a first P-channel MOSFET are respectively provided between a first output node and a power supply voltage and between the output node and a ground potential of the circuit. An N-channel MOSFET and an inverted signal of the first input signal are supplied to a gate, and a second
Provided between the output node of the circuit and the ground potential of the circuit.
Between the power supply voltage and the first output node and between the first output node and the ground potential of the circuit.
Channel type MOSFET and first n-channel type M
A second P-channel MOSFET and a second N-channel MOSFET connected to an OSFET and a CMOS logic configuration, the gates of which are supplied with a second input signal; the first output node and the first P-channel MOSFET; Channel type MO
A third P-channel MOSF inserted in series with the SFET and having a gate connected to the second output node;
ET; and a fourth P-channel MOSFET provided between the second output node and the power supply voltage and having a gate connected to the first output node. A semiconductor integrated circuit having a level conversion circuit with a logic function for forming an output signal of a level corresponding to the power supply voltage from the first output node as a signal level smaller than the power supply voltage; Circuit device. 12. A first CMOS logic circuit receiving a first input signal and an inverted delay signal thereof, and a second CM receiving a second input signal and an inverted delay signal thereof.
An OS logic circuit; a first conductivity type first and second MOSFET provided in parallel with the first conductivity type logic MOSFET in series with the first and second CMOS logic circuits; A second conductivity type first and second MOSFETs provided in parallel with the second conductivity type logic MOSFET in parallel with the first and second CMOS logic circuits; The gates of the first and second MOSFETs of the conductivity type and the first and second MOSFETs of the second conductivity type are commonly connected to each other and cross-connected to the output of the other CMOS logic circuit. The first and second input signals And each of the inverted delay signals is output from the output terminal of the first or second CMOS logic circuit at a level corresponding to the power supply voltage as a signal level smaller than the power supply voltage. A semiconductor integrated circuit device comprising a level conversion circuit with a logic function for forming a force signal.