JPH11213671A - Semiconductor integrated circuit device and initialization circuit built-in ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To collectively and quickly initialize all cells of a RAM by supplying an initialization signal to the RAM, and by providing an initialization circuit for collectively initializing all RAM cells on the input of the initialization signal in the RAM. SOLUTION: For a one-chip microcomputer 10, a semiconductor integrated circuit device consisting of a CPU 11, an initialization circuit built-in RAM 12, a power-on reset circuit 13, a reset bit circuit 14, and a logic OR circuit 15 is incorporated into one tip. The CPU 11 and the initialization circuit built-in RAM 12 exchange data through an address bus 11a, a control bus 11b, and a data bus 11c. The power-on reset circuit 13 generates a PWRST signal(first reset signal) for collectively initializing all RAM cells of the RAM 12 when power is turned on. The reset bit circuit 14 generates a second reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device in which a RAM cell batch initialization process performed in a RAM test or the like is improved, and a RAM with a built-in initialization circuit mounted on the semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, as a RAM mounted on a one-chip microcomputer or the like, for example, there is a RAM as shown in FIG.

FIG. 7 is a circuit diagram showing a 1-bit configuration of a conventional RAM.

This RAM has a plurality of word lines WL0-W
A RAM cell array unit 101 in which a RAM cell 110 is connected at each intersection of Ln and a pair of bit lines bit and bitV is provided, and a word selector unit 102, a bit line precharge circuit 103, a word line detection circuit 10
4. Precharge control signal generation circuit 105, read /
A write circuit 106, a read / write control signal generation circuit 107, a data input circuit 108, and a data output circuit 109 are provided.

Prior to a data read / write operation, a precharge control signal PRCV output from a precharge control signal generation circuit 105 is controlled to a "1" level / "0" level in synchronization with a clock φ1 to generate a bit line. The precharge circuit 103 receives the precharge control signal P
Receiving the RCV, the bit line pair bit, bitV is precharged to “1” level.

At the time of data reading, an address is given, and a RAMCS signal (chip select) = "1".
The RAMWR signal = "0" and the RAMRD signal = "1". AL1 to AL5, AL6 to AL8, AL9 in the figure
Is a signal generated corresponding to the address,
L1V to AL5V are inverted signals of the signals AL1 to AL5.

The word selector unit 102 activates a predetermined number of word lines WL0 to WLn to "1" level in accordance with a given address. Then, the data stored in the cell 110 connected to the selected word line is read onto the bit line pair bit, bitV.

At this time, the word line detecting circuit 104 detects the terminating signal of each of the word lines WL0 to WLn, and outputs the resulting "0" level to the precharge control signal generating circuit 1.
05, the precharge control signal PRCV is fixed at the “1” level, and the precharge by the bit line precharge circuit 103 stops. At the same time, the data input circuit 108 is inactive because the RAMWR signal is "0".

Then, the R / W control signal generation circuit 107
Sets the R / W control signal EN to “1” in accordance with the clock φ2.
/ "0" level, and at the "1" level, the read / write circuit 106 transmits read data on the bit line pair bit to the data output circuit 109. RAMR
Since the D signal = “1”, the data output circuit 109
The read data is output to the system bus MBUSn.

At the time of data writing, the RAMRD signal becomes "0", and the output of the data output circuit 109 enters a high impedance state. Then, an address is given, and the RAMCS signal = “1” and the RAMWR signal =
When it becomes “1”, the write data from the system bus MBUSn latched by the data input circuit 108 is transferred to the bit line pair bi via the read / write circuit 106.
t, bitV propagated to the selected RAM cell 110
Data is written to

At the time of testing the RAM, all RAM cells 110 are collectively initialized by sequentially writing initialization data from the first address to the last address of the RAM using a RAM initialization test program.

[0012]

In the above-mentioned conventional RAM, in order to initialize all the cells of the RAM cell 110 collectively,
As described above, since it is necessary to sequentially write the initialization data from the first address to the last address of the RAM, there is a problem that much time is required for the test of the RAM. For example, if the increment time of one address is 0.2 μs, the time for initializing the RAM data of 2048 bytes capacity is 0.2 μs * 204
8 bytes = about 0.4 ms.

Further, since an initialization program is required, the number of program steps on the software increases depending on the RAM capacity, which has led to a situation where a bug on the software tends to occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor integrated circuit device capable of performing high-speed batch initialization of all cells of a RAM. That is. It is another object of the present invention to provide a RAM with a built-in initialization circuit for performing a batch initialization of all cells at a high speed. Furthermore, while performing the batch initialization of all the cells of the RAM at high speed,
An object of the present invention is to provide a one-chip microcomputer capable of greatly reducing the number of program steps on software.

[0015]

In order to achieve the above-mentioned object, a first aspect of the present invention is a RAM arranged on an array.
RAM for writing / reading data to / from cells
And an initialization signal supply circuit for supplying an initialization signal to the RAM, and the RAM includes an initialization circuit for batch-initializing all RAM cells when the initialization signal is input. That is.

According to a second aspect of the present invention, in the first aspect, the RAM stops an operation related to writing / reading in a normal mode in an initialization mode to which the initialization signal is input. It is in.

A feature of the third invention is that the first or second embodiment is characterized in that:
In the invention, the initialization signal supply circuit includes a power-on reset circuit that generates a first reset signal as the initialization signal when power is turned on.

A feature of the fourth invention is that the first or second embodiment is characterized in that:
In the invention, the initialization signal supply circuit is constituted by a reset bit circuit that generates a second reset signal as the initialization signal when a reset bit is written according to an instruction from an external circuit.

A fifth aspect of the present invention is characterized in that the first or second aspect is provided.
In the invention, the initialization signal supply circuit includes a power-on reset circuit that generates a first reset signal as the initialization signal when power is turned on, and a power-on reset circuit that writes a reset bit according to an instruction from an external circuit. 2
And a reset bit circuit that generates the reset signal of the above (1), and supplies the first or second reset signal to the RAM as the initialization signal.

A sixth aspect of the present invention is characterized in that a RAM cell array section in which RAM cells are respectively connected to intersections of a plurality of word lines and bit line pairs, a word selector section for selecting the word lines, and a precharge. A bit line precharge circuit for precharging the bit line pair by a control signal; a word line detection circuit for detecting a termination signal of each of the word lines; and a precharge control signal based on a detection result of the word line detection circuit. A read / write circuit for performing a data write / read operation on the bit line pair after precharge by a read / write control signal, and a read / write control signal. A read / write control signal generation circuit to be generated and write data input from an external bus to write And outputs to the read / write circuit during write, and a data output circuit for outputting the read data on the bit line pair received from the read circuit during the read to the external bus RAM
An initialization data writing circuit for transmitting initialization data to the bit line pair when an initialization signal is input from the outside, wherein the word selector unit activates all of the word lines when the initialization signal is input. And the read / write control signal generation circuit, the data input / output circuit, and the precharge control signal generation circuit are configured to be in an inactive state when the initialization signal is input. It is in.

According to a seventh aspect of the present invention, a RAM with a built-in initialization circuit according to the sixth aspect of the present invention and a CP for controlling a write / read operation of the RAM with a built-in initialization circuit are provided.
U and the built-in initialization circuit R when the power is turned on or when the reset bit is written by the instruction of the CPU.
An initialization signal supply circuit for supplying an initialization signal to the AM is constituted by one chip.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor integrated circuit device and a RAM with an initialization circuit according to the present invention will be described.

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device (one-chip microcomputer) according to an embodiment of the present invention.

The one-chip microcomputer 10 includes a CPU 1
1 other than the RAM 1 with a built-in initialization circuit of the present invention.
2. A semiconductor integrated circuit device including a power-on reset circuit 13, a reset bit circuit 14, and a logical OR circuit 15 is incorporated in one chip. The CPU 11 exchanges data with the initialization circuit built-in RAM 12 through the address bus 11a, the control bus 11b, and the data bus 11c.

The power-on reset circuit 13 is a circuit that generates a PWRST signal (first reset signal) for collectively initializing all the RAM cells of the RAM 12 when the power is turned on. FIGS. 2A and 2B show examples of the configuration. In the configuration shown in FIG. 2A, the N-MOS transistor 2
1, a capacitor 22, a resistor 23, an N-MOS transistor 24, and inverters 25 and 26. FIG.
In another configuration shown in (b), the diode 31, the resistor 3
2, a capacitor 33 and an inverter 34.

According to the power-on reset circuit 13, as shown in FIG.
A period during which a transition from the ND level to the VDD level (5v) occurs,
For example, a “1” pulse signal having a pulse width of 1 μs or more is generated as a PWRRST signal between 1.5 V and 3 V.

The reset bit circuit 14 is used when the reset bit is written according to an instruction from the CPU 11.
Is a circuit that generates an RRSTRST signal (second reset signal) for batch-initializing all the RAM cells. The configuration thereof is, for example, as shown in FIG. 3A, a reset bit register 41, a two-input OR gate 42, a latch 43 with a reset function, a buffer 44, and latches 45 and 46.
Consists of

The reset bit register 41 stores RSTW
Receiving the R signal = "1", the system bus MBUS (11
c) Write the above data and set the RSTRD signal =
In response to "1", data is read out to the system bus MBUS. Here, the RSTWR signal is generated by the logical product of the ADR ′ signal, the WR signal, and the system clock φ1, and
The STRD signal is generated by the logical product of the ADR 'signal, the RD signal, and the system clock φ1. ADR '
The signal is generated based on an address signal ADR from the CPU 11 as shown in FIG. RD signal is CP
A read control signal from U11, and a WR signal is a write control signal.

As shown in FIG. 3B, when the ADR 'signal, WR signal and system clock φ1 all become "1" and the RSTWR signal becomes "1", "1" data is stored in the reset bit register 41. Written, as a result, RS
The TBIT signal becomes "1" level. Since the latch 43 with the reset function operates in synchronization with the system clock φ2 which is an inverted signal of the system clock φ1, the RST
The RSTRST signal becomes "1" from the next rise of the system clock φ2 at the time when the BIT signal becomes "1" (the time shown by the broken line in FIG. 3B).

On the other hand, the RSTRST signal = "1"
The data is fed back to one end of the OR gate 42 via latches 45 and 46 operating in synchronization with the system clock φ1 and the system clock φ2, respectively. Accordingly, the next system clock φ2 at the time indicated by the broken line in FIG.
Signal rises to the "1" level, the output of the two-input OR gate 42 becomes "1", the latch 43 is reset, and the RSTRST signal = "0".

As described above, in one clock period t (t = 100 ns at a transmission frequency of 20 MHz) in FIG. 3B, the RSTRST signal becomes "1", and an RSTRST signal having a one-shot pulse width is generated. The reset bit circuit 14 is reset by a RESET signal = "1" from the CPU 11.

The logical OR circuit 15 outputs the PWRRST signal output from the power-on reset circuit 13 and the RSTR signal output from the reset bit circuit 14.
The logical sum operation of the ST signal is performed, and the initialization signal IN
The IT signal is supplied to the RAM 12.

FIG. 4 is a circuit diagram showing a one-bit configuration of RAM 12 with a built-in initialization circuit shown in FIG.

The RAM 12 has a plurality of word lines WL0
A RAM cell array unit 51 in which a RAM cell 60 is connected to each intersection of WLn and a pair of bit lines bit and bitV is provided. Further, the word selector unit 5
2, bit line precharge circuit 53, word line detection circuit 54, precharge control signal generation circuit 55, read /
Write circuit 56, read / write control signal generation circuit 57, data input circuit 58, and data output circuit 59
In addition, an initialization data writing circuit 61 which is a feature of the present invention is provided.

The RAM cell 60 is composed of N-MOS transistors 60a and 60b and inverters 60c and 60d connected in anti-parallel between the transistors 60a and 60b.

Initialization data writing circuit 61
At the time of RAM initialization (INIT signal = "1")
Is a circuit for writing initialization data to the bit line pair bit, bitV, and is composed of a tri-state inverter 61a and a tri-state inverter 61b. The tri-state inverter 61a has a power supply potential as an input, its output side is connected to a bit line bit, the tri-state inverter 61b has a ground potential as an input, and its output side is connected to a bit line bitV. The operation is controlled by an INITWR signal based on the INIT signal applied to the activation control line 62. The initialization control line 62 is
It is laid branching in the word line direction and the bit line direction, and the INIT signal is supplied from both ends. In the middle of the initialization control line 62 on the word line direction side, a buffer 6 for outputting an INITWR signal is provided.
2a and 62b are inserted.

The word selector unit 52 decodes an address during a normal operation to decode a plurality of word lines WL0 to WL.
Ln, a predetermined one is selected, and at the time of RAM initialization (INIT signal = “1”), all word lines WL
This circuit sets 0 to WLn to “1”. NOR gate 52a-1 for address decoding as in the conventional circuit
52a-n and AND gates 52b-1 to 52b-n, and a two-input OR gate 5 which is a feature of the present invention.
2c-1 to 52c-n. OR gate 52c
-1 to 52c-n are respectively connected to the output terminals of AND gates 52b-1 to 52b-n for outputting an address decode result, and the other input terminals are connected to the bit of the initialization control line 62. Commonly connected to the line on the line direction side.

The bit line precharge circuit 53 is a circuit for simultaneously precharging the pair of bit lines bit and bitV to "1" level when the precharge control signal PRCV is at "0" level. The P-MOS transistors 53a and P-
It is composed of a MOS transistor 53b.

The word line detection circuit 54 is connected to each word line WL.
0 to WLn, and a NOR gate 54a-1 to 54a-n and a NAND gate 54b.
-1 to 54b-n and a multi-input NOR gate 54c, and the output of the NOR gate 54c is an output signal of the circuit 54. When all of the word lines WL0 to WLn are not selected at “0” level, the output of the word line detection circuit 54 is “1”.
Level, and when at least one of the word lines WL0 to WLn is also at the "1" level, it is at the "0" level.

The precharge control signal generation circuit 55
Is a circuit for generating a "0" level precharge control signal PRCV for precharging the bit line precharge circuit 53 when the output of the word line detection circuit 54, the INIT signal and the system clock φ1 are in an AND condition. Inverters 55a and 55b, a three-input NOR gate which characterizes the present invention, and inverters 55d and 55d
55e and 55f. The output of the word line detection circuit 54 is input to the inverter 55a, the system clock φ1 is input to the inverter 55b, and
The input NOR gate 55c includes inverters 55a, 55
b and the INIT signal are input.

The read / write circuit 56 uses the R / W control signal EN to pre-charge the bit line pair bi.
This is a circuit for performing a data write / read operation with respect to t and bitV.
6b, 56c, 56d and tri-state inverter 56
e.

The R / W control signal generating circuit 57
This circuit generates a W control signal EN, and includes a NOR gate 57a for address decoding, AND gates 57b and 57
c and an inverter 57d. An address decode output and an R / W control signal EN which becomes "1" when the INIT signal = "0" and an AND condition of the system clock φ2 are output.

The data input circuit 58 is connected to the system bus MB
At the time of writing (RAMWR signal = “1”, RAMRD = signal “0”,
INIT signal = "0") read / write circuit 56
And a clocked inverter 58a,
58b, an inverter 58c, and an AND gate 58d,
58e and 58f.

The data output circuit 59 operates at the time of reading (RA
MRD = “1”, RAMWR = “0”, INIT signal =
“0”) is a circuit that receives read data on the bit line pair bit, bitV from the read / write circuit 56 and outputs it to the system bus MBUSn.
D gate 59a, NOR gate 59b, inverter 59
c, a tri-state inverter 59d, and an AND gate 59e. An address decode condition for outputting the output of the read / write circuit 56 to the system bus MBUSn is included.

Next, the one-chip microcomputer 10 having the above configuration
In the operation of the RAM 12 with built-in initialization circuit,
In particular, the operation at the time of initialization will be described.

(Operation at Power-on) At the time of power-on, during the transition from the GND level to the VDD level as shown in FIG. 2C, the power-on reset circuit 13 operates as described above, and the PWRRST signal , A “1” pulse signal having a pulse width of 1 μs or more is generated. As a result, the INIT of the “1” level is
The signal is supplied to the RAM 12 with a built-in initialization circuit.

In the RAM 12 with a built-in initialization circuit,
While the INIT signal is at “1” level, the word line WL0
To WLn all become “1” level, and writing to the RAM cell 60 becomes possible. Since the INITWR signal is also at the “1” level, the tri-state inverter 6
1a and 61b enter the output state, and the bit line pair bit and b
The “0” / “1” level is transmitted to itV, respectively.
As a result, the initialization data (d0-dn = “0” level) is written to all the RAM cells 60 at a time,
Batch initialization of the RAM cells 60 is performed.

In the initialization period, the output of the three-input NOR gate 55c of the precharge control signal generating circuit 55 is fixed at "0" level, so that the PRCV signal =
It becomes "1", and the precharge operation for the bit lines bit and bitV stops. Further, since the output of the AND gate 57c of the R / W control signal generation circuit 57 is fixed at "0" level, the R / W control signal EN for controlling writing / reading to / from the bit line in the normal mode is set to "0". "Level (disabled). At the same time, the data output circuit 59
The output of the AND gate 59e is also fixed to the "0" level, so that the tri-state inverter 59d for reading the RAM data to the system bus is disabled. FIG. 5 shows the RAM initialization operation when the power is turned on.
The timing chart is shown in FIG.

(Normal Read / Write Operation) CPU
When reading data stored in the initialization circuit built-in RAM 12, the RAM 11 gives an address to the RAM 12 through the address bus 11 a, and further supplies a RAMCS signal (=
“1”) and the RD signal (= “1”) and W
The D signal (= "0") is sent to make the RAMWR signal = "0" and the RAMRD signal = "1". INIT signal =
Since it is at the “0” level, the operation of the RAM 12 is the same as that of the conventional circuit (FIG. 7).

(Operation at the time of writing the reset bit) When "1" data is written into the reset bit register 41 by a command from the CPU 11 during the normal operation, as shown in FIG.
It becomes “1” level. Further, based on the RSTBIT signal, 1
An RRSTRST signal having a shot pulse width is generated. As a result, the "1" level INIT signal is supplied to the initialization circuit built-in RAM 12 by the logical OR circuit 15.

The operation up to the batch initialization of the RAM cells 60 is the same as the RAM initialization operation when the power is turned on, and therefore, the description is omitted. However, the writing time is 1 μs or more when the power is turned on, but becomes as fast as about 0.2 μs when writing the reset bit. FIG. 6 is a timing chart showing the RAM initialization operation at the time of writing the reset bit.

As described above, since the RAM 12 of the present embodiment incorporates the initialization data writing circuit 61, all the RAM cells 60 in the RAM circuit are turned on when the power is turned on.
Can be collectively initialized, and also during normal operation, by writing a reset bit to the reset bit register 41, all the RAM cells 60 can be collectively initialized at high speed. RA on such hardware
The test time of the RAM circuit can be significantly reduced by the M cell batch initialization method.

For example, in the conventional circuit, when the increment time of one address is set to 0.2 μs, the time for initializing the RAM data of 2048 bytes capacity is set to 0.
It was necessary to spend an initialization time of 2 μs * 2048 bytes = about 0.4 ms. In contrast, in the present embodiment,
At the fastest time of 0.2 μs, all the cells of the RAM can be collectively initialized.

Further, since the conventional RAM initialization test program is not required, the number of program steps can be significantly reduced on software, and the bug occurrence rate on software can be reduced.

[0055]

As described above in detail, according to the semiconductor integrated circuit device of the present invention, since the batch initialization of all the RAM cells is performed by hardware, the batch initialization can be performed at high speed. . As a result, for example, the RAM test time can be significantly reduced.
Since the initialization test program becomes unnecessary, the number of program steps on the software can be significantly reduced.

The batch initialization of all the RAM cells can be performed by hardware when power is turned on or when instructed by an external circuit.

Further, by using a one-chip microcomputer, the conventional RAM initialization program becomes unnecessary, and the number of program steps on software is greatly reduced, so that the incidence of bugs on software can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a power-on reset circuit in FIG.

FIG. 3 is an explanatory diagram of a reset bit circuit in FIG. 1;

FIG. 4 is a circuit diagram showing a 1-bit configuration of a RAM with a built-in initialization circuit in FIG. 1;

FIG. 5 is a timing chart showing a RAM initialization operation when power is turned on.

FIG. 6 is a timing chart showing a RAM initialization operation when writing a reset bit.

FIG. 7 is a circuit diagram showing a 1-bit configuration of a conventional RAM.

[Explanation of symbols]

 Reference Signs List 10 one-chip microcomputer 11 CPU 12 RAM with built-in initialization circuit 13 power-on reset circuit 14 reset bit circuit 15 logical OR circuit 51 RAM cell array section 52 word selector section 53 bit line precharge circuit 54 word line detection circuit 55 precharge control signal generation circuit 56 read / write circuit 57 read / write control signal generation circuit 58 data input circuit 59 data output circuit 60 RAM cell 61 initialize data write circuit WL0 to WLn word line bit, bitV bit line pair

Claims (7)

[Claims] 1. A semiconductor integrated circuit device having a RAM for writing / reading data to / from RAM cells arranged on an array, comprising: an initialization signal supply circuit for supplying an initialization signal to the RAM; A semiconductor integrated circuit device, comprising: an initialization circuit for batch-initializing all RAM cells when the initialization signal is input. 2. The semiconductor integrated circuit according to claim 1, wherein the RAM is configured to stop an operation related to writing / reading in a normal mode in an initialization mode to which the initialization signal is input. apparatus. 3. The semiconductor integrated circuit according to claim 1, wherein said initialization signal supply circuit comprises a power-on reset circuit that generates a first reset signal as said initialization signal when power is turned on. Circuit device. 4. The initialization signal supply circuit according to claim 1, wherein a reset bit circuit that generates a second reset signal as said initialization signal when a reset bit is written by an external circuit is written. Or 2) a semiconductor integrated circuit device. 5. An initialization signal supply circuit comprising: a power-on reset circuit for generating a first reset signal as the initialization signal when power is turned on; and an initialization signal for writing a reset bit instructed by an external circuit. A reset bit circuit for generating a second reset signal;
3. The semiconductor integrated circuit device according to claim 1, wherein the first or second reset signal is supplied to the RAM as the initialization signal. 6. A RAM cell array unit in which RAM cells are connected to respective intersections of a plurality of word lines and bit line pairs, a word selector unit for selecting the word lines,
A bit line precharge circuit for precharging the bit line pair by a precharge control signal; a word line detection circuit for detecting a terminating signal of each word line; and the precharge based on a detection result of the word line detection circuit. A precharge control signal generating circuit for generating a control signal; a read / write circuit for performing a data write / read operation on the bit line pair after precharge by a read / write control signal; A read / write control signal generating circuit for generating a signal, and inputting write data from an external bus and outputting to the read / write circuit at the time of writing, and reading data on the bit line pair at the time of reading from the read circuit. Data input / output circuit for receiving and outputting to the external bus An initialization data writing circuit that propagates initialization data to the bit line pair when an initialization signal is input from the outside, wherein the word selector unit includes the word line when the initialization signal is input. Are activated, and the read / write control signal generation circuit, the data input / output circuit, and the precharge control signal generation circuit are inactivated when the initialization signal is input. A RAM with a built-in initialization circuit. 7. The RAM with built-in initialization circuit according to claim 6, a CPU for controlling a write / read operation of the RAM with built-in initialization circuit, and the built-in initialization circuit when power is turned on or when a reset bit is written according to an instruction from the CPU. A semiconductor integrated circuit device comprising an initialization signal supply circuit for supplying an initialization signal to a RAM on a single chip.