JPH11213669A - Sense circuit and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a sense circuit for achieving quick operation with high sensitivity by outputting an output signal from at least one of a pair of input and output where a pair of the drain outputs of a differential MOSFET and a CMOS latch circuit are crossed and connected. SOLUTION: The sources of N channel type MOSFETs N1 and N2 of first and second CMOS inverter circuits are connected in common. Then, an N channel type MOSFEF N3 is provided between the source and an earthing potential VSS, where the MOSFET N3 receives an operation timing signal MA1 and forms an operating current in the first and second CMOS inverter circuits. The operation timing signal MA1 is generated before an equalizing signal EQ#, thus performing quick operation. When the equalizing signal EQ# is returned to a high level and the operation timing signal MA1 is generated after the termination timing of equalizing operation, the start timing of sense amplification operation is delayed by that amount.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a sense circuit and a semiconductor integrated circuit device, for example, a random access memory (RAM).
The present invention relates to a technology effective when applied to a sense (main amplifier) circuit that amplifies a small-amplitude input signal read from a memory cell through a column selection circuit like an access memory.

[0002]

2. Description of the Related Art A dynamic RAM having a large storage capacity such as 64 Mbits or 256 Mbits is disclosed in "Nikkei Electronics" No. 641, pp. 99-214, published on July 31, 1995 by Nikkei McGraw-Hill. is there.

[0003]

In order to reduce power consumption, reduce noise, increase speed, and the like, a dynamic RAM also forms an internal step-down voltage obtained by stepping down a power supply voltage supplied from an external terminal. Is written / read. On the other hand, the output signal output from the external terminal needs to have a large signal amplitude corresponding to the power supply voltage. In this case, the signal amplitude read from the memory cell through the address selection circuit is a minute voltage based on the step-down voltage,
In a sense circuit (main amplifier) for amplifying the signal amplitude to a signal amplitude corresponding to the power supply voltage, high-speed operation with high sensitivity is required.

Prior to the present invention, the inventors of the present invention have studied the use of a cross-coupled sense circuit as shown in FIG. 22 and a latched sense circuit as shown in FIG. did. In a cross-coupled sense circuit as shown in FIG. 22, an input signal formed at the stepped-down operating voltage as described above is received by the gate of an N-channel type differential MOSFET, and the cross-coupled P-channel type MOSFET is used. It has been found that there is a problem that the sense operation is delayed due to the amplifying action. For example, in a synchronous DRAM, it is required to operate a sense circuit with a short pulse of about several nanoseconds. Therefore, the above-described cross-coupled sense circuit corresponds to the short pulse in terms of amplifying operation speed. Can not.

In a latch type sense circuit as shown in FIG.
In contrast to the potential corresponding to the level reduced voltage VDL level of the input signals VIN, VINB, the output terminals OUT,
OUTB is a voltage higher than the step-down voltage VDL, such as the external power supply voltage VCC or VDD. When the relationship of VCC> VDDL is satisfied in this manner, in the latch-type sense circuit in which the input and the output are cross-connected as described above, the current flows backward from the power supply voltage VCC of the sense circuit to the input signal side, The potential of the input node is set to the internal step-down voltage VD
L, the circuit malfunction potential increases, for example, the equalizing operation of the input node is not completed within a short precharge period. In addition, there is a problem that it is difficult to secure a potential difference (signal amount) of an input signal input to the sense circuit because the input capacitance is larger than that of a gate input type such as the cross-coupled sense circuit.

An object of the present invention is to provide a sense circuit which realizes high-speed operation with high sensitivity and a semiconductor integrated circuit device having the same. Another object of the present invention is to provide a sense circuit realizing the above-described high sensitivity, high-speed operation, and low power consumption, and a semiconductor integrated circuit device having the same. Still another object of the present invention is to provide a sense circuit which realizes the above-described high-sensitivity, high-speed, level conversion operation and low power consumption, and a semiconductor integrated circuit device having the same. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the differential MO receiving the input signal
A first MOSFET for receiving an operation timing signal and flowing an operation current is provided on the common source side of the SFET.
A CMOS latch circuit is provided which receives the drain output of the OSFET and has an input and an output cross-connected to each other.
A second MOSFET for receiving an operation timing signal and supplying an operation current to the S latch circuit;
An output signal is output from at least one of the pair of drain outputs and the pair of cross-connected inputs and outputs of the CMOS latch circuit.

[0008]

FIG. 1 shows a synchronous DRAM (hereinafter simply referred to as an SDRAM) to which the present invention is applied.
1 is an overall block diagram of one embodiment. Although not particularly limited, the SDRAM shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The SDRAM of this embodiment has a memory array 200A forming memory bank 0 and a memory bank 1
Is provided. Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix. According to the figure, the selection terminals of the memory cells arranged in the same column are coupled to a word line (not shown) for each column. The data input / output terminals of the memory cells arranged in the same row are connected to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selected level in accordance with the result of decoding a row address signal by a row (row) decoder 201A. A complementary data line (not shown) of the memory array 200A is an I / O line 2 including a sense amplifier and a column selection circuit.
02A. The sense amplifier in the I / O line 202A including the sense amplifier and the column selection circuit is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in this case is a switch circuit for selecting complementary data lines individually and conducting to the complementary I / O lines. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A.

Similarly, a row decoder 201B, an I / O line 202B including a sense amplifier and a column selection circuit, and a column decoder 203B are provided on the memory array 200B side. The complementary I / O lines are write buffers 214A and 214B.
And the input terminals of the main amplifiers 212A and 212B. The main amplifier (or sense circuit) 21
Although the output signals of 2A and 2B are not particularly limited,
The signal is transmitted to the input terminal of the register 213, and the output signal of the latch / register 213 is output from an external terminal via the output buffer 211. The write signal input from the external terminal is transmitted to the input terminals of the write buffers 214A and 214B via the input buffer 210.
The external terminal is a data input / output terminal for outputting data D0 to D15 of 16 bits, although not particularly limited.

Address signals A0 to A9 supplied from the address input terminals are taken into a column address buffer 205 and a row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of a column address counter 207, and the column (column) address counter 207 outputs a column address signal as the preset data or a column address signal according to an operation mode specified by a command described later. A value obtained by sequentially incrementing the column address signal is output to the column decoders 203A and 203B.

A controller 2 shown by a dotted line in FIG.
09 is, although not particularly limited, a clock signal CLK, a clock enable signal CKE, and a chip select signal / C.
S, a column address strobe signal / CAS (symbol / means that a signal added thereto is a row enable signal), a row address strobe signal / RAS,
An external control signal such as a write enable signal / WE and control data from address input terminals A0 to A9 are supplied, and the operation mode of the SDRAM and the circuit block The mode register 10 and the command decoder 2 form an internal timing signal for controlling the operation.
0, a timing generation circuit 30, a clock buffer 40, and, although not particularly limited, a synchronous clock generation circuit 50.

The clock signal CLK is input to the synchronous clock generation circuit via the clock buffer 40 as described above, and is synchronized with the internal clock formed here. Although the internal clock is not particularly limited, a timing signal int.CLK for activating the output buffer 211 is used.
The signal passed through the clock buffer is directly transmitted to other circuits. Other external input signals are made significant in synchronization with the rising edge of the internal clock signal.

The chip select signal / CS indicates the start of a command input cycle by its low level. When the chip select signal / CS is at a high level (chip is not selected) and other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. / RAS, / CAS and / WE signals are normal DR
The function is different from that of the corresponding signal in AM, and is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal indicating the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. Although not shown, in the read mode,
When an external control signal / OE for controlling output enable for the output buffer 211 is provided, the signal / OE is also supplied to the controller 209. When the signal is at a high level, for example, the output buffer 211 is in a high output impedance state. To be.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK (internal clock signal).

The address signal A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at low level, memory bank 0 is selected, and when it is at high level, memory bank 1 is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the input buffer 210 and the output buffer of the selected memory bank only. It can be performed by processing such as connection to 211.

An address signal A8 in a precharge command cycle to be described later indicates a mode of a precharge operation for a complementary data line or the like, and its high level indicates that both memory banks are to be precharged. The low level indicates that one of the memory banks indicated by the address signal A9 is to be precharged.

The column address signal is defined by the levels of A0 to A7 in a read or write command (to be described later, a column address read command, a column address write command) cycle synchronized with the rising edge of the clock signal CLK (internal clock). Is done.
The column address defined in this way is used as a start address for burst access.

Next, the SDR specified by the command
The main operation mode of the AM will be described. (1) Mode register set command (Mo) This command is for setting the mode register 30. The command is specified by / CS, / RAS, / CAS, / WE = low level, and the data to be set (register set data ) Are given via A0-A9. Although the register set data is not particularly limited,
Burst length, CAS latency, write mode, and the like are set. Although not particularly limited, the settable burst length is 1, 2, 4, 8, and full page, the settable CAS latency is 1, 2, 3, and the settable write modes are burst write and Single light.

In the read operation specified by a column address read command, which will be described later, the above CAS latency is caused by the output buffer 21 from the fall of / CAS.
This indicates how many cycles of the internal clock signal are to be consumed before the output operation of 1. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the internal clock signal. In other words, when using a high-frequency internal clock signal, set the CAS latency to a relatively large value, and when using a low-frequency internal clock signal, set the CAS latency to a relatively small value. I do.

(2) Row address strobe / bank active command (Ac) This is a command for validating a row address strobe and selecting a memory bank by A9.
S, / RAS = low level, / CAS, / WE = high level. At this time, the address supplied to A0 to A8 is taken as a row address signal, and the signal supplied to A9 is taken as a memory bank selection signal. .
The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines. Here, it should be understood that synchronization does not mean a strict sense of phase matching, but includes a slight phase shift.

(3) Column Address Read Command (Re) This command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe, and / CS, / CAS =
Instructed by low level, / RAS, / WE = high level. At this time, column addresses supplied to A0 to A7 are taken in as column address signals. The fetched column address signal is supplied to the column address counter 207 as a burst start address.

In the burst read operation instructed thereby, a memory bank and a word line in the memory bank are selected in a row address strobe / bank active command cycle before the memory cell of the selected word line is selected. The data is sequentially selected according to the address signal output from the column address counter 207 in synchronization with the internal clock signal, and is continuously read. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column Address Write Command (Wr) When a burst write is set in the mode register 10 as a mode of the write operation, it is a command necessary to start the burst write operation, and the write operation of the write operation is performed. As a mode, when the single write is set in the mode register 10, the command is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write.

The command is: / CS, / CAS, / W
Instructed by E = low level and / RAS = high level. At this time, the addresses supplied to A0 to A7 are taken in as column address signals. The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by A8 and A9, and / C
S, / RAS, / WE = low level, / CAS = high level.

(6) Auto-refresh command This command is required to start auto-refresh, and includes / CS, / RAS, / CA
Instructed by S = low level, / WE, CKE = high level.

(7) Burst stop in full page command This command is required to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. This command is for / CS, / WE = low level, / RAS, / CA
Indicated by S = high level.

(8) No operation command (No
p) This is a command instructing that no substantial operation is performed, / CS = low level, / RAS, / CAS, / W
It is indicated by the high level of E.

In the SDRAM, when a burst operation is performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied. The row address operation in the other memory bank is enabled without affecting the operation in one memory bank. For example, the SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly addresses and control signals, are not particularly limited, but may be held for each memory bank. It has become. Alternatively, data for one word line in a memory block selected by a row address strobe / bank active command cycle is held in a latch / register 213 for a read operation before a column-related operation. I have.

Therefore, as long as the data D0 to D15 do not collide at the data input / output terminal composed of, for example, 16 bits, during execution of a command whose processing has not been completed, the command being executed is different from the memory bank to be processed. The internal operation can be started in advance by issuing a precharge command and a row address strobe / bank active command to the memory bank.

Since the SDRAM can input and output data, addresses, and control signals in synchronization with a clock signal CLK (internal clock signal), it is possible to operate a large-capacity memory similar to a DRAM at a high speed comparable to an SRAM. ,
By specifying the number of data to be accessed for one selected word line by the burst length, the selection state of the column system is sequentially switched by the built-in column address counter 207, and a plurality of data are accessed. Can be read or written continuously.

FIG. 2 is a schematic layout diagram showing an embodiment of a synchronous DRAM (dynamic RAM) to which the present invention is applied. In FIG.
In each circuit block constituting the RAM, a portion related to the present invention is shown so as to be understood, and it is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. It is formed.

The SDRAM of this embodiment has, but is not limited to, a storage capacity of about 64 megabits. The memory array is composed of four memory blocks as a whole. Two memory arrays are divided on the left and right sides with respect to the longitudinal direction of the semiconductor chip, and an address input circuit, a data input / output circuit, an input / output interface circuit including a bonding pad row, a power generation circuit, and the like are provided in a central portion. .

As described above, of the four memory blocks divided into two on the left and right and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, two blocks arranged on the upper and lower sides constitute one set. The bank 0 and the bank 1 are configured, and a main word driver MWD is arranged at the center of each bank. The main word driver MWD forms a main word line selection signal extending so as to penetrate the one memory block. One memory block is connected to dynamic memory cells having a storage capacity of 4K bits in the main word line direction and 4K bits in a complementary bit line (or data line) direction (not shown) orthogonal to the main word line direction. Since a total of four such memory blocks are provided, the memory block has a large storage capacity such as 4 × 4K × 4K = 64 Mbits.

In the figure, SAs arranged in parallel with the longitudinal direction of the semiconductor chip are sense amplifiers,
YDEC provided near the center of the chip is a column decoder. A main amplifier MA (or a sense circuit) as described later according to the present invention is provided along the column decoder YDEC. The CTRL provided at the center to divide the memory block into upper and lower parts is
The array control circuit supplies a row address decoder and a timing signal necessary for the operation of the memory array.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit line is divided into 16 by the sense amplifier SA. Although not particularly limited, as will be described later, the sense amplifier SA is configured by a shared sense method, and complementary bit lines are provided on the left and right around the sense amplifier except for the sense amplifiers arranged at both ends of the memory array. , Are selectively connected to one of the left and right complementary bit lines.

FIG. 3 is a schematic layout diagram showing an embodiment of the sub-array and its peripheral circuits. FIG. 2 exemplarily shows four subarrays SBARY among the memory arrays shown in FIG. In the drawing, the region where the sub-array SBARY is formed is shaded to distinguish the sub-word driver region, the sense amplifier region and the cross area provided around the region. The sub-array SBARY has a sub-word line SW assuming that a word line extends in a horizontal direction.
There are 256 Ls and 512 pairs of complementary bit lines. Therefore, the 256 sub-word lines SW
The 256 sub-word drivers SWD corresponding to L
The sub-array is divided into 128 units on the left and right sides. The 512 sense amplifiers SA provided corresponding to the 512 pairs of complementary bit lines BL are of the shared sense amplifier type as described above, and are divided and arranged in 256 units above and below the sub-array.

The sub-array SBARY has 512 regular sub-word lines SWL and a spare word line (not shown) in addition to the normal sub-word lines SWL. Therefore, the 512 sub-word lines SWL and the sub-word drivers SWD corresponding to the spare word lines are separately arranged on the left and right sides of the sub-array. As described above, the lower right sub-array is composed of 512 pairs of complementary bit lines BL, and 256 sense amplifiers are arranged vertically as described above. The 256 pairs of complementary bit lines formed in the upper and lower sub-arrays SBARY on the right side are commonly connected to the sense amplifier SA interposed therebetween via a shared switch MOSFET. Although not shown as above, a spare bit line is also provided, and a corresponding sense amplifier is also provided vertically.

The main word lines MWL are extended as one of them is exemplarily shown as a representative. Also,
The column selection line YS is extended in the vertical direction in the figure as one of them is exemplarily shown as a representative. A sub-word line SWL is arranged in parallel with the main word line MWL,
A complementary bit line BL (shown in the figure) is arranged in parallel with the column selection line YS. Eight sub-word selection lines FX0B to FX0F are provided for the four sub-arrays.
X7B is 4 sets (8 pieces) like the main word line MWL
Is extended to penetrate the subarray. Then, four sub-word selection lines FX0B to FX3B and F
The four lines X4B to FX7B are separately extended on the upper and lower sub-arrays. Thus, one set of sub-word select lines FX0B to FX0 for two sub-arrays
The reason for allocating the 7Bs and extending them on the sub-array is to reduce the size of the memory chip.

On the sub-array, one main word line is provided for eight sub-word lines, and a sub-word selection line is provided for selecting one of the eight sub-word lines. It is necessary. Since one main word line is formed for every eight sub word lines formed in accordance with the pitch of the memory cells, the wiring pitch of the main word lines is gentle. Therefore, it is relatively easy to form the sub-word selection line between the main word lines using the same wiring layer as the main word line.

If the one extending in parallel with the main word line MWL is a first sub-word select line FX0B,
A second, which is provided in the upper left cross area and supplies a selection signal to the vertically arranged sub-word drivers via a sub-word selection line driving circuit FXD which receives a selection signal from the first sub-word selection line FX0B. A sub word line FX0 is provided. The first sub-word selection line FX0B extends in parallel with the main word line MWL and the sub-word line SWL, while the second sub-word selection line has a column selection line YS and a complementary bit line BL which are orthogonal thereto. It is extended in parallel. In contrast to the eight first sub-word selection lines FX0B to FX7B, the second sub-word selection lines FX0 to FX7 have even numbers FX0, FX0,
2, 4 and 6, and the odd numbers FX1, 3, 5, and 7 are distributed to sub-word drivers SWD provided on the left and right of the sub-array SBARY.

The sub word select line driving circuit FXD is
In the same drawing, as shown by a triangle, two pieces are distributed above and below one cross area. That is, as described above, in the upper left cross area, the sub-word selection line driving circuit arranged on the lower side operates the first sub-word selection line F
Two sub-word selection line driving circuits FXD corresponding to X0B and provided in the cross area of the left middle part correspond to the first sub-word selection lines FX2B and FX4B, and are provided on the upper side provided in the lower left cross area. The arranged sub-word selection line driving circuit operates the first sub-word selection line FX.
6B.

In the cross area at the upper center, the sub word select line driving circuit arranged on the lower side corresponds to the first sub word select line FX1B, and the two sub word select line driving circuits provided in the cross area at the center middle part are driven. Circuit FXD
Correspond to the first sub-word selection lines FX3B and FX5B, and the upper sub-word selection line drive circuit provided in the cross area at the lower center corresponds to the first sub-word selection line FX7B. In the upper right cross area, the lower sub word select line drive circuit corresponds to the first sub word select line FX0B, and two sub word select line drive circuits provided in the right middle cross area. FXD corresponds to the first sub-word selection lines FX2B and FX4B, and the upper sub-word selection line driving circuit provided in the lower right cross area corresponds to the first sub-word selection line FX6B. As described above, the sub-word driver provided at the end of the memory array drives the sub-word line SWL only on the left side since there is no sub-array on the right side.

In the configuration in which the sub-word selection lines are arranged between the pitches of the main word lines on the sub-array as in this embodiment, a special wiring channel is not required, so that 1
Even if eight sub-word selection lines are arranged in one sub-array, the memory chip does not become large. However, the sub-word selection line driving circuit F
The area is increased to form the XD, which hinders high integration. That is, in the cross area, a switch circuit IOS provided corresponding to the main input / output line MIO and the sub input / output line LIO as shown by the dotted line in FIG.
This is because there is no area allowance because peripheral circuits such as W, a power MOSFET for driving the sense amplifier, a drive circuit for driving the shared switch MOSFET, and a drive circuit for driving the precharge MOSFET are formed.

In the sub-word driver, the second word
Are provided in parallel with the sub-word selection lines FX0 to FX6, etc., for passing selection signals corresponding to the first sub-word selection lines FX0B to FX6B. However, since the load is small as described later, 2 sub-word select line F
X0 to X6 are provided by wiring directly connected to the first sub-word selection lines FX0B to FX6B without providing a special driver FXD. However, the same wiring layer as the second sub-word selection lines FX0 to FX6 is used.

Among the cross areas, those arranged in the extension direction A of the second sub-word selection lines FX0 to FX6 corresponding to the even numbers have a constant voltage with respect to the sense amplifier as indicated by P in FIG. N for supplying the internal voltage VDL
A channel-type power MOSFET, a P-channel type power MOSFET that supplies a clamp voltage VDDCLP for overdrive to the sense amplifier as described later with respect to the sense amplifier as indicated by O, and an N as indicated by O. An N-channel power MOSFET for supplying the circuit ground potential VSS to the sense amplifier is provided.

Of the above cross areas, those arranged in the extending direction B of the second sub-word selection lines FX0 to FX6 corresponding to the odd numbers include, as shown by B in FIG. An N-channel drive MOSFET for turning off the MOSFET,
The circuit ground potential V with respect to the sense amplifier
N-channel type power MOSF for supplying SS
An ET is provided. This N-channel type power MOS
FET is an amplifying MOSFET of an N-channel type MOSFET constituting a sense amplifier from both sides of a sense amplifier row.
Are supplied with a ground potential. That is, for the 128 or 130 sense amplifiers provided in the sense amplifier area, the N-channel type power MOSFET provided in the cross area on the A side and the N-channel power MOSFET provided in the cross area on the B side are provided. The ground potential is supplied by both of the channel type power MOSFETs.

As described above, the sub word line drive circuit SWD
Selects the sub-word lines of the sub-arrays on both sides with respect to the center. On the other hand, two sense amplifiers are activated corresponding to the selected sub-word lines of the two sub-arrays. That is, when the sub-word line is set to the selected state, the address selection MOSFET is turned on and the charge of the storage capacitor is combined with the bit line charge, so that the sense amplifier is activated to return to the original charge state. This is because a write operation needs to be performed.
For this reason, except for those corresponding to the subarrays at the ends, the power MOSFETs denoted by P, O and N
Is used to activate the sense amplifiers on both sides of it. On the other hand, in the sub-word line driving circuit SWD provided on the right side of the sub-array provided at the end of the memory array, only the sub-word lines of the sub-array are selected. Activates only the sense amplifier corresponding to the sub-array.

The sense amplifier is of a shared sense type, and among the sub-arrays disposed on both sides of the shared amplifier, the shared switch MOSFET corresponding to the complementary bit line on the non-selected side of the sub-word line is turned off. As a result, the read signal of the complementary bit line corresponding to the selected sub-word line is amplified, and a rewrite (refresh) operation of returning the storage capacitor of the memory cell to the original charge state is performed.

FIG. 4 shows a synchronous D according to the present invention.
FIG. 2 is a schematic layout diagram showing an example of a well region forming a sub-array and its peripheral circuit in a RAM. FIG. 2 exemplarily shows eight subarrays SBARY in the memory array shown in FIG.

In the figure, the white portion is a P-type substrate (P
SUB). The ground potential VSS of the circuit is applied to the P-type substrate PSUB. The above P-type substrate PSU
B has two types of N-type well regions N as indicated by hatching.
WELL (VDL) and NWELL (VDDCLP) are formed. That is, the N-type well region in which the P-channel type amplification MOSFET forming the sense amplifier SA is formed and the N-type well region in which the power switch MOSFETs arranged in the cross area of the column A are formed are boosted voltages. A clamp voltage VDDCLP formed using VPP is supplied.

In the cross area of the column B, a P-channel MOSFET constituting a switch circuit IOSW provided corresponding to the sub-input / output line LIO and P-channel MOSFETs provided for the main input / output line for precharging and equalizing are provided. An N-type well region where a channel type MOSFET is formed is formed, and an internal voltage VDL formed by stepping down is supplied.

Sub-array and sub-word line drive circuit SW
The entire region where D is formed has N formed at a deep depth.
A mold well region DWELL is formed. The N-type well region having the deep depth is supplied with the boosted voltage VPP corresponding to the word line selection level. The sub-word line driving circuit S
An N-type well region NWWLL in which a P-channel MOSFET constituting WD is formed is formed, and a boost voltage VPP is applied in the same manner as in the deep N-type well region DWELL.

The deep N-type well region DWELL
A P-type well region PWELL for forming an N-channel address selection MOSFET constituting a memory cell and an N-channel MOSFET of a sub-word drive circuit SWD is formed in the memory cell. These P-type well regions P
WELL is supplied with a substrate back bias voltage VBB which is set to a negative voltage.

In the memory array of FIG. 2, one of the four divided memory arrays has a depth N
The mold well region DWELL is formed by arranging 16 subarrays arranged in the word line direction as one unit, and 16 subarrays in the bit line direction in total. Then, the cross areas corresponding to the sub-word drivers (Sub-Word Drivers) arranged at both ends of the main word line extending on the array are the A rows, and are arranged alternately like the B rows as described above. You. Therefore, except for the end portion, the row A and the two sense amplifiers (Se
An N-type well region NWELL (VDDCLP) for forming a P-channel MOSFET of a nce amplifier is provided in common.

FIG. 5 shows a synchronous D according to the present invention.
FIG. 2 shows a main part circuit diagram of an embodiment of a sense amplifier section of a RAM and peripheral circuits thereof. FIG. 1 exemplarily shows a sense amplifier arranged between two subarrays from the left and right and circuits related thereto. The well region where each element is formed is shown by a dotted line, and the bias voltage applied thereto is also shown.

As the dynamic memory cell, one provided between the sub-word line SWL provided in the one sub-array and one of the complementary bit lines BL and / BL is exemplarily shown as a representative. ing. The dynamic memory cell includes an address selection MOSFET Qm and a storage capacitor Cs. Address selection MOS
The gate of the FET Qm is connected to the sub-word line SWL, the drain of the MOSFET Qm is connected to the bit line BL, and the storage capacitor Cs is connected to the source.
The other electrode of the storage capacitor Cs is shared and receives a plate voltage. The selection level of the sub-word line SWL is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.

The sense amplifier described below is connected to the internal step-down voltage VD
When operating at L, the high level amplified by the sense amplifier and applied to the bit line is set to a level corresponding to the internal voltage VDL. Therefore, the high voltage VPP corresponding to the word line selection level is VD
L + Vth + α. The pair of complementary bit lines BL and / BL of the subarray provided on the left side of the sense amplifier are arranged in parallel as shown in FIG. Can be
These complementary bit lines BL and / BL are connected to input / output nodes of a unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2.

The unit circuit of the sense amplifier is composed of N-channel type amplifying MOSFETs Q5, Q6 and P-channel type amplifying MOSFETs Q7, Q8, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CS.
Connected to P. Each of the common source lines CSN and CSP is provided with a power switch MOSFET. Although not particularly limited, an N-channel type amplification MOS
Common source line C to which the sources of FETs Q5 and Q6 are connected
SN is the N provided in the cross area between the A and B sides.
Channel type power switch MOSFETs Q12 and Q
13 provides an operating voltage corresponding to the ground potential.

Although not particularly limited, the common source line CSP to which the sources of the P-channel type amplification MOSFETs Q7 and Q8 are connected is connected to the overdrive P-channel type power M provided in the A-side cross area.
OSFET Q15 and N for supplying the internal voltage VDL
A channel type power MOSFET Q16 is provided. The overdrive voltage is a boosted voltage VPP
Is supplied to the gate of the N-channel MOSFET Q1
4 is used. The power supply voltage VDD supplied from an external terminal is supplied to the drain of the MOSFET Q14,
The SFET Q14 is operated as a source follower output circuit, and the MOSFET Q1
Clamp voltage VDDC lowered by the threshold voltage of 4.
Form LP.

Although not particularly limited, the boosted voltage VPP
Is controlled by using the reference voltage to operate the charge pump circuit, and is set to a stabilized high voltage such as 3.8V. The threshold voltage of the MOSFET Q14 is formed at a low threshold voltage lower than the address selection MOSFET Qm of the memory cell, and the clamp voltage VD
DCLP is brought to a stabilized constant voltage such as about 2.9V. The MOSFET Q26 is a MOSFET that forms a leak current path, and allows only a very small current of about 1 μA to flow. This prevents the VDDCLP from excessively rising due to the standby state (non-operating state) for a long period of time or the bump of the power supply voltage VDD, and the amplifying MOS to which the voltage VDDCLP at the time of such excessive increase is applied.
The operation delay due to the back bias effect of the FETs Q7 and Q8 is prevented.

In this embodiment, noting that the overdrive voltage of the sense amplifier is formed by the clamp voltage VDDCLP as described above, a P-channel type power MOSFET Q15 for supplying the voltage,
P channel type amplification MOSFET Q of sense amplifier
7, Q8 are formed in the same N-type well region NWELL as shown by the dotted line in the same figure, and the clamp voltage VDDCLP is supplied as the bias voltage. Then, a P-channel type amplifier M of the sense amplifier
The power MOSFET Q16 for applying the original operating voltage VDL to the common source line CSP of the OSFETs Q7 and Q8 has N
MOSF for overdrive as the channel type
It is formed electrically separated from the ETQ 14.

The above N-channel type power MOSFET
Sense amplifier activation signal S supplied to the gate of Q15
AP2 is an overdrive activation signal / S supplied to the gate of the P-channel MOSFET Q15.
The signal has a phase opposite to that of AP1, and although not particularly limited, a high level thereof is a signal corresponding to the power supply voltage VDD. That is, as described above, VDDCLP is approximately +2.9.
V, which is the minimum allowable voltage VDDmi of the power supply voltage VDD.
Since n is about 3.0 V, the P-channel MO
The SFET Q15 can be turned off, and the N-channel MOSFET Q16 has a low threshold voltage.
Can be output.

An equalizing MOSF for short-circuiting the complementary bit line is provided at the input / output node of the unit circuit of the sense amplifier.
A precharge circuit including ETQ11 and switch MOSFETs Q9 and Q10 for supplying a half precharge voltage to a complementary bit line is provided. These MOSFETs
The gates of Q9 to Q11 share the precharge signal BL
EQ is supplied. The driver circuit for forming the precharge signal BLEQ provides an N-channel MOSFET Q18 in the cross area on the B side to make the falling speed faster. That is, in order to advance the word line selection timing at the start of the memory access, the N-channel MOSFETs Q18 provided in the respective cross areas are turned on and the MOSFs constituting the precharge circuit are turned on.
ETQ9 to Q11 are switched off at high speed.

On the other hand, a P-channel MOSFET Q17 for forming a signal for starting a precharge operation is provided.
Is provided not in the cross area as described above, but in the array control unit. In other words, the precharge operation is started at the end of the memory access, but since the operation has a margin in time, it is not necessary to make the rising of the signal BLEQ fast. As a result, the P-channel MOSFET provided in the A-side cross area is only the power MOSFET Q15 for overdrive, and the P-channel MOSFET provided in the B-side cross area is P-channel MOSFET.
Can be made only of MOSFETs constituting a precharge circuit for precharging the MOSFETs Q24 and Q25 and the main common input line MIO to the internal voltage VDL, which will be described next. The above-mentioned VDDCLP is provided in these N-type well regions.
Since a bias voltage such as (cross area A) and the above VDL (cross area B) is applied, one type of N-type well region is formed, and no parasitic thyristor element is formed.

The unit circuit of the sense amplifier is connected to similar complementary bit lines BL and / BL of the right sub-array via shared switch MOSFETs Q3 and Q4. The switch MOSFETs Q12 and Q13 constitute a column switch circuit, and upon receiving the selection signal YS, connect the input / output node of the unit circuit of the sense amplifier to the sub-common input / output line LIO. For example, when the sub word line SWL of the left sub array is selected, the right shared switch MOSFETs Q3 and Q4 of the sense amplifier are selected.
Are turned off. As a result, the input / output node of the sense amplifier is connected to the left-side complementary bit lines BL and / BL, amplifies the minute signal of the memory cell connected to the selected sub-word line SWL, and passes through the column switch circuit. It is transmitted to the sub common input / output line LIO. The sub common input / output line is connected to the N side provided in the cross area on the B side.
It is connected to a main input / output line MIO connected to an input terminal of a main amplifier via a switch circuit IOSW composed of channel type MOSFETs Q19 and Q20 and the P-channel type MOSFETs Q24 and Q25.

Although not particularly limited, the column switch circuit connects a pair of complementary bit lines to a pair of sub-common input / output lines LIO by one selection signal. Therefore 1
In the sub-array selected by the operation of selecting one main word line, a total of two pairs of complementary bit lines are selected by the pair of column switch circuits provided corresponding to the pair of sense amplifiers provided on both sides thereof. . The signal of the main common input / output line MIO is supplied to a main amplifier (sense circuit) MA (not shown). As described above, the main common input / output line MIO is precharged by the internal step-down voltage VDL as described above, and the amplified signal of the sense amplifier is transmitted through the local input / output line LIO and the main common input / output line MIO. The signal amplitude is set to a small amplitude based on the internal step-down voltage VDL, and is amplified by the main amplifier MA to a CMOS level corresponding to the power supply voltage VDD.

The sub-word line drive circuit SWD includes a P-channel MOSFET Q21 formed in the deep N-type well region DWELL (VPP), one of which is exemplarily shown as a representative. D
The P-type well region PWELL (V
N-channel MOSFET Q22 formed in BB)
And Q23. Inverter circuit N1
Although it is not particularly limited, it constitutes the sub-word select line drive circuit FXD, and is provided in the cross area as described above. The address selection MOSFET Qm of the memory cell is also formed in the P-type well region PWELL (VBB) formed in the DWELL.

FIG. 6 is a main block diagram for explaining the relationship between the main word lines and the sub word lines of the sub array. This figure mainly explains the circuit operation, and omits the geometrical arrangement of the sub-word selection lines as described above and collectively shows the sub-word selection lines FX0B to FX7B. In the figure, two main word lines MWL0 and MWL1 are shown as representatives for explaining the sub-word line selection operation. These main word lines MWL0 are selected by a main word driver MWD0. The other main word line MWL1 is similarly selected by a main word driver similar to the above.

The one main word line MWL0 has:
Eight sets of sub-word lines are provided in the extending direction. FIG. 2 exemplarily shows two sets of the sub-word lines as representatives. The sub word line is even 0 to
A total of eight sub-word lines 6 and odd numbers 1 to 7 are alternately arranged in one sub-array. Except for even numbers 0 to 6 adjacent to the main word driver and even numbers 0 to 6 arranged on the far end side (opposite side of the word driver) of the main word line,
The sub-word driver arranged between the sub-arrays drives the sub-word lines of the left and right sub-arrays centered on the sub-word driver.

Thus, although the sub-array is divided into eight as described above, the sub-word driver SWD substantially selects the sub-word lines corresponding to the two sub-arrays on both sides at the same time. Will be divided into four sets. In the configuration in which the sub-word lines SWL are divided into even numbers 0 to 6 and odd numbers 1 to 7 as described above, and the sub-word drivers SWD are arranged on both sides of the memory block, respectively, The substantial pitch of the SWL can be relaxed twice in the sub-word driver SWD, and the sub-word driver SWD and the sub-word line SWL
Can be efficiently laid out on a semiconductor chip.

In this embodiment, the sub-word driver SWD supplies a selection signal from the main word line MWL to four sub-word lines 0 to 6 (1 to 7) in common. A sub-word select line FXB for selecting one sub-word line from the four sub-word lines is provided. The sub-word selection lines are composed of eight lines FXB0 to FXB7, of which even-numbered FXB0 to FXB6 are supplied to the even-numbered sub-word drivers 0 to 6, and odd-numbered FXB1 to FXB7 are odd-numbered sub-word drivers 1 to 7 of the odd-numbered columns. Supplied to

The sub word select lines FXB0 to FXB7 are
On the sub-array, the second metal wiring layer M2
And a second sub-word select line extending in parallel with the main word lines MWL0 to MWLn also formed by the second metal wiring layer M2, and a second sub-word extending in a direction orthogonal thereto. Consists of a selection line.
Although not particularly limited, the second sub-word selection line is
A third metal wiring layer M3 is provided to cross the main word line MWL.

The sub-word driver SWD has a main word line M as one of them is illustratively shown.
The input terminal is connected to WL, and the sub-word line S is connected to the output terminal.
A first CM including a P-channel MOSFET Q21 and an N-channel MOSFET Q22 to which WL is connected.
An OS inverter circuit and a switch MOSFET Q23 provided between the sub-word line SWL and the ground potential of the circuit and receiving the sub-word selection signal FXB. The gate of this switch MOSFET Q23 is FX
In order to connect to B and to connect each of the MOSFETs Q21 to FX, a total of eight sub-word select lines of FX and FXB are arranged along a sub-word driver row composed of 0, 2, 4, and 6. However, it is represented by a single line in FIG.

A second CMOS inverter circuit N1 for receiving the above-mentioned sub-word selection signal FXB and forming an inverted signal FX thereof is provided as a sub-word selection line driving circuit FXD. P-channel MOSFET Q2 which is a terminal
1 to the source terminal. The second CMOS inverter circuit N1 is not particularly limited, but has a boosted voltage VPP
And is formed in the cross area as shown in FIG.
Commonly used corresponding to a plurality of sub-word drivers SWD.

In the above configuration of the sub-word driver SWD, when the main word line MWL is at a high level such as the boosted voltage VPP corresponding to the word line selection level, the N-channel type of the first CMOS inverter circuit The MOSFET Q22 is turned on, and the sub-word line SWL is set to a low level such as the ground potential of the circuit. At this time, the sub-word selection signal FXB becomes a low-level selection level such as the ground potential of the circuit, and the output signal of the second CMOS inverter circuit N1 as the sub-word selection line driving circuit FXD becomes the selection level corresponding to the boosted voltage VPP. However, depending on the non-selection level of the main word line MWL, the P-channel MOSFET Q2
Since 1 is in the OFF state, the sub-word line SWL is set to the non-selected state due to the ON state of the N-channel MOSFET Q22.

When the main word line MWL is at a low level such as the ground potential of the circuit corresponding to the selected level, the N-channel type MO of the first CMOS inverter circuit is
The SFET Q22 is turned off, and the P-channel type MO
SFET Q21 is turned on. At this time, if the sub-word selection signal FXB is at a low level such as the ground potential of the circuit, the output signal of the second CMOS inverter circuit N1 as the sub-word selection line driving circuit FXD is set to the selection level corresponding to the boosted voltage VPP. , The sub word line SWL is set to a selection level such as VPP. If,
If the sub-word selection signal FXB is at a non-selection level such as the boosted voltage VPP, the second CMOS inverter circuit N
2 becomes low level, and at the same time, N
The channel type MOSFET Q23 is turned on to set the sub-word line SWL to the low level non-selection level.

The main word line MWL and the first sub-word select line FXB arranged in parallel to the main word line MWL are both set to a non-selection level such as VPP as described above. Therefore, even when an insulation failure occurs between the main word line MWL and the first sub-word selection line FXB arranged in parallel when the RAM is in the non-selection state (standby) state, leakage current flows. There is no. As a result, the first sub-word selection line FXB can be formed between the main word lines MWL and arranged on the sub-array, and the DC failure due to the above-described leakage current can be avoided even when the layout density is increased. It will be reliable.

FIG. 7 is a main block diagram for explaining the relationship between the main word lines of the memory array and the sense amplifiers. In FIG.
Two main word lines MWL are shown. This main word line MWL is selected by the main word driver MWD. A sub-word driver SW corresponding to the even-numbered sub-word line adjacent to the main word driver
D is provided.

Although not shown in the figure, a complementary bit line (Pair Bit Line) is provided so as to be orthogonal to a sub-word line arranged in parallel with the main word line MWL. In this embodiment, although not particularly limited, the complementary bit lines are also divided into even columns and odd columns, and the sense amplifiers SA are distributed to the left and right corresponding to the respective sub-arrays (memory cell arrays). The sense amplifier SA is of the shared sense type as described above. In the sense amplifier SA at the end, although substantially one complementary bit line is not provided, the sense amplifier SA is connected to the complementary bit line via a shared switch MOSFET. Connected.

In the configuration in which the sense amplifiers SA are dispersedly arranged on both sides of the memory block as described above, since the complementary bit lines are distributed to the odd columns and the even columns, the pitch of the sense amplifier columns can be reduced. it can. In other words, it is possible to secure element areas for forming the sense amplifiers SA while arranging complementary bit lines at high density. The sub input / output lines are arranged along the arrangement of the sense amplifiers SA. This sub input / output line is connected to the complementary bit line via a column switch. The column switch is composed of a switch MOSFET. The gate of the switch MOSFET is connected to a column selection line YS to which a selection signal of a column decoder COLUMN DECORDER is transmitted.

FIG. 8 is a sectional view of an element structure for explaining a dynamic RAM (synchronous DRAM) according to the present invention. In this embodiment, the element structure of the memory cell section as described above is exemplarily shown as a representative. The storage capacitor of the memory cell uses the second polysilicon layer as the storage node SN, and has one source and drain SD of the address selection MOSFET.
Connected to The storage node SN made of the second polysilicon layer has a crown structure, and has a plate electrode P made of the third polysilicon layer via a thin gate insulating film.
L is formed. MOSFE for address selection
The gate of T is formed integrally with the sub-word line SWL, and is formed of a first polysilicon layer and tungsten silicide (WSi) formed thereon. The other source and drain of the address selection MOSFET are connected to a bit line BL formed of a polysilicon layer and the same tungsten silicide provided above the polysilicon layer. A main word line MWB composed of a second metal layer M2 and a sub-word select line FXB are formed above the memory cell, and a Y select line YS composed of a third metal layer M3 is formed above the main word line MWB. Alternatively, a sub-word selection line FX is formed.

Although not shown in the figure, an N-channel MOSFET and a P-channel MOSFET which constitute a sub-word driver SWD and the like are provided around the memory cell portion.
An OSFET is formed. Although not shown, a first metal layer is formed to configure these peripheral circuits. For example, an N-channel type MOSFET and a P-channel type MO are used to constitute the above CMOS inverter circuit.
The first metal layer M1 is used for the wiring connecting the gate to the SFET. The connection between the input terminal of the CMOS inverter circuit and the main word line MWB including the second metal layer M2 is dropped to a first metal layer M1 as a dummy through a through hole. Is connected to the gate electrode via the contact and the wiring layer M1.

When connecting the Y selection line YS formed by the third metal layer M3 to the gate of the column selection switch MOSFET, or by connecting the sub word line selection line FX formed by the metal layer M3 and the P channel The connection to the source and the drain of the MOSFET is dropped to the metal layer M2 and the metal layer M1 as the dummy through a through hole, and the column switch MOS is dropped.
It is connected to the gate of the FET and the source and drain of the P-channel MOSFET.

When adopting the element structure as in this embodiment,
As described above, the second metal layer M2 constituting the main word line intersects with the portion of the second metal layer M2 extending in parallel with the second metal layer M2 or the metal layer M2 of the main word line. When a defect occurs in the insulating film between the third word layer M3 and the sub-word selection line, a non-negligible leak current flows. Such a leak current itself is practically no problem if it does not affect the read / write operation of the memory cell, but causes a problem of a current failure in a non-selected state. In the present invention, as described above, the main word line M
Since the WB and the sub-word select line FXB are in the non-selected state at the same potential, the above-described leakage current does not occur.

When a read / write operation of a memory cell is defective due to the generation of a leak current between the main word line MWB and the sub-word select line FXB, the memory cell is replaced with a spare main word line. However, the defective main word line MWB remains as it is, resulting in the leakage current continuing to flow to the main word line MWB. The occurrence of the leak current as described above does not affect the reading and writing operations of the memory itself as a result of replacing the main word line MWB with the spare main word line. However, the DC current increases, which leads to deterioration of the performance of the product. In the worst case, the DC failure occurs, so that the defect relief circuit cannot be used. Can be avoided.

FIG. 9 is a circuit diagram showing one embodiment of the main amplifier (sense circuit) MA used in the SDRAM according to the present invention. The main input / output line MIO
Input signals VIN and VIN # transmitted through
(Here, # indicates that the low level is the active level corresponding to /) is supplied to the gates of the differential N-channel MOSFETs M4 and N5.
An N-channel MOSFET N6 which receives an operation timing signal MA1 and forms an operation current of the differential MOSFETs N4 and N5 is provided between the common source of these differential MOSFETs N4 and N5 and the ground potential Vss of the circuit.
Is provided.

The drains of the differential MOSFETs N4 and N5 are connected to a first CMOS inverter circuit composed of a P-channel MOSFET P1 and an N-channel MOSFET N1, and a second CMOS inverter circuit composed of a P-channel MOSFET P2 and an N-channel MOSFET N2. The input and output are connected to such an input / output node of a CMOS latch circuit configured by cross-connecting each other. The sources of the P-channel MOSFETs P1 and P2 constituting the first and second CMOS inverter circuits are:
Connected to power supply voltage VDD supplied from an external terminal.
The sources of the N-channel MOSFETs N1 and N2 of the first and second CMOS inverter circuits are commonly connected, and the first and second CMOS inverter circuits receive the operation timing signal MA1 between the sources and the ground potential Vss. N-channel type MOSFET that forms operating current in inverter circuit
N3 is provided.

The input / output nodes of the first and second CMOS latch circuits are connected to complementary output signal lines VOUT and VOUT #.
Connected to. A P-channel type MO for precharging the output signal lines VOUT and VOUT # to a power supply voltage VDD
SFETs P3 and P4, and output lines VOUT and VOUT
An equalizing circuit including a P-channel MOSFET P5 for short-circuiting # is provided. These MOSFETP
The equalizing signal EQ # is supplied to the gates 3 to P5.

FIG. 10 is a timing chart for explaining an example of the operation of the main amplifier (sense circuit) MA shown in FIG. In this embodiment, the main amplifier MA
For high-speed operation. Equalize signal EQ #
Is set to a low level, and the output signal lines VOUT and VO
While the UT # is being precharged to the power supply voltage VDD, the operation timing signal MA1 is changed from a low level to a high level, and the MOSFETs N6 and N3 are turned on. That is, the operation timing signal MA1 is changed to the high level at the timing T1, and the equalization signal EQ # is changed to the high level at the timing T2 after a certain time has elapsed. In this case, when the input signals VIN and VIN # applied to the gates of the differential MOSFETs N4 and N5 have only a small difference voltage, the differential MOSFETs N4 and N5 start the amplifying operation, and the amplified signal Output.

At this time, the CMOS latch circuit also has a MOSF corresponding to the high level of the operation timing signal MA1.
The operation starts in response to the ON state of ETN3, but since the current supply from the power supply voltage VDD is also continued by the equalizing circuit, the differential MOSFET N
It operates as a differential amplifier circuit that receives the amplified signals of Nos. 4 and N5, and starts the operation of amplifying the small signal.

When the equalizing signal EQ # changes to the high level, the MOSFETs P3 to P5 are turned off, the potential difference between the output signal lines VOUT and VOUT # decreases while widening, and the low-level potential becomes the P-channel MOSFET. , The P-channel MOSFET receiving it is turned on, and the high-level output signal is raised to the power supply voltage VDD. As in this embodiment, the equalizing signal EQ
By generating the operation timing signal MA1 ahead of #, the operation can be speeded up. That is,
This is because if the equalizing signal EQ # is returned to the high level and the end timing of the equalizing operation is adjusted to generate the operation timing signal MA1, the start timing of the sense amplification operation is delayed accordingly. In this embodiment, the input signals VIN and VIN # are supplied to the gates of the differential MOSFETs N4 and N5 and are electrically separated from the output signal lines VOUT and VOUT #. It can be realized.

That is, as the main amplifier MA,
As shown in FIG. 23, when a latch type sense circuit composed of the latch circuit composed of the first and second CMOS inverter circuits and the MOSFET N3 for operation control is adopted, the input and output become Since it is directly connected, it is necessary to start the operation after the equalization is completed and a desired signal potential difference is generated in the input signal, and the voltage is lowered with respect to the external power supply voltage VDD as in the dynamic RAM. When the input signals VIN and VIN # are formed using the applied voltage VDL, the input signals VIN and VIN # are supplied from the power supply voltage VDD side of the main amplifier MA.
A current flows into the main input / output line MIO to which N # is transmitted, and the input signals VIN and VIN # become higher than the internal step-down voltage VDL. When the potential of the main input / output line MIO becomes higher than VDL in this manner, the operation of the equalizing circuit of the main input / output line MIO as shown in FIG. 5 may be disabled and a malfunction may occur. .

On the other hand, as the main amplifier MA, a differential circuit composed of differential MOSFETs N1, N2 and MOSFET N3 as shown in FIG. When a cross-coupled sense circuit provided with channel type MOSFETs P1 and P2 is employed, the minute input signals VIN and VIN # stepped down as described above are converted to the power supply voltage VD.
It takes time to amplify the output signal to a CMOS level corresponding to D and the ground potential Vss, and the amplification operation speed is insufficient for operating the sense circuit with a short pulse of about several ns (nanoseconds) as in the SDRAM. Is what you do.

In the main amplifier MA according to the present invention, the differential MOSFETs N4 and N5 are combined with a CMOS latch circuit using first and second CMOS inverter circuits, and the differential amplifier having a high input impedance is provided on the input side. A high-speed, high-gain CMOS latch circuit is arranged on the output side by arranging a driving circuit, thereby ensuring high-speed operation speed and preventing malfunction due to a difference in operation potential such as VDL and VDD as described above. To make it possible.

FIG. 11 is a timing chart for explaining another example of the operation of the main amplifier (sense circuit) MA shown in FIG. This embodiment is aimed at achieving both high speed and low power consumption of the main amplifier MA. At the same timing T1, the precharge operation is completed by changing the equalizing signal EQ # from the low level to the high level, and the operation timing signal MA1 is changed from the low level to the high level.
3 is turned on. That is, the operation start timing of the sense circuit is set in accordance with the end timing of the equalizing operation. In this case, since the direct sensing operation is possible as described above, even if the timing signals EQ # and MA1 slightly overlap or a time difference occurs, there is no operational problem, and the timing design can be easily performed. it can.

FIG. 12 is a timing chart for explaining still another example of the operation of the main amplifier (sense circuit) MA shown in FIG. This embodiment is directed to low power consumption of the main amplifier MA. Timing T
2, the precharge operation is completed by changing the equalizing signal EQ # from low level to high level, and then at timing T1 later than that, the operation timing signal MA1 is changed from low level to high level to turn on the MOSFETs N6 and N3. Let it be in a state. That is, the operation of the sense circuit is started after the equalizing operation is completed. In this case, when the potential difference between the input signals VIN and VIN # becomes large, the differential MOSFETs N4 and N5 perform an amplification operation, and the CMOS latch circuit receives the amplified output signal to perform the amplification operation. DC current flowing between the power supply and the ground potential VSS can be greatly reduced.

FIG. 13 is a circuit diagram showing another embodiment of the main amplifier (sense circuit) MA. In this embodiment, the operation timing signal MA1 applied to the gate of an N-channel type MOSFET N6 for flowing an operation current through the differential MOSFETs N4 and N5 and the CMOS
N-channel type MOSFE for flowing operating current to latch circuit
Operation timing signal MA2 applied to the gate of TN3
And supply them separately. Another configuration is shown in FIG.
This is the same as the embodiment.

FIG. 14 is a timing chart for explaining an example of the operation of the main amplifier (sense circuit) MA shown in FIG. This embodiment is directed to a high-speed operation of the main amplifier MA. The equalizing signal EQ # is set to low level, and the output signal line VOUT
While VOUT # and VOUT # are precharged to the power supply voltage VDD, the operation timing signal MA1 is changed from a low level to a high level, and the MOSFET N6 is turned on. That is, the operation timing signal MA1 is changed to the high level at the timing T1, and at the timing T2 after the elapse of a predetermined time, the equalization signal E1
Q # is changed to a high level.
In this case, when the input signals VIN and VIN # applied to the gates of the differential MOSFETs N4 and N5 have only a small difference voltage, the differential MOSFETs N4 and N5 start the amplifying operation and the amplified signals are sent to the drains. Output.

At this time, also in the CMOS latch circuit, the operation timing signal MA2 is still at the low level, and the MOSFET N3 is in the off state.
Therefore, the differential MOSFETs N4 and N5 and the C
P-channel type MOSFE constituting a MOS latch circuit
Although TP1 and P2 operate as a cross-coupled sense circuit, since the equalizing circuit is still operating, it is slightly different from a strictly meaningful cross-cup type sensing circuit. Type MOSFETs P3 and P4 are differential MOSFETs N4 and N
5 to form an amplified signal.

At timing T2, the equalizing signal EQ # is changed from low level to high level to
OSFETs P3 to P5 are turned off. In this state, the differential MOSFETs N4 and N5 and the CMOS
P-channel MOSFET P1 constituting a latch circuit
And P2 to operate as a cross-coupled sense circuit to increase the potential difference between the upper output signal lines VOUT and VOUT #. Then, at the timing T3, the operation timing signal MA2 is changed from the low level to the high level, and the MOSFET N3 is turned on. That is,
At timing T3, the operation of the CMOS latch circuit is started to amplify the output signal formed by the cross-coupled sense circuit, and at timing T4, the output signal is expanded to a CMOS level such as the power supply voltage VDD and the ground potential Vss. Through a series of operations as described above, a high-speed read operation is realized while suppressing the generation of a direct current in the CMOS latch circuit.

FIG. 15 is a timing chart for explaining another example of the operation of the main amplifier (sense circuit) MA shown in FIG. This embodiment is directed to low power consumption of the main amplifier MA. After the precharge operation is completed by changing the equalizing signal EQ # from low level to high level at the timing T2, the operation timing signal MA1 is changed from low level to high level at the later timing T1 to turn on the MOSFET N6. Let That is,
After the equalizing operation is completed, the differential MOSFET N4
And N5 and P-channel MOS of CMOS latch circuit
The operation of the cross-coupled sense circuit is started using the FETs P1 and P2. In this case, the differential MOSFETs N4 and N5 perform the amplification operation when the potential difference between the input signals VIN and VIN # becomes large.

At timing T3, the operation timing signal MA2 is changed from low level to high level to turn on the MOSFET N3. That is, the operation of the CMOS latch circuit is started at the timing T3, the output signal formed by the cross-coupled sense circuit is amplified, and expanded at the timing T4 to the CMOS level such as the power supply voltage VDD and the ground potential Vss. In the above-described series of operations, the DC current flowing between the power supply voltage VDD and the ground potential Vss of the circuit is changed from the timing T1 to the timing T3.
Only a very small current during the amplification period in the cross-coupled sense circuit by the differential MOSFETs N4 and N5 and the P-channel MOSFETs P1 and P2 of the CMOS latch circuit can be realized, and a great reduction in power consumption can be realized.

In addition, as shown in FIG.
The operation of the main amplifier MA in FIG. 13 may be controlled by a combination in which A1 and EQ # are changed at the same timing, and thereafter, the operation timing signal MA2 is changed to a high level. In this case, the timing signal EQ # is inverted to form the timing signal MA1, or vice versa.
And EQ #, and the timing generation circuit can be simplified.

FIG. 16 is a circuit diagram showing still another embodiment of the main amplifier (sense circuit) MA.
In this embodiment, an operation timing signal MA1 applied to the gate of an N-channel type MOSFET N6 for flowing an operation current through the differential MOSFETs N4 and N5 is used.
It is used as a control timing signal for an equalizing P-channel MOSFET P5 for short-circuiting the output signal lines VOUT and VOUT #. Then, an N-channel MOSFET N3 for flowing an operation current to the CMOS latch circuit.
Is used as a control timing signal for precharging P-channel MOSFETs P3 and P4 for supplying the external power supply voltage VDD to the output signal lines VOUT and VOUTB by using the operation timing signal MA2 applied to the gate of the gate. In this configuration, the P-channel MOSFETs P3 to P3 constituting the equalizing / precharge circuit
5 can be omitted. Other configurations are the same as those in the embodiment of FIG.

FIG. 17 is a circuit diagram showing still another embodiment of the main amplifier (sense circuit) MA.
This embodiment is a modification of the embodiment of FIG. 16 and uses a P-channel MOSFET Q6 as a precharge circuit.
And Q7 are added. These MOSFETs Q6 and Q7
Are supplied with the operation timing signal MA1. That is, an equalizing P-channel type for short-circuiting the output signal lines VOUT and VOUT # by using the operation timing signal MA1 applied to the gate of the N-channel type MOSFET N6 for flowing an operating current to the differential MOSFETs N4 and N5. The MOSFET P5 and the added precharge MOSFETs Q6 and Q7 are simultaneously controlled. N-channel type differential MOSFE
When the operation point of the sense circuit is set by TN4 and N5 and the MOSFETs P3 and P4 as loads, the precharge characteristics of the sense circuit are set independently of the operation point setting. Exclusive P-channel MOSFETs P6 and P7 are provided. Other configurations are the same as those in the embodiment of FIG.

FIG. 18 is a timing chart for explaining an example of the operation of the main amplifier (sense circuit) MA shown in FIGS. 16 and 17. In this embodiment, the equalizing signal EQ # is omitted, and the operation timing signal MA1 is changed from a low level to a high level in the circuit of FIG.
When the SFET P5 is turned off, the differential MOSFETs N4 and N
5 is turned on. That is, at the timing T1, the operation timing signal MA1 is changed to the high level, the P-channel MOSFET P5 which short-circuits the output signal lines VOUT and VOUT # is turned off, and the N-channel MOSFET N6 is used to turn on the differential MOSFETs N4 and N5.
5, an operating current is supplied to the precharge MOSFETs P3 and P4, which are kept on at this time, to form an amplified signal having a small potential difference between the input signals VIN and VIN # using the loads as loads. In the circuit of FIG. 17, the added precharge MOSFETs P6 and P7 are connected to the equalizing P
It is turned off simultaneously with the channel type MOSFET P5.

At a timing T2 after a lapse of a predetermined time, the operation timing signal MA2 is changed from a low level to a high level to turn off the MOSFETs P3 and P4, and to supply an operating current to the CMOS latch circuit. Is turned on. In this state, the differential MOSFETs N4 and N4
5 and the CMOS latch circuit operate to operate the differential M
Output signal line VOUT amplified by OSFETs N4 and N5
The amplification operation of expanding the potential difference between VOUT # and VOUT # to the CMOS level such as the power supply voltage VDD and the ground potential Vss by the operation of the CMOS latch circuit is performed simultaneously. By changing the operation timing signal MA1 from low level to high level earlier than MA2, the sense circuit can be driven even if the input voltages VIN and VIN # are not sufficiently large. In other words, there is no need to wait until the potentials of the input voltages VIN and VIN # become sufficiently large.
A so-called direct sense operation becomes possible.

FIG. 19 is a circuit diagram showing still another embodiment of the main amplifier (sense circuit) MA.
This embodiment is a modification of the embodiment of FIG. 17, and is a P-channel MOSFET P5 forming an equalizing circuit.
The irraquoise signal EQ # is supplied to the gates .about.P7, and the precharge signal PC # is supplied to the P-channel MOSFETs P3 and P4. That is, instead of the operation timing signals MA1 and MA2 as described above, independent timing signals EQ # and PC # are supplied as described above.

FIG. 20 is a timing chart for explaining an example of the operation of the main amplifier (sense circuit) MA shown in FIG. In this embodiment, at the timing T1, the equalizing signal EQ # changes from low level to high level, and the equalizing P-channel MOSFET P5 and the precharging P-channel MOSFETs P6 and P7 are turned off.
At a timing T2 that is later than the timing T1, the operation timing signal MA1 is changed from the low level to the high level, and the N-channel MOSFET N6 that supplies an operation current to the differential MOSFETs N4 and N5 is turned on. In other words, at the timing T2, the differential MOSFET N
4 and N5, an amplifying operation of a small potential difference between the input signals VIN and VIN # is started by using the precharge MOSFETs P3 and P4, which are maintained in the ON state, as loads.

At timing T3, which is later than timing T2, the precharge signal PC # changes from low level to high level to turn off the precharge P-channel MOSFETs P3 and P4. As a result, the potentials of the output signal lines VOUT and VOUT #
It decreases while spreading due to the amplifying operation of OSFETs N4 and N5. Timing T4 delayed from the timing T3
Then, the operation timing signal MA2 changes from the low level to the high level, and the N-channel MOSFET N3 that supplies the CMOS latch circuit with the operation current is turned on. In this state, the differential MOSFETs N4 and N4
5 and the CMOS latch circuit operate to operate the differential M
Output signal line VOUT amplified by OSFETs N4 and N5
An amplification operation is performed in which the potential difference between VOUT # and VOUT # is expanded to a CMOS level such as the power supply voltage VDD and the ground potential Vss by the operation of the CMOS latch circuit. Also in this embodiment, since the sense circuit can be driven even if the input voltages VIN and VIN # are not sufficiently large, a so-called direct sense operation excellent in high-speed operation as described above can be performed.

FIG. 21 is a circuit diagram of one embodiment of the output buffer. In the figure, 1 corresponding to 1 bit
Output circuits are illustratively shown as representatives. That is, in an SDRAM or the like which outputs data in units of 16 bits as shown in FIG. 1, the circuit shown in FIG. Then, a clock signal DO for controlling the operation is provided.
CLK (int.CLK) is commonly supplied to the 16 output buffers.

The output buffer is an N-channel output M
OSFETs Q34 and Q35 and such output MOSFETs
In operation, Q34 and Q35 are complementarily turned on / off in response to data DATA, and in non-operational state, both output MOSFETs Q34 and Q35 are turned off to output high impedance, so that NAND gate circuits G20 and G21 are used. And a drive circuit including an inverter circuit N20. In addition, the power supply voltage VDD
In order to raise the gate voltage of the output MOSFET Q34 on the side to be higher than the power supply voltage VDD and obtain a high-level output signal up to the power supply voltage VDD,
A booster circuit including Q31 to Q33, an inverter circuit N21 and a capacitor C is provided.

When the clock signal DOCLK is at a low level and is in a non-operating state, the output of the NAND gate circuit G20 goes to a high level regardless of the data DATA, turning on the N-channel MOSFET Q33 to turn on the output MO.
The output MOSFET Q34 is turned off by setting the gate voltage of the SFET Q34 to the ground potential. At this time, the output of the inverter circuit N21 becomes low level,
The capacitor C has a diode type MOSFET Q31.
Has been pre-charged through. Clock signal D
OCLK changes to the high-level operation state, and the data DA
If TA is at the high level, the output of the NAND gate circuit G20 goes to the low level, and the output signal of the inverter circuit N21 changes from the low level to the high level.

In the capacitor C, a boosted voltage is generated by adding the output high level of the inverter circuit N21 to the precharge voltage. The low level of the output signal of the NAND gate circuit G20 causes N
Since the channel type MOSFET Q33 is turned off and the P-channel type MOSFET Q32 is turned on, the boosted voltage of the capacitor C is increased by the M
The voltage is transmitted to the gate of the output MOSFET Q34 through the OSFET Q32, and the voltage is increased to the power supply voltage VDD or higher. As a result, data DO output from the output terminal is output.
At a high level like the high level power supply voltage VDD. When the data DATA to be output is at a low level, the input signals of the NAND gate circuit G21 are both at a high level to form a low-level output signal. The output signal of the inverter circuit N22 receiving this output signal goes high, turning on the output MOSFET Q35 to output a low level such as the ground potential of the circuit.

In such an output buffer, the data DATA to be output is held in the main amplifier (sense circuit) MA as described above or in the latch / register to which the amplified signal has been transmitted. The operation starts in synchronization with the rise of the clock signal DOCLK formed by the generation circuit, and the access time tAC is made equal to the operation delay time of the output buffer by synchronizing the DOCLK with the external clock signal ext.CLK. Can be shortened.

The operation and effect obtained from the above embodiment are as follows. That is, (1) a first operation current is supplied to the common source side of the differential MOSFET that receives the input signal and the operation current is supplied to the differential MOSFET.
A CM having a drain output of the differential MOSFET and an input and an output cross-connected to each other.
An OS latch circuit, and a second MOSF which receives an operation timing signal and supplies an operation current to the CMOS latch circuit.
An ET is provided to output an output signal from at least one of a pair of drain outputs of the differential MOSFET and a pair of cross-connected inputs and outputs of a CMOS latch circuit, according to the performance required for the sense circuit. The effect is obtained that a malfunction due to the output-side potential being undesirably fed back to the input side can be prevented while speeding up operation, facilitating timing design, or reducing power consumption.

(2) First and second switch MOSFETs for outputting the output signal as a complementary signal from a pair of output signal lines and supplying a power supply voltage between the power supply voltage and the pair of output signal lines; By providing an equalizing circuit comprising a third switch MOSFET for short-circuiting the pair of output signal lines, the amplifier circuit is automatically switched between a cross-coupled sensing operation and a latched sensing operation according to the output voltage. As a result, the above-described two amplifier circuits can be stably operated.

(3) The same operation timing signal is supplied to the gates of the first MOSFET and the second MOSFET. The effect is that the speeding up can be achieved.

(4) The same operation timing signal is supplied to the gates of the first MOSFET and the second MOSFET, and the operation timing signal is generated in accordance with the operation end timing of the equalizing circuit. The advantage is that it is possible to achieve both high speed and low power consumption while facilitating the timing design.

(5) The same operation timing signal is supplied to the gates of the first MOSFET and the second MOSFET, and the operation timing signal is generated later than the operation end timing of the precharge circuit. Thus, an effect that power consumption can be reduced can be obtained.

(6) On the basis of supplying different first and second operation timing signals to the gates of the first MOSFET and the second MOSFET, respectively,
A first operation timing signal supplied to the gate of the FET is generated prior to the operation end timing of the equalizer circuit, and a second operation timing signal supplied to the gate of the second MOSFET is generated by the equalizer circuit. By generating it at the same time as or later than the operation end timing, it is possible to achieve the effect of achieving higher speed and lower power consumption.

(7) Different first and second operation timing signals are supplied to the gates of the first MOSFET and the second MOSFET, respectively.
A first operation timing signal supplied to the gate of the SFET is generated at the same time as or later than the operation end timing of the equalizing circuit, and a second operation timing signal supplied to the gate of the second MOSFET is generated. First
By generating the operation timing signal later than the operation timing signal, it is possible to obtain an effect that power consumption can be further reduced.

(8) The differential MOSFET and the first and second MOSFETs are of the first conductivity type, and the first, second, and third switch MOSFETs are of the second conductivity type.
A first timing signal generated in advance to the gates of the first MOSFET and the third switch MOSFET;
By supplying the SFET and the gates of the first and second switch MOSFETs with the second timing signal generated with a certain time delay with respect to the first timing signal, the timing control signal can be reduced and the speed can be reduced. The advantage is that the power consumption and the power consumption can be reduced.

(9) Fourth and fifth switch MOSFETs of the second conductivity type for supplying power supply voltage to the pair of output signal lines are further provided, and the first and second switch MOSFETs are provided.
Of the fourth and fifth switch MOSFs
By supplying power to the gate of the ET, the operating point of the differential MOSFET and the precharge characteristic of the output signal line can be independently and optimally set while achieving high speed and low power consumption. Can be

(10) The output signal is a complementary signal output from a pair of output signal lines, and first and second, and fourth and fifth pre-charges for supplying a power supply voltage to the pair of output signal lines. And an equalizing circuit including a third switch MOSFET for short-circuiting the pair of output signal lines, and a third switch MOSFET and a gate of the third switch MOSFET. The fourth timing signal is supplied to the gates of the fourth and fifth switch MOSFETs, and the first, second and third timing signals are supplied in the first operation stage by the third timing signal. Switch MOSF
The ET is turned off, and in the second operation stage, the first MOSFET causes an operation current to flow according to the first operation timing signal. In the third operation stage, the fourth and fifth timing signals are used according to the fourth timing signal. Switch MOSFET
Is turned off, and in the fourth operation stage, the second MOSFET is controlled by the second operation timing signal so that the second MOSFET conducts an operation current. The effect is obtained that the precharge characteristics of the point and the output signal line can be optimally set independently of each other.

(11) An internal circuit which operates with an internal step-down voltage obtained by stepping down a power supply voltage supplied from an external terminal and outputs a minute voltage signal corresponding to the internal step-down voltage, and a power supply voltage supplied from an external terminal A sense circuit that operates and amplifies the minute voltage signal formed by the internal circuit to a signal amplitude corresponding to the power supply voltage; and an output circuit that receives an amplified signal of the sense circuit and sends an output signal from an external terminal. In the semiconductor integrated circuit device provided with the first circuit, the first sense circuit receives an operation timing signal and supplies an operation current to a common source of a differential MOSFET receiving an input signal.
A CM having a drain output of the differential MOSFET and an input and an output cross-connected to each other.
An OS latch circuit, and a second MOSF which receives an operation timing signal and supplies an operation current to the CMOS latch circuit.
A semiconductor integrated circuit device required by providing an ET and outputting an output signal from at least one of a pair of drain outputs of the differential MOSFET and a pair of cross-connected inputs and outputs of a CMOS latch circuit; It is possible to prevent malfunction due to undesired feedback of the output side potential to the input side while increasing the speed of the sense circuit, facilitating the timing design, or reducing the power consumption according to the performance of the sense circuit. The effect is obtained.

The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the output signal of the sense circuit is the differential MOSFET N4 or N4.
5 (one input / output node of the corresponding CMOS latch circuit) to obtain an output signal. The equalizing circuit can be omitted. However, CM
If the output signal of the previous operation remains in both inputs of the OS latch circuit, competition with the output signal of the differential MOSFET occurs.
Short-circuit MOSFE for short-circuiting the input / output node of the latch circuit
T is required.

In the sense circuit, the conductivity types of the MOSFETs may be all reversed. That is, the differential M
The OSFET is composed of a P-channel MOSFET, and the differential MOSFET and the MOSFET for supplying an operating current to the CMOS latch circuit are P-channel MOSFETs.
T may be used. In the sense circuit according to the present invention, in addition to the main amplifier as described above, one semiconductor integrated circuit device is provided with a plurality of functional blocks like a microcomputer, and the dynamic circuit of the embodiment is used for signal transmission for each functional block. It can also be used as an input circuit for receiving a small amplitude signal when a small amplitude signal is transmitted like a type RAM. SD
In the RAM, the synchronous clock generation circuit may be omitted, and the clock signal transmitted to the output buffer and the internal circuit may be such that the clock signal CLK supplied from the external terminal is transmitted through the clock buffer circuit. The present invention can be widely used as a sense circuit and a semiconductor integrated circuit device on which the sense circuit is mounted.

[0133]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the differential MO receiving the input signal
A first MOSFET for receiving an operation timing signal and flowing an operation current is provided on the common source side of the SFET.
A CMOS latch circuit is provided which receives the drain output of the OSFET and has an input and an output cross-connected to each other.
A second MOSFET for receiving an operation timing signal and supplying an operation current to the S latch circuit;
By outputting an output signal from at least one of a pair of drain outputs and a pair of cross-connected inputs and outputs of a CMOS latch circuit, high-speed operation and easy timing design can be made according to the performance required for the sense circuit. It is possible to prevent malfunction due to undesired feedback of the output side potential to the input side while reducing power consumption.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

FIG. 2 is a synchronous DRAM to which the present invention is applied;
FIG. 2 is a schematic layout diagram showing one embodiment of a (dynamic RAM).

FIG. 3 is a schematic layout diagram showing one embodiment of the sub-array of FIG. 2 and its peripheral circuits.

FIG. 4 is a schematic layout diagram showing one embodiment of a well region forming a sub-array and its peripheral circuits in FIG. 2;

FIG. 5 is a main part circuit diagram showing an embodiment of a sense amplifier section and peripheral circuits of the synchronous DRAM according to the present invention.

6 is a main part block diagram for explaining a relationship between a main word line and a sub word line of the sub array of FIG. 5;

7 is a main block diagram for explaining a relationship between a main word line and a sense amplifier of the memory array of FIG. 5;

FIG. 8 is a sectional view of an element structure for explaining a dynamic RAM (synchronous DRAM) according to the present invention.

FIG. 9 is a circuit diagram showing an embodiment of the main amplifier (sense circuit) MA used in the SDRAM according to the present invention.

FIG. 10 is a timing chart for explaining an example of the operation of the main amplifier (sense circuit) MA of FIG. 9;

11 is a timing chart for explaining another example of the operation of the main amplifier (sense circuit) MA of FIG. 9;

12 is a timing chart for explaining still another example of the operation of the main amplifier (sense circuit) MA of FIG. 9;

FIG. 13 is a circuit diagram showing another embodiment of the main amplifier (sense circuit) MA used in the SDRAM according to the present invention.

FIG. 14 is a timing chart for explaining an example of the operation of the main amplifier (sense circuit) MA in FIG. 13;

FIG. 15 is a timing chart for explaining another example of the operation of the main amplifier (sense circuit) MA of FIG. 13;

FIG. 16 is a circuit diagram showing still another embodiment of the main amplifier (sense circuit) MA used in an SDRAM or the like according to the present invention.

FIG. 17 is a circuit diagram showing still another embodiment of the main amplifier (sense circuit) MA used in an SDRAM or the like according to the present invention.

FIG. 18 is a timing chart for explaining the operation of the main amplifier (sense circuit) shown in FIGS. 16 and 17;

FIG. 19 is a circuit diagram showing still another embodiment of the main amplifier (sense circuit) MA used in an SDRAM or the like according to the present invention.

FIG. 20 is a timing chart for explaining the operation of the main amplifier (sense circuit) in FIG. 19;

FIG. 21 is a circuit diagram showing one embodiment of an output buffer used in the present invention.

FIG. 22 is a circuit diagram showing an example of a sense circuit studied prior to the present invention.

FIG. 23 is a circuit diagram showing another example of a sense circuit studied prior to the present invention.

[Explanation of symbols]

10: mode register, 20: command decoder, 30
... timing generation circuit, 30 ... clock buffer, 50
... Synchronous clock generation circuit, 200A, 200B ... Memory array, 201A, 201B ... Row decoder, 202
A, 202B: sense amplifier and column selection circuit, 20
3A, 203B: column decoder, 205: column address buffer, 206: row address buffer, 207
... column address counter, 208 ... refresh counter, 209 ... controller, 210 ... input buffer,
211: output buffer, 212A, B: main amplifier,
213: latch / register, 214A, B: write buffer. N1 to N6 N-channel MOSFETs, P1 to P7
... P-channel MOSFET, Q1-Q35 ... MOS
FET, C: capacitor, G20 to G21: gate circuit, N20 to N22: inverter circuit. CSP, CSN: common source line, YS: column selection signal, LIO: local common input / output line, MIO: main common input / output line, M1 to M3: metal layer, SN: storage node, PL: plate electrode, BL: bit Line, SD ...
Source, drain, FG: First polysilicon layer.

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/10 681G (72) Inventor Hiromasa Noda 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Semiconductor Company Hitachi, Ltd. In headquarters

Claims (17)

[Claims] A differential MOSFET for receiving an input signal; a first MOSFET provided on a common source side of the differential MOSFET;
A first MOSFET that receives an operation timing signal and flows an operation current to the differential MOSFET; a CMOS latch circuit that receives a drain output of the differential MOSFET and has an input and an output cross-connected; A second MOSFET receiving an operation timing signal and supplying an operation current to the CMOS latch circuit; and a pair of drain outputs of the differential MOSFET and a CMO.
A sense circuit for outputting an output signal from at least one of a pair of inputs and outputs cross-connected to an S latch circuit. 2. The output signal is a complementary signal output from a pair of output signal lines. The pair of output signal lines has a pre-supply voltage for supplying a power supply voltage to the pair of output signal lines. 2. The sense circuit according to claim 1, further comprising an equalizing circuit including a first and a second switch MOSFET for charging and a third switch MOSFET for short-circuiting the pair of output signal lines. 3. The first and second operation timing signals are the same timing signal and the first MOSF
3. The ET and the gate of the second MOSFET, wherein the ET is generated so as to form the operating current prior to the operation end timing of the equalizing circuit. Sense circuit. 4. The first and second operation timing signals are the same timing signal, and the first MOSF
3. The power supply circuit according to claim 2, which is supplied to the gates of ET and a second MOSFET, and is generated so as to form the operating current in accordance with the operation end timing of the equalizing circuit. Sense circuit. 5. The first and second operation timing signals are the same timing signal and the first MOSF
3. The sensing circuit according to claim 2, wherein the sensing circuit is supplied to the gates of the ET and the second MOSFET, and is generated so as to flow the operating current later than the operation end timing of the equalizing circuit. 6. The first operation timing signal supplied to the gate of the first MOSFET is supplied to the differential MOSFE prior to the operation end timing of the equalizing circuit.
The second operation timing signal generated so as to flow an operation current of T and supplied to the gate of the second MOSFET is the same as or later than the operation end timing of the equalizer circuit.
3. The sense circuit according to claim 2, wherein the sense circuit is generated so as to flow an operating current of the latch circuit. 7. A first operation timing signal supplied to the gate of the first MOSFET is delayed by the operation end timing of the equalizing circuit and the differential MOSF is delayed.
The second operation timing signal generated so as to flow the operation current of the ET and supplied to the gate of the second MOSFET is the same as or delayed from the first operation timing signal. 3. A sense circuit according to claim 2, wherein said sense circuit is generated so that an operation current flows through said sense circuit. 8. The differential MOSFET and the first and second MOSFETs are composed of a first conductivity type MOSFET, and the first, second and third switch MOSFETs are of a second conductivity type. A first MOSFET and a third switch MOSF
The first timing signal generated earlier is commonly supplied to the gate of the ET, and the first timing signal is supplied to the gates of the second MOSFET and the first and second switch MOSFETs. 3. A sense circuit according to claim 2, wherein a second timing signal generated with a delay of a predetermined time is supplied. 9. A precharge fourth and fifth switch MOSFE of the second conductivity type for supplying a power supply voltage to the pair of output signal lines.
9. The sense circuit according to claim 8, further comprising T, wherein the first timing signal is also supplied to gates of the fourth and fifth switch MOSFETs. 10. The output signal is a complementary signal output from a pair of output signal lines. The pair of output signal lines includes a pre-supply that supplies a power supply voltage to the pair of output signal lines. An equalizing circuit comprising first and second and fourth and fifth switch MOSFETs for charging and a third switch MOSFET for short-circuiting the pair of output signal lines; and the first and second switches are provided. A third timing signal is supplied to the gates of the MOSFET and the third switch MOSFET. The gates of the fourth and fifth switch MOSFETs are
A fourth timing signal is supplied. In the first operation stage, the first, second, and third switch MOSFETs are turned off by the third timing signal. In the second operation stage, the first operation is performed. The first MOSFET is caused to flow an operation current by a timing signal. In the third operation stage, the fourth and fifth switch MOSFETs are turned off by the fourth timing signal. In the fourth operation stage, 3. The sense circuit according to claim 2, wherein said second MOSFET is controlled by said second operation timing signal so that an operation current flows. 11. An internal circuit that operates with an internal step-down voltage obtained by stepping down a power supply voltage supplied from an external terminal and outputs a minute voltage signal corresponding to the internal step-down voltage, and operates with a power supply voltage supplied from an external terminal A sense circuit that amplifies the minute voltage signal formed by the internal circuit to a signal amplitude corresponding to the power supply voltage; and an output circuit that receives the amplified signal of the sense circuit and sends an output signal from an external terminal. A semiconductor integrated circuit device, wherein the sense circuit is provided on a common source side of the differential MOSFET for receiving an input signal;
A first MOSFET that receives an operation timing signal and flows an operation current to the differential MOSFET; a CMOS latch circuit that receives a drain output of the differential MOSFET and has an input and an output cross-connected; A second MOSFET that receives an operation timing signal and supplies an operation current to the CMOS latch circuit; a pair of drain outputs of the differential MOSFET and a CMO
A complementary output signal line connected to a pair of cross-connected inputs and outputs of the S latch circuit; a first and a second switch MOSFET provided between the pair of complementary output signal lines and the power supply voltage; A third switch MOSFET for short-circuiting the pair of output signal lines
A semiconductor integrated circuit device comprising: an equalizing circuit comprising: 12. The first and second operation timing signals are the same timing signal and the first MOSF
12. The control circuit according to claim 11, wherein said ET is supplied to a gate of said second MOSFET and said ET is generated so as to form said operating current prior to an operation end timing of said equalizing circuit. Semiconductor integrated circuit device. 13. The first and second operation timing signals are set to the same timing signal and the first MOSF
12. The ET and the gate of the second MOSFET, wherein the ET is generated so as to form the operating current in accordance with the operation end timing of the equalizing circuit. Semiconductor integrated circuit device. 14. A first operation timing signal supplied to a gate of the first MOSFET is supplied to the differential MOSF prior to an operation end timing of the equalizing circuit.
The second operation timing signal generated so as to flow the operation current of the ET and supplied to the gate of the second MOSFET is the same as or later than the operation end timing of the equalizer circuit.
12. The semiconductor integrated circuit device according to claim 11, wherein the semiconductor integrated circuit device is generated so as to flow an operating current of the latch circuit. 15. The differential MOSFET and first and second differential MOSFETs.
The first, second, and third switch MOSFETs are composed of a second conductivity type MOSFET. The first and third MOSFETs are composed of a second conductivity type MOSFET. Switch MOSF
The first timing signal generated earlier is commonly supplied to the gate of the ET, and the first timing signal is supplied to the gates of the second MOSFET and the first and second switch MOSFETs. 12. The semiconductor integrated circuit device according to claim 11, wherein a second timing signal generated after a predetermined time is supplied to the second integrated circuit. 16. A precharge fourth and fifth switch MOSF of the second conductivity type for supplying a power supply voltage to the pair of output signal lines.
16. The semiconductor integrated circuit device according to claim 15, further comprising an ET, wherein the first timing signal is also supplied to gates of the fourth and fifth switch MOSFETs. 17. The semiconductor device according to claim 11, wherein said internal circuit comprises a dynamic memory cell arranged in a matrix at an intersection of a plurality of word lines and a plurality of bit lines, and an address selection circuit therefor. Integrated circuit device.