JPH11213573A - Recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means in which an error correcting circuit is effectively functioned with a simple method by keeping correctly a storing order of data even if detection of synchronous patterns such as Sync, RS (resync) and the like are missed in a recording and reproducing device. SOLUTION: A format converting means 5 converting decoding data 11 to byte data 12 has a dummy data inserting function, and sends out dummy data by a pseudo pulse generated by a window for detecting a synchronous pattern when detecting a synchronous pattern is missed. Thereby, it can be prevented that one sector is made all useless by failure of detecting synchronous patterns such as Sync, RS, and the like. Further. even if inserted dummy data is not correct data, when its magnitude is in a range of correcting capability of a correcting means, it can be restored to correct data. This means improving reliability of a recording and reproducing device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic disk drive, an optical disk drive, a magneto-optical disk drive and the like, which encodes recording data into a recording code suitable for a recording medium, records the recording data as a serial signal on the medium, and The present invention relates to a recording / reproducing apparatus for decoding and reproducing a serial signal recorded on a device.

[0002]

2. Description of the Related Art In a recording / reproducing device such as a magnetic disk device, a magneto-optical disk device, and an optical disk device, an input data bit string is not recorded as it is, but is converted into another symbol in accordance with an encoding rule and then recorded.

In order to retrieve recorded data, it is necessary to know where the data is recorded on the medium, and when recording the data, it is necessary to know the area that can be used. It is common to take.

As an example of a 3.5 inch magneto-optical disk drive, this data format is disclosed in
This is shown in FIG. This will be described with reference to FIG.
a, a first sector mark (SM), first and second VFOs (91b, 91e) for locking the PLL circuit, and first and second address marks (91c, 91f) indicating that subsequent data is an ID track number And first and second ID sections (91d, 91g) in which sector numbers are recorded. These data are pre-written on the medium and are read-only.

On the other hand, the data portion is readable and writable,
SYNC section (92c) indicating the beginning of third VFO (92h) data for re-synchronizing the PLL, a plurality of user data sections (92a), and CRC section (9) which is an error check code
2b), an ECC unit (92c) that is an error correction code, and a RESY that is a resynchronization pattern provided between each data block.
It comprises an NC section (92e), a postamble section (92f), and a buffer section (92g).

[0006] Reading of a predetermined sector is performed as follows. First, information recorded on a medium is detected as serial data by recording signal detecting means such as a magnetic head or an optical head. Sector mark (hereinafter S
M) is used to indicate the start of a sector, and therefore, it is general that no pattern detection period is provided.
An address mark (hereinafter referred to as AM) is detected by providing a detection period by a counter based on the detection timing of the SM, and by performing the AM detection operation only during this period, erroneous pattern detection is prevented. I have to. This detection window is used not only for detection of AM but also for detection of a sync mark (hereinafter referred to as Sync).

Since the start position of the address data in the serial data to be read next can be accurately known by detecting the AM, the address information written on the medium can be correctly reproduced. If the reproduced address information is a desired address, the circuit starts reading the data area next, but the start position of the data on the serial data can be known by detecting Sync.

However, in the case of a magneto-optical disk in particular, the error rate of read data is several orders of magnitude lower than that of a magnetic disk, and there are many read errors. Therefore, there is a high risk that the clock extraction from the data will fail and the synchronization relationship between the data and the read clock will be lost. Therefore, RESYN is included in the data.
A section C (hereinafter referred to as RS) is provided to resynchronize.

[0009] Also, high capability is required for error correction. For this purpose, a Reed-Solomon code is generally used, and the error correction capability is improved in a format called LDC (long distance code). This is a code format in which the Hamming distance is lengthened one-dimensionally and interleaved to prevent burst errors. For this correction method, refer to Triceps's “Signal Processing Technology in Optical Recording” P163 to P175.

Incidentally, the presence of the RS means that even if the detection of Sync fails, there is a possibility that data can be correctly reproduced. That is, if any of the subsequent RSs can be detected, the start position of the correct data can be known there, that is, 'byte synchronization' can be achieved, so that if the number of errors is within the range of the error correction capability, correct The data can be reproduced.

[0011]

However, according to the algorithm of the error correction means described above, the read data is
The data must be stored in the correct order in each interleave. If this condition is not satisfied, errors cannot be corrected, and even correctly read data is wasted.

Further, the decoding circuit is connected to a buffer memory and an error correction circuit for connecting to the interface circuit, and the data needs to be in byte units. However, since the output of the decoding circuit is generally output in units of bits or blocks of several bits, means for converting these data into a format in units of bytes and connecting to the above-described circuit is required.

Therefore, the structure of the error correction means is adapted to
Even if the detection of the sync or the RS fails, a rational mechanism is required that has both the function of storing data at the correct interleave position in the correct order and the function of transferring data in byte data units. However, there has been no disclosure of a specific configuration method or the like regarding the structure of a reproducing apparatus that satisfies this requirement.

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to store read data in a correct interleave position and a correct buffer memory address even when Sync and RS detection fails. Accordingly, an object of the present invention is to provide means for enabling error correction and improving the data reproduction capability of a recording / reproducing apparatus with a simple circuit configuration.

[0015]

According to a first aspect of the present invention, there is provided a recording / reproducing apparatus comprising dummy data inserting means between a decoding means and an error correcting means or a buffer memory.

According to the above configuration, Sync or RS
, The byte synchronization can be established at the provisional timing and the provisional data can be sent to the circuits that need them. Therefore, if the detection of the next synchronization pattern succeeds and the byte synchronization is correctly achieved after the failure of the synchronization pattern detection, the read data is stored in the correct interleave position in the correct order and at the correct buffer memory address, and error correction is performed. Has an effect of effectively functioning.

According to the second aspect of the present invention, the dummy data insertion means is realized as a part of the format conversion means between the decoding means and the error correction means or the interface circuit, and no additional circuit is required. It is characterized by.

According to the above configuration, during reading of temporary data due to detection failure of the synchronization pattern, a special circuit for data processing is not required, and a desired object can be achieved while maintaining consistency with the format conversion means. Therefore, there is an effect that simplification of the circuit and reliability of the operation can be expected.

According to a third aspect of the present invention, there is provided a recording / reproducing apparatus in which the format means comprises an output buffer for shaping the decoded data into a one-byte size, and a pointer for managing the amount of data stored in the buffer. The insertion of dummy data is realized by controlling the value of this pointer.

According to the above configuration, when inserting dummy data, the function of cutting out the data originally provided in the circuit in units of bytes is used, so that the desired function can be easily realized.

In the recording / reproducing apparatus according to the present invention, in the format conversion means, insertion of dummy data is performed by a pointer for managing a buffer, and control of the pointer is performed by a pulse generated from a trailing edge of Sync_window, RS_window. It is characterized by.

According to the above configuration, even when Sync or RS cannot be detected, the head position of temporary data can be determined from the pattern detection window.
This has the effect that the temporary data of one data block length is read out until the next synchronization pattern is detected, and the correct number of data transfers to the error correction circuit and the buffer memory can be realized.

Further, there is an effect that it is not necessary to particularly add a circuit to realize this function, and the circuit configuration can be simplified.

According to a fifth aspect of the present invention, there is provided a recording / reproducing apparatus in which the format conversion means has a function of separating the user data and the synchronization pattern in the data area. It is realized by an output of a counter that counts the generated pulses and decoded data in byte units.

According to the above configuration, the RS detection signal is ignored until a certain number of data blocks have been counted.
This has an effect that a filter function for erroneous detection of an RS pattern is realized.

Further, since control is performed by the value of the byte counter, it is not necessary to consider how much the RS area needs to be read in order to decode the last data, so that the circuit configuration and operation are simplified and reliability is improved. It has the effect of.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 to 7 and Tables 1 and 2 show the main parts of a first embodiment of the recording / reproducing apparatus according to the first to fifth aspects of the present invention. First, an overall data flow will be described with reference to FIG. Serial data obtained from an optical head or the like (not shown) is decoded by the decoding means 6. Since the decoding method itself is not directly related to the present invention, it will not be described here. For example, the decoding method can be realized by a method disclosed in Japanese Patent Publication No. 55-26494 or Japanese Patent Application Laid-Open No. 58-13020. The decoded data 11 decoded by the decoding means 6 is cut out as byte data 12 by the format conversion means 5 and
It is sent to the error correction means 3 and the ID determination means 4. At this time, the ID data and the user data are separated by using the transfer request b of 9 when outputting the ID data and the transfer request a of 10 when outputting the user data.

The error correction means 3 calculates the position and magnitude of the error based on the byte data 12 and writes the data 8 for correction to the buffer memory 2 to write the correction data 8 into the buffer memory 2.
Correct the data in. The corrected data 7 is sent to the host computer (not shown) through the interface circuit 1.
And so on.

There are three things to consider here.

1. The input to the decoding means 6 is generally serial data, but the output is obtained in serial or several bit units depending on the decoding means 6.

For example, when serial data subjected to 2-7 modulation is taken as input data to the decoding means 6, according to this code conversion rule (not shown), '0-0-0-0.
-1-0-0-0-0-0-0-0-0-1-0-0 '
Serial input data such as '0011', '001'
0 ', but this output is' 0-0-1-1-1-
That is, it can be obtained as serial data of 0-0-1-0 'one bit at a time, or it can be obtained in blocks of several bits, such as'0011-0010'. On the other hand, the error correction means 3 or the buffer memory 2 which receives the data is composed of the decoding means 6 for processing the data in byte units and the buffer memory 2 or the error correction means 3.
The format conversion means 5 exists between the two and must function to cut out data in byte units.

2. As described above, one sector includes a portion in which a sector address or the like is written in advance and a user data portion. The read ID data is determined by the ID determination unit 4 as to whether or not it is a target sector. Since the byte data 12 output from the format conversion means 5 includes both ID data and user data, it is necessary to discriminate these. Furthermore, there are synchronization patterns such as Sync and RS in the user data part. In particular, since the head part of the RS is necessary for decoding the last valid data of the user data, a part of the data of the RS part is also decoded. 6 must be entered. Therefore, it is necessary to separate the synchronization pattern from the user data and take specific means for extracting only the user data portion.

3. The error correction means 3 orders the byte data 12 and performs an operation necessary for an error correction process between data belonging to the same interleave. Therefore, once Syn
The circuit configuration must be such that the interleave position of each data does not shift due to the detection failure of c or RS, and the order of the data is not out of order within the same interleave.

How these three points are solved by the present invention will be described in order.

FIGS. 2 to 4 show the format conversion means 5 described above.
And Table 1 is a table for explaining the detailed operation.

[0037]

[Table 1]

In this example, it is assumed that the decoded data 11 obtained from the decoding means 6 is obtained in units of several blocks, and that the modulation method is 2-7 modulation. Therefore, the decrypted data 1
1 is one of 2, 3, and 4 bits.

In FIG. 2, the 8-bit buffer a14 is empty, and the 8-bit buffer b15 stores 6-bit decoded data, and the decoded data sent from the encoding means (not shown). The coded data 24 (4 bits long) is about to be written to the buffer b15.

FIG. 3 shows the state of each buffer immediately after writing. This figure shows how the lower two bits of the decoded data 24 are stored in the upper two bits of the buffer b15, and the surplus data 25 is generated. At this stage, 1-byte data is stored in the buffer b15 in the correct order for each bit.

FIG. 4 shows a state in which the byte data in the buffer b15 is transferred to the buffer a14, and the remaining data 25 is stored in the lower part of the buffer b15. The buffer a14 generates a transfer request signal 19 when 1-byte data is written, and transfers the data to the buffer memory (not shown) or the error correction means (not shown) via the output destination selecting means 13.

Table 1 shows that the buffers a14 and b1
5 is a table for explaining the operation of FIG. 5 in detail. Here, the description will be given on the assumption that the modulation method is 2-7 modulation. Table 1
In, the 'pointer value' indicates the current amount of data held in the buffer b15. 'Length of data to be written' is determined by decoding means from buffer b15.
Represents the length of the data to be written to. In Table 1, 'contents of buffer b' and 'contents of buffer a' indicate the content of each buffer immediately after this data is written.

More specifically, referring to FIG. 2, the value of the pointer is 6 at this time. The length of the data to be written is four. Therefore, referring to the row of "pointer value 6" written data length 4 "in Table 1," contents of buffer b "is" [000000, d3: d2] ", and" contents of buffer a "is" [d1: d0, b5: b0] ′. This is stored in the buffer b15 just before writing.
[00, b5: b0] is held and [d
By writing the 4-bit data "3: d0", 1-byte data [d1: d0, b5: b0] is formed and written to the buffer a14, and the buffer b
The remaining 2 bits of data [d3: d2]
[000000, d3: d2]. Thereafter, by repeating the same operation, data input in units of several blocks is shaped in units of 1 byte.

The "sync pattern detection signal" is Syn.
The detection signals of the synchronization patterns such as c and RS, and the “pseudo synchronization pattern detection signal” are signals generated instead when these patterns cannot be detected. When the former becomes “1”, the 14 buffers a and 15 Buffer b is initialized and operates with the next data as the start of a new data block. The latter is "1" when the synchronization pattern cannot be detected at the position where it should be originally detected. At this time, the buffer a in 14 transmits dummy byte data. These operations will be described later together with the third problem.

Next, the second problem will be described with reference to FIGS. In FIG. 2, the output destination selecting means 13 is controlled by a selection signal 20, and its input is a transfer request 19 and its output is a transfer request a17 and a transfer request b18.
When the selection signal 20 is "1", the transfer request 19 is output to the transfer request a17, and when the selection signal 20 is "0", the transfer request 19 is output to the transfer request b18. Therefore, referring to FIG. 1, the selection signal 20 of FIG.
Is appropriately controlled, the destination of the byte data output from the 14 buffers a can be selected.

The selection signal 20 is the synchronization pattern detection signal 2
1. Generated by the selection signal generating means 16 using the pseudo sync pattern detection signal 22 and the byte counter output 23.

A byte counter (not shown) is a counter which counts up each time 10 transfer requests a in FIG. 1 are asserted. Therefore, this counter counts the number of bytes of the transferred user data.

The generation timing of these signals will be described with reference to FIG. FIG. 6A shows the structure of the user data section in one sector. Normally, a window for detecting AM and Sync is generated to prevent erroneous detection of each pattern. A window for this is generated by starting a counter by detecting SM and from the count value. The window generated in this way is Sync_win in FIG.
dow. In the present invention, the synchronization pattern detection signal 2
1 or the pseudo sync pattern detection signal 22 from FIG.
The RS_window of (c) is generated.

FIG. 6D shows the synchronous pattern detection signal 21,
FIG. 6E shows the pseudo synchronization pattern detection signal 22, FIG.
(F) shows the byte counter output 23, and FIG. 6 (g) shows the waveform of the selection signal 20.

As can be seen from this figure, when the synchronization pattern such as Sync and RS in FIG. 6A is correctly detected, the synchronization pattern detection signal 21 is asserted for one clock. If the synchronization pattern cannot be detected while the detection window is open, the pseudo synchronization pattern detection signal 22 is asserted. A byte counter (not shown) is initialized by the synchronization pattern detection signal 21 and the pseudo synchronization pattern detection signal 22, counts up user data one byte at a time, and when it reaches a certain value, the next synchronization pattern detection signal 21 or The count value is held until the pseudo synchronization pattern detection signal 22 is asserted. Here, the constant value is the number of bytes of the user data existing between the RS patterns, and in this example, is 20 bytes. Hereinafter, this part is referred to as a data block.

The selection signal 20 is the synchronization pattern detection signal 2
It is designed so that it becomes "1" when the pseudo sync pattern detection signal 22 is asserted or "0" when the counter output 23 reaches the number of bytes of the data block.
At this time, in order to prevent the user data from being erroneously read as a synchronization pattern due to a reading error or the like, the synchronization pattern detection signal 2 is kept until the byte counter has counted one data block.
1. The output of the pseudo sync pattern detection signal 22 is ignored. This state is shown in FIG.

Since the selection signal 20 is input to the output destination selection means 13 as described above, the RS data existing in the user data is separated, and only the user data is sent to the error correction means 3 and the buffer memory 2. Can be.

Although the first part of the RS is necessary for decoding the last data, since the selection signal is switched based on the byte count value in this way, the data part and the RS part need not be distinguished at all. Decoding without any inconsistency.

By the way, how the data of the ID portion is separated and what happens to the operation of the ID determining means 4 during the reading of the RS is that the ID information is preceded by an AM.
Has already been described, and the presence of ID information is detected by detecting this. When the window for detecting this AM is asserted, I
The D determination means 4 is designed to start up and stop when the ID data has been read.

On the other hand, if the byte counter has finished counting data for one sector and the selection signal 20 becomes "0", the transfer request 19 is output to the transfer request b side. After detection, a window for AM detection is opened. Therefore, when reading the ID portion, the byte data 11 output from the decoding means 6 is processed by the ID judging means 4.

In the user data area, even if the byte counter has counted one data block and the transfer request 19 is output to the transfer request b18, the ID window 4 does not operate because the AM window is not opened.

As described above, it is understood that the ID data and the user data, and the user data and the synchronization pattern can be separated without contradiction.

The last problem will be described with reference to FIGS. 5, 6, 7 and Table 2.

[0059]

[Table 2]

Table 2 shows the detailed structure of the user data portion, where SB1 to SB4 represent Sync, and D1, D2... Each represent one byte of user data. .. Represent RS (resync information) inserted between the user data. If the chunk of user data divided by the RS is called a data block as described above, one data block is 20 bytes in this example.
'FF' is arbitrary data, and in this case 16
Indicates that 'FF' is entered in base number. C1 to C4 are data for error detection, and E1, 1 to E5, and 16 are data for error correction. The method of generating these data is based on ISO / IEC
CD15041.

When data is recorded on the medium, the data is recorded in the order of SB1, SB2... D5, D6... D10... From the upper left of the table. At this time, E1,1, E1,2
... Data in vertical columns such as E1,15, E1,16 are D
1, D6... D511, generated from FF. Similarly E
2,1-E2,16, E3,1-E3,16, E4,1-E
4,16 and E5,1 to E5,16 are also D2 ... C1,
D3... C2, D4... C3, D5 to C4.
Then, for each vertical column, 0-4
The numbers up to are referred to as interleave 0 to interleave 4, respectively.

By the way, when reproducing such data, the data is read out in the same order as the order in which it was written. However, when performing error correction, it is necessary to process the data in units of interleaving in the process. is there.
This is shown in FIG. The block shown in FIG. 5 is inside the error correction means 3 in FIG. 1, and the read data is sequentially changed into a data group 28 belonging to interleave 0 to a data group 32 belonging to interleave 4 every time one byte is counted. These are stored and input to the syndrome calculating means 27 in interleave units.
These data are used to generate a syndrome 26 for calculating the magnitude and location of the error.

In consideration of the above structure, if the detection of the RS existing in the user data fails, the following problem occurs.

Referring to FIG. 5, it is assumed that, for example, after the detection of the RS is successfully performed and one data block including D1 to D20 is normally read, the detection of the next RS fails. At this time, the value of the byte counter remains at 20, so the selection signal 20 in FIG. 6G is in the next one data block period '0'. Therefore, the next user data D20
To D39 are not transferred to the error correction means 3 and the buffer memory 2. Thereafter, the RS was successfully detected and D40 to D59
Even if these data blocks are normally transferred, they are input to the positions where D20 to D39 are supposed to be. Further, even if all of the RSs are successfully detected thereafter, they are all input with a shift of one data block. This is the same as erroneous reading of data from the viewpoint of error correction, and all data blocks in which RS can be normally detected are wasted.

How this problem can be solved by the present invention is as follows.
Although it is generated from the timing at which M is detected, in the present invention, an RS_window following it is created by the method shown in FIG. 7 and the window is solved by this window.

FIG. 7 shows the main part of the RS_window generating circuit, and the operation is as follows.

In the read operation of 1.1 sector, Sy
When nc can be detected, the counter is started based on the detection timing, and an RS_window, which is an RS detection window appearing after one data block, is generated.

2. If Sync detection fails, Sync_w
The counter is started by the trailing edge of indow and the next RS_window is generated. If the next RS is successfully detected, The RS_window is generated from the detection timing in the same manner as described above.

3.2. If the detection of RS fails in RS
Start the counter by the trailing edge of _window and start the next RS_window
Generate

This circuit has three states S0, S1, and S2. Describing these state transitions, first, S0 is set to Syn while the Sync_window is open.
This is a state for determining whether or not c has been detected. If Sync can be detected during this period, the state becomes S
Transition to 2. If Sync is not detected during this period, the flow shifts to S1. S1 is a state in which it is determined whether or not an RS has been detected while the RS_window is open. If it can be detected, it transits to S2, and if it cannot be detected, it stays at S1. In any state, the state returns to the state of S0 by the signal 'End_sec' indicating the end of one sector.

The window generation counter (not shown) is S
In the state of 1, it is started by the trailing edge of Sync_window or RS_window, and when it reaches a certain value, it is initialized there and starts counting up. Since the length of one data block is fixed, the number to be counted before initialization is known. An RS_window is repeatedly generated by decoding the output of the window generation counter. In S2, a counter is started according to the detection timing of Sync or RS, and an RS_window is generated as in S1. The difference between the operations of the counters in S1 and S2 is that the start timing of the counter is accurate in S2, so that the window can be generated accurately, and the window generated in this way loses the RS once detected. In such a case, it is generated at the correct position.

The pseudo sync pattern detection signal 22 is a pulse signal generated from the trailing edge of the field window where the above sync pattern could not be detected. Referring to Table 1, when this signal is asserted, the buffer b15 is cleared and the value of the pointer is forced to 8. Therefore, byte data exists in the buffer b15. In this case, all data of 8 bits are transferred to the buffer a14, and subsequently, the contents of the buffer a14 are transferred to the error correction means 3 or the buffer memory 2. . That is, dummy data has been transmitted. Then 1
The same byte data generation operation as usual is performed on the data of the data block based on the read data.

FIG. 6 shows the operation when no RS is detected.
Referring to the portion indicated by the arrow in FIG. 6, since the RS could not be detected, FIG.
The pseudo-sync pattern detection signal 22 shown in FIG.
Therefore, as described above, the selection signal 20 changes from '0' to '1' as shown in FIG. 6 (g), and thereafter the read data is sent to the error correction means 3 or the buffer memory 2. Naturally, since the RS could not be detected, the head of the true data is not known, and the decoded data is also generally incorrect. However, if the next RS can be correctly detected by reading the dummy data in this way, the subsequent data can be correctly corrected without causing the above-described problem.
The data is sent to the buffer memory 2. Therefore, even if dummy data for one data block is inserted, they can be corrected correctly within the correction capability range of the error correction means.

The advantages of inserting dummy data in this way are as follows. Generally, the window for pattern detection is opened in a wider range than the area where the actual pattern is written in consideration of the rotation fluctuation of the spindle motor and the like. Therefore, if the synchronization pattern cannot be detected correctly, the decoding of the prescribed number of bytes may not be completed until the next synchronization pattern is reached by simply decoding the trailing edge of the window as the head of data. In this case, the detection of the next synchronization pattern also fails. With the structure as proposed in this proposal, counting of the value of the byte counter is completed at a timing earlier than that in the case where the synchronization pattern can be normally detected, and it is possible to prepare for the next synchronization pattern detection. This situation is understood by the output of the byte counter in FIG.

[0075]

As described above, according to the recording / reproducing apparatus of the present invention, it is possible to prevent the whole sector from being wasted due to the failure to detect the synchronization pattern such as Sync and RS.

Further, even if the inserted dummy data is not correct data, it can be restored to the correct data if its size is within the range of the correction capability of the error correction means.
This leads to an improvement in the reliability of the recording / reproducing device.

Further, since the present invention is incorporated in the byte data generating means itself which this kind of device originally needs to have, there is no contradiction with the functions of reading the ID portion and separating user data and synchronous data. Integrated without having to. Therefore, the circuit configuration and operation are simple, and it is easy to apply to general recording / reproducing apparatuses.

[Brief description of the drawings]

FIG. 1 is a diagram showing a data flow in the present invention.

FIG. 2 is a diagram showing a state immediately before data is written to a buffer b.

FIG. 3 is a diagram showing a state immediately after data is written to a buffer b.

FIG. 4 is a diagram illustrating a state immediately after byte data is transmitted.

FIG. 5 is a diagram illustrating data interleaving.

FIG. 6A is a diagram showing a structure of a user data section in one sector. (B) is a diagram showing the generation timing of Sync_window. (C) is a diagram showing the generation timing of Rsync_window. (D) is a diagram showing the generation timing of the synchronization pattern detection signal. (E) is a diagram showing the generation timing of the pseudo synchronization pattern detection signal. (F) is a diagram showing the operation of the byte counter. (G) is a diagram showing the timing of a selection signal.

FIG. 7 is a view for explaining a window generation method.

[Explanation of symbols]

 1. Interface circuit 2. 2. Buffer memory Error correction means 4. ID determination means 5. Format conversion means 6. Decoding means 7. 7. Data after correction Data for correction 9, 18 Transmission request signal b 10, 17. Transmission request signal a 11, 24. Decoded data 12. Byte data 13. Output destination selection means 14. Buffer a15. Buffer b16. Selection signal generating means 19. Send request 20. Selection signal 21. Synchronization pattern detection signal 22. Pseudo synchronization pattern detection signal 23. Byte counter output 25. Surplus data 26. Syndrome data 27. Syndrome calculation means 28. Data group belonging to interleave 0 29. Data group belonging to interleave 1 30. Data group belonging to interleave 2 31. Data group belonging to interleave 3 32. Data group belonging to interleave 4

Claims (5)

[Claims] A decoding means for decoding a recording code read from a recording medium into recording data; a format converting means for cutting out decoding data obtained from the decoding means in byte units; An error correcting means for performing error correction on the recording and reproducing apparatus having a buffer memory for performing data transfer with an interface circuit and reproducing the recorded data, wherein the decoding means, the error correcting means or the buffer A recording / reproducing apparatus comprising a dummy data inserting unit for one data block between the memory and the memory. 2. The recording / reproducing apparatus according to claim 1, wherein said dummy data inserting means is realized as a part of said format converting means, and does not require a new additional circuit. 3. The format conversion means has a buffer for shaping the decoded data into one-byte size, and a pointer for managing the amount of data stored in the buffer. 3. The recording / reproducing apparatus according to claim 2, wherein dummy data insertion is realized by controlling a value. 4. In the format conversion means, insertion of dummy data is performed by a pointer for managing the buffer, and control of the pointer is performed by Sync_windo.
4. The recording / reproducing apparatus according to claim 3, wherein the recording is performed by a pulse generated from a trailing edge of w, RS_window. 5. The format conversion means has a function of separating user data and a synchronization pattern in a data area, and this function includes a Sync detection signal or an RS detection signal or a pulse generated from a trailing edge of Sync_window or RS_window. 5. The recording / reproducing apparatus according to claim 4, wherein the recording / reproducing apparatus is realized by an output of a counter which counts decoded data in byte units.