JPH11204926A - Soldering method and manufacture of electronic device - Google Patents
Soldering method and manufacture of electronic deviceInfo
- Publication number
- JPH11204926A JPH11204926A JP10002395A JP239598A JPH11204926A JP H11204926 A JPH11204926 A JP H11204926A JP 10002395 A JP10002395 A JP 10002395A JP 239598 A JP239598 A JP 239598A JP H11204926 A JPH11204926 A JP H11204926A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- soldering method
- solder
- film removing
- solder material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning And De-Greasing Of Metallic Materials By Chemical Methods (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、リード部品や面実
装部品等を電子配線基板にフラックスを用いずに、高温
ではんだ付けすることのできるはんだ付け方法と、該方
法を用いた電子装置の製造方法とに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a soldering method capable of soldering a lead component, a surface mount component, or the like at a high temperature without using a flux on an electronic wiring board, and an electronic device using the method. A manufacturing method.
【０００２】なお、本明細書において「電子装置」と
は、例えば樹脂封止型半導体装置などのように、配線基
板上に半導体チップまたはトランジスタ素子などの電子
部品が搭載されたものをいい、配線基板の備える配線が
回路を形成しているか否かを問わない。[0002] In this specification, the term "electronic device" refers to a device in which an electronic component such as a semiconductor chip or a transistor element is mounted on a wiring board, such as a resin-sealed semiconductor device. It does not matter whether the wiring provided on the substrate forms a circuit.
【０００３】[0003]
【従来の技術】電子部品の接続においては、接続のため
の金属薄膜（すなわちメタライズ層）の形成が重要であ
るとされている。例えば、ＬＳＩ（大規模集積回路）の
メタライズ層は、一般に、スパッタまたは蒸着で形成さ
れる。このメタライズ層は薄すぎると良好な接続が得ら
れないが、厚すぎると膜応力の発生によりそれ自体が基
板から剥がれてしまい、また、形成にコストと時間がか
かってしまう。このため、メタライズ層の膜厚は、数μ
ｍ程度とすることが普通である。2. Description of the Related Art In connecting electronic components, it is considered important to form a metal thin film (that is, a metallized layer) for connection. For example, a metallized layer of an LSI (Large Scale Integrated Circuit) is generally formed by sputtering or vapor deposition. If the metallized layer is too thin, good connection cannot be obtained, but if it is too thick, the metallized layer itself peels off from the substrate due to the generation of film stress, and it takes a long time to form the metallized layer. Therefore, the thickness of the metallized layer is several μm.
It is usually about m.
【０００４】この薄膜形成されたメタライズ層を用いた
接続に用いられる高融点のはんだには、柔軟性、接続性
および融点の高さから、メタライズとＳｎが反応するこ
とにより結合を形成するＳｎ−Ｐｂ系はんだが挙げられ
る。[0004] The high melting point solder used for connection using the metallized layer formed with the thin film is formed of Sn- which forms a bond by reacting metallization and Sn due to flexibility, connectivity and high melting point. Pb-based solder is exemplified.
【０００５】良好な接続を形成するためには、メタライ
ズと反応するＳｎの含有量が０．１％以上であることが
望ましい。しかし、はんだ中のＳｎ含有量が多いと、は
んだの硬さが増し、融点が下がる。また、上述のように
メタライズ層は極めて薄いため、はんだ中にＳｎが多量
に含まれる場合、このＳｎとの反応にメタライズのほと
んどが消費されてしまい、その後の電子部品のリペア接
続が不可能になることがある。従って、Ｓｎ含有量は、
１０重量％以下とすることが望ましい。In order to form a good connection, the content of Sn which reacts with metallization is desirably 0.1% or more. However, when the Sn content in the solder is large, the hardness of the solder increases, and the melting point decreases. In addition, since the metallization layer is extremely thin as described above, when Sn is contained in a large amount in the solder, most of the metallization is consumed in the reaction with Sn, so that repair connection of the electronic component cannot be performed thereafter. May be. Therefore, the Sn content is
It is desirable that the content be 10% by weight or less.
【０００６】このようなＳｎ−Ｐｂ系はんだを用いては
んだ付けする場合、はんだ表面の酸化膜をフラックスに
より除去することが一般的である。電子部品を配線基板
上にフラックスを用いてはんだ付けする場合、はんだ付
けの後のフラックス残渣による腐食を防止するために、
ハロン（フロンまたは塩素系有機溶剤など）等による洗
浄を行わなければならない。しかし、ハロンは環境保全
の立場から使用しないことが望ましい。また、微細かつ
高密度なはんだ接続部では、信頼性を確保するための高
い清浄度が要求されるが、一旦付着した残渣を完全に除
去することは困難である。そこで、例えば、特開平７−
２３５７６３号公報および特開平８−２９３６６５号公
報では、フラックスを用いないで配線基板上に電子部品
をはんだ付けする技術として、清浄化処理したはんだ表
面を有機材料で覆う方法が提案されている。[0006] When soldering using such Sn-Pb-based solder, it is common to remove an oxide film on the solder surface by using a flux. When soldering electronic components on a wiring board using flux, to prevent corrosion due to flux residue after soldering,
Cleaning with halon (such as chlorofluorocarbon or a chlorinated organic solvent) must be performed. However, it is desirable not to use halon from the standpoint of environmental protection. Further, in a fine and high-density solder connection portion, high cleanliness is required to ensure reliability, but it is difficult to completely remove the residue once adhered. Therefore, for example, Japanese Patent Application Laid-Open
In Japanese Patent Application Laid-Open No. 235763 and Japanese Patent Application Laid-Open No. 8-293665, as a technique for soldering an electronic component on a wiring board without using a flux, a method of covering a cleaned solder surface with an organic material has been proposed.
【０００７】この方法では、有機材料によって電子部品
を配線基板の所定の位置に仮止めすることができるとと
もに、はんだの加熱溶融時に接続部表面が外気に曝され
るのを回避することができる。これらの公報記載のはん
だ付け技術における有機材料の役割は、次の３つに分類
できる。According to this method, the electronic component can be temporarily fixed at a predetermined position on the wiring board by the organic material, and the surface of the connection portion can be prevented from being exposed to the outside air when the solder is heated and melted. The role of organic materials in the soldering techniques described in these publications can be classified into the following three.
【０００８】（１）仮止め用接着剤としての役割 有機材料を用いる場合、その粘性により、はんだ付けの
前工程で電子部品を配線基板上の所定の位置に位置決め
して仮止めすることができる。このようにすれば、リフ
ロー接続までの搬送等における衝撃による位置ずれ、移
動、落下等を防ぐことができる。 （２）酸化防止被膜としての役割 はんだ溶融時に有機材料が接続部を被覆することにより
酸化が防止され、ぬれ性も確保される。 （３）酸化膜除去剤としての役割 有機材料によりはんだ表面の酸化膜が除去され、メタラ
イズに対するぬれ性が改善されるため、セルフアライメ
ント作用が有効に発揮される。(1) Role of adhesive for temporary fixing When an organic material is used, an electronic component can be positioned and temporarily fixed at a predetermined position on a wiring board in a process before soldering due to its viscosity. . With this configuration, it is possible to prevent a displacement, a movement, a drop, or the like due to an impact in the conveyance or the like up to the reflow connection. (2) Role as an antioxidant film When the solder is melted, the organic material covers the connection portion, thereby preventing oxidation and ensuring wettability. (3) Role as an oxide film remover An oxide film on a solder surface is removed by an organic material, and the wettability to metallization is improved, so that a self-alignment effect is effectively exhibited.
【０００９】上述の３つの役割のうち、（１）および
（２）の役割を果たす材料としては、炭化水素系、ケト
ン類、エステル系、アルデヒド系等の有機材料を使用す
ることができ、（３）の役割を満足する有機材料として
は、少なくとも１個以上の水酸基（−ＯＨ基）を有する
アルコール系材料を用いることが好ましい。[0009] Of the above three roles, organic materials such as hydrocarbons, ketones, esters, and aldehydes can be used as the materials fulfilling the roles (1) and (2). As the organic material satisfying the role of 3), it is preferable to use an alcohol-based material having at least one or more hydroxyl group (—OH group).
【００１０】[0010]
【発明が解決しようとする課題】しかし、この方法で
は、上述のＳｎ−Ｐｂはんだのように融点の高いはんだ
材を用いると、接続時の加熱温度が高いことから、はん
だ材が有機材料中に溶け出してしまう。従って、用いる
有機材料をごく微量にしない限り、はんだ付け後に残る
塩類等の残渣が多くなってしまう。このような残渣は、
得られた電子装置が稼働する際に、腐食や短絡（残渣マ
イグレーションも含む）を起こす原因になる場合があ
る。しかし、有機材料の量をごく微量にコントロールす
ることは困難であった。However, in this method, when a solder material having a high melting point, such as the above-mentioned Sn-Pb solder, is used, the heating temperature at the time of connection is high. Will melt away. Therefore, unless an organic material to be used is used in a very small amount, residues such as salts remaining after soldering will increase. Such residues are
When the obtained electronic device operates, it may cause corrosion or short circuit (including residue migration). However, it has been difficult to control the amount of the organic material to a very small amount.
【００１１】そこで本発明は、Ｓｎ含有量の多いはんだ
材を用いる場合であっても、はんだ付けに際しての残渣
の発生を減少／回避することのできる、フラックスを用
いないはんだ付け方法と、該方法を用いて電子部品を配
線基板に搭載する、電子装置の製造方法とを提供するこ
とを目的とする。Accordingly, the present invention provides a flux-free soldering method which can reduce / avoid generation of residues during soldering even when a solder material having a high Sn content is used, and a method using the same. And a method for manufacturing an electronic device in which an electronic component is mounted on a wiring board by using the method.
【００１２】[0012]
【課題を解決するための手段】上記目的を達成するた
め、本発明では、はんだ材表面に酸化膜除去用組成物を
供給する酸化膜除去剤供給工程と、酸化膜除去用組成物
を介して被接合部材とはんだ材とを仮止めする仮止め工
程と、はんだ材を融点以上の温度に加熱して被接合部材
と接合させる接合工程とを、この順で備えるはんだ付け
方法であって、酸化膜除去用組成物として、酸化膜除去
作用を有する有機化合物である酸化膜除去剤と、希釈剤
とを含むものを用いるはんだ付け方法が提供される。本
発明のはんだ付け方法は、Ｐｂ含有量がＳｎ含有量より
多いＰｂ−Ｓｎ系はんだを用いるはんだリフローに、特
に適している。In order to achieve the above object, the present invention provides an oxide film removing agent supplying step of supplying an oxide film removing composition to the surface of a solder material, A soldering method comprising, in this order, a temporary fixing step of temporarily fixing a member to be joined and a solder material, and a bonding step of heating the solder material to a temperature equal to or higher than a melting point and joining the member to the member to be joined. There is provided a soldering method using a composition containing an oxide film removing agent, which is an organic compound having an oxide film removing action, and a diluent as the film removing composition. The soldering method of the present invention is particularly suitable for solder reflow using a Pb-Sn-based solder having a Pb content higher than a Sn content.
【００１３】なお、酸化膜除去剤の沸点がはんだ材の融
点より高い場合は、接合工程の後に、加熱および減圧の
少なくともいずれかを行うことにより酸化膜除去剤を除
去する工程を、さらに設けることが望ましい。また、希
釈剤の沸点が酸化膜除去剤の沸点より低い場合は、仮付
け工程と接合工程との間に、または、接合工程におい
て、加熱および減圧の少なくともいずれかにより、希釈
剤を除去することが望ましい。In the case where the boiling point of the oxide film removing agent is higher than the melting point of the solder material, a step of removing the oxide film removing agent by performing at least one of heating and decompression after the joining step is further provided. Is desirable. When the boiling point of the diluent is lower than the boiling point of the oxide film remover, the diluent may be removed by heating and / or depressurization between the tacking step and the joining step, or in the joining step. Is desirable.
【００１４】さらに、本発明では、この本発明のはんだ
付け方法を用いて、電子部品と配線基板との接合を行う
電子装置の製造方法が提供される。なお、はんだ材は、
電子部品と配線基板とのいずれに設けられてもよく、ま
た、被接合部材も、電子部品と配線基板とのいずれであ
ってもよい。Further, the present invention provides a method of manufacturing an electronic device for joining an electronic component and a wiring board by using the soldering method of the present invention. The solder material is
It may be provided on any of the electronic component and the wiring board, and the member to be joined may be any of the electronic component and the wiring board.
【００１５】[0015]
【発明の実施の形態】本発明では、はんだ付けの際に、
はんだの表面酸化膜を除去する作用を持つ有機化合物で
ある酸化膜除去剤と、希釈剤とを含む酸化膜除去用組成
物を用いる。酸化膜除去剤を希釈剤により希釈すること
により、作業に用いる液体の体積が増加するため、作業
性が向上し、均一な塗布を容易に行うことができる。従
って、本発明によれば、酸化膜除去剤の量を適正量に制
御することができ、さらに、はんだ表面へ一様に供給す
ることができる。ゆえに、本発明により適正量を均一に
供給することで、Ｓｎ含有量の多いはんだ材を用いて
も、ぬれ性よくはんだ付けすることができ、さらに、は
んだ付けに際しての残渣の発生を減少または回避するこ
とができる。本発明では、酸化膜除去剤および希釈剤と
して、はんだ材を溶出させないものを用いるため、腐食
やマイグレーションの発生などの接続信頼性を低下させ
る現象の発生を回避することができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, when soldering,
An oxide film removing composition containing an oxide film remover, which is an organic compound having an action of removing a surface oxide film of solder, and a diluent is used. By diluting the oxide film remover with the diluent, the volume of the liquid used for the operation increases, so that the workability is improved and uniform coating can be easily performed. Therefore, according to the present invention, the amount of the oxide film removing agent can be controlled to an appropriate amount, and further, it can be uniformly supplied to the solder surface. Therefore, by supplying an appropriate amount uniformly according to the present invention, soldering can be performed with good wettability even when a solder material having a high Sn content is used, and furthermore, the generation of residues at the time of soldering is reduced or avoided. can do. In the present invention, since a material that does not elute the solder material is used as the oxide film remover and the diluent, it is possible to avoid the occurrence of a phenomenon such as corrosion or migration that lowers connection reliability.
【００１６】また、本発明では、フラックスを用いない
ため、はんだ付け後にフラックス残渣を洗浄する必要も
ない。さらに、本発明では、この酸化膜除去用組成物の
表面張力または粘性により、はんだ付けする対象物を仮
止めすることができるため、はんだ付け対象物（電子部
品など）をはんだ付け位置に載置した後これをリフロー
接続するまでの搬送等における衝撃による位置ずれ、移
動、落下等を防ぐことができる。なお、良好な仮接着性
を得るためには、酸化膜除去用組成物は常温で液体であ
ることが好ましい。Further, in the present invention, since no flux is used, there is no need to clean flux residues after soldering. Furthermore, in the present invention, the object to be soldered can be temporarily fixed by the surface tension or viscosity of the composition for removing an oxide film, so that the object to be soldered (such as an electronic component) is placed at the soldering position. After that, it can be prevented from being displaced, moved, dropped, or the like due to an impact in conveyance or the like until the reflow connection is performed. In order to obtain good temporary adhesiveness, the composition for removing an oxide film is preferably liquid at room temperature.
【００１７】なお、本発明によれば、残渣を発生させる
ことなく、十分な体積の酸化膜除去用組成物をはんだ表
面に供給することができるため、これを用いて仮止めさ
れた被接続物のセルフアライメント（自己整合）により
位置精度よくはんだ付けすることができる。ここで、セ
ルフアライメントとは、溶融したはんだの表面張力によ
り被接続物がはんだ中央に移動し、再配置される現象で
ある。従って、配線基板上に電子部品を搭載する際、そ
の載置位置が所定の位置から多少のずれていても、リフ
ロー加熱の際のセルフアライメントにより、所定の位置
に接続することができる。これにより、微細接続部にお
ける高精度の位置合わせを行うことなく、簡便な工程に
より高精度の搭載が実現できる。According to the present invention, a sufficient volume of the oxide film removing composition can be supplied to the solder surface without generating a residue. Can be soldered with high positional accuracy by the self-alignment. Here, the self-alignment is a phenomenon in which an object moves to the center of the solder due to the surface tension of the molten solder and is rearranged. Therefore, when the electronic component is mounted on the wiring board, even if the mounting position is slightly deviated from the predetermined position, the electronic component can be connected to the predetermined position by self-alignment during reflow heating. Thereby, high-precision mounting can be realized by a simple process without performing high-precision positioning at the fine connection portion.
【００１８】酸化物除去剤としては、はんだ材の溶融後
も、その表面を覆って外気から遮断し、再度酸化膜が形
成されるのを回避することができるため、用いるはんだ
材の融点よりも沸点の高いものを用いることが望まし
い。この酸化物除去剤の除去は、リフロー時間を長くす
る（すなわち、はんだの接合後も所定時間加熱を続け
る）ことにより行ってもよく、また、はんだ接続後に減
圧雰囲気にし、必要に応じて加熱することにより行って
もよい。As the oxide remover, even after the solder material is melted, it can cover the surface and shield it from the outside air to avoid the formation of an oxide film again. It is desirable to use one having a high boiling point. The removal of the oxide remover may be performed by extending the reflow time (that is, heating is continued for a predetermined time after the solder is joined), or a reduced-pressure atmosphere is established after the solder connection, and heating is performed as necessary. It may be done by doing.
【００１９】このような酸化物除去剤としては、例え
ば、つぎの表１に挙げるようなものを用いることができ
る。なお、表１には、各化合物の化学式と、１気圧（７
６０Ｔｏｒｒ）における沸点とを合わせて示した。As such an oxide remover, for example, those listed in the following Table 1 can be used. Table 1 shows the chemical formula of each compound and 1 atm (7
60 Torr).
【００２０】[0020]
【表１】 [Table 1]
【００２１】酸化膜除去剤のはんだ材表面への供給量
は、多過ぎるとはんだ材が溶けだして残渣が発生するこ
とがある。この残渣は、接続不良、腐食、短絡（残渣マ
イグレーションも含む）の原因となる。従って、酸化膜
除去剤の供給量は、用いるはんだ材、酸化膜除去剤およ
び希釈剤の種類などに応じて適宜決定することが望まし
い。例えば、ペンタエチレングリコールを酸化膜除去剤
として用いる場合、その供給量は、縦横各１５ｍｍ（表
面積２．２５×１０-4ｍ2）の電子部品表面に対して、
通常、０．５ｍｇ〜１．２ｍｇ（はんだ表面積１ｍ2当
たり８．４ｇ〜２０．２ｇ）とすることが望ましい。ペ
ンタエチレングリコールの供給量が０．５ｍｇより少な
いとぬれ不良が発生することがあり、また、１．２ｍｇ
より多いとはんだ成分の鉛および錫が溶け出して、接続
不良の原因となる程度の残渣が発生することがある。If the supply amount of the oxide film removing agent to the surface of the solder material is too large, the solder material may melt and a residue may be generated. This residue causes poor connection, corrosion, and short circuit (including residue migration). Therefore, it is desirable that the supply amount of the oxide film removing agent is appropriately determined according to the type of the solder material, the oxide film removing agent, and the diluent to be used. For example, when pentaethylene glycol is used as the oxide film remover, the supply amount is 15 mm in each of the vertical and horizontal directions (surface area of 2.25 × 10 −4 m 2 ).
Usually, it is desirable to set it to 0.5 mg to 1.2 mg (8.4 g to 20.2 g per 1 m 2 of solder surface area). If the supply amount of pentaethylene glycol is less than 0.5 mg, poor wetting may occur.
If the amount is larger than the above, lead and tin of the solder component may elute, and a residue may be generated to the extent that a connection failure is caused.
【００２２】酸化膜除去用組成物の濃度および希釈剤の
添加量は、このような微量の酸化膜除去剤をはんだ材表
面に作業性よく供給することができるように、作業性よ
く供給可能な酸化膜除去用組成物の体積と、供給すべき
酸化膜除去剤量とから、適宜決定することが望ましい。
なお、酸化膜除去用組成物を、はんだ付けする２つの物
体（例えば、電子部品および配線基板）の間のはんだが
存在しない空間の体積以上に供給すると、リフローの際
に、はんだ付けする２つの物体間の気体の膨張や、酸化
膜除去用組成物の蒸発または膨張などにより、電子部品
の位置がずれる可能性があり、好ましくない。従って、
酸化物除去剤の供給量は、供給装置により安定して供給
可能な最小量以上、はんだ付けする２つの物体間のはん
だが存在しない空間の体積未満とすることが望ましい。
このような観点から、酸化膜除去用組成物における酸化
膜除去剤の濃度は、通常、６．５〜１０-2〜４．９モル
／ｄｍ3とすることが望ましく、特に、希釈剤としてア
ルコール類（メタノール、エタノール、イソプロピルア
ルコールなど）を用いる場合、６．５〜１０-2〜２．０
モル／ｄｍ3とすることが望ましい。The concentration of the oxide film removing composition and the amount of the diluent added can be supplied with good workability so that such a small amount of oxide film remover can be supplied to the solder material surface with good workability. It is desirable to appropriately determine the volume of the oxide film removing composition and the amount of the oxide film removing agent to be supplied.
When the composition for removing an oxide film is supplied to a volume greater than the volume of a space where no solder exists between two objects to be soldered (for example, an electronic component and a wiring board), two components to be soldered at the time of reflow. The position of the electronic component may shift due to the expansion of the gas between the objects and the evaporation or expansion of the oxide film removing composition, which is not preferable. Therefore,
It is desirable that the supply amount of the oxide remover be equal to or more than the minimum amount that can be stably supplied by the supply device and smaller than the volume of the space where there is no solder between the two objects to be soldered.
From such a viewpoint, the concentration of the oxide film removing agent in the composition for removing an oxide film is usually desirably 6.5 to 10 -2 to 4.9 mol / dm 3, and in particular, alcohol as a diluent When using a compound (methanol, ethanol, isopropyl alcohol, etc.), 6.5 to 10 -2 to 2.0
Desirably, it is mol / dm 3 .
【００２３】希釈剤としては、残渣の発生を防ぐため
に、はんだ材を溶解させないものを用いる。このような
ものとしては、例えば、つぎの表２に挙げるようなもの
を用いることができる。なお、表２には、各化合物の化
学式と、１気圧（７６０Ｔｏｒｒ）における沸点とを合
わせて示した。As the diluent, a diluent that does not dissolve the solder material is used in order to prevent generation of residues. For example, those listed in Table 2 below can be used. Table 2 shows the chemical formula of each compound and the boiling point at 1 atm (760 Torr).
【００２４】[0024]
【表２】 [Table 2]
【００２５】なお、希釈剤は、リフロー処理当初に蒸発
してもよく、リフロー中に蒸発してもよく、はんだ接続
後に残留した希釈剤を別途蒸発させるようにしてもよ
い。希釈剤および酸化膜除去剤がはんだ材の融点以下で
あれば、リフロー処理の当初または処理中に蒸発するた
め、はんだ接続後にこれらが残留することはない。従っ
て、これらを除去する工程が不要である、希釈剤および
酸化膜除去剤の沸点ははんだ材の融点以下であることが
好ましい。しかし、希釈剤の沸点がはんだ材の融点より
高く、はんだ接続後に希釈剤が残留する場合であって
も、希釈剤としてはんだ材が溶け出さないものを用いる
ため、残渣が発生することはない。従って、このような
場合も、希釈剤を真空脱気等により気化させるなどして
除去する工程を設ければよく、残渣を洗浄する工程を設
ける必要はない。このように、希釈剤の融点の高低は特
に問われないため、本発明では、はんだ材の融点やプロ
セス条件、酸化膜除去剤の種類などに応じて、適宜最適
な希釈剤を選択することができる。The diluent may evaporate at the beginning of the reflow process, may evaporate during the reflow process, or may separately evaporate the diluent remaining after the solder connection. If the diluent and the oxide film remover are at or below the melting point of the solder material, they evaporate at the beginning of or during the reflow process, so that they do not remain after the solder connection. Therefore, it is preferable that the boiling point of the diluent and the oxide film removing agent is not more than the melting point of the solder material. However, even when the boiling point of the diluent is higher than the melting point of the solder material and the diluent remains after the solder connection, since a diluent that does not dissolve the solder material is used, no residue is generated. Therefore, even in such a case, a step of removing the diluent by vaporizing it by vacuum degassing or the like may be provided, and there is no need to provide a step of cleaning the residue. As described above, since the level of the melting point of the diluent is not particularly limited, in the present invention, it is possible to appropriately select the optimal diluent according to the melting point of the solder material, the process conditions, the type of the oxide film remover, and the like. it can.
【００２６】[0026]
【実施例】以下、融点３２０℃の９８重量％Ｐｂ−２重
量％Ｓｎはんだ（以下、Ｐｂ2Ｓｎと記す）を用いた、
セラミック配線回路基板（以下、セラミック基板と省
略）上への電子部品の搭載に、本発明を適用した場合の
実施例について、図面を用いて説明する。なおここで取
り上げている実施例は、微細なＰｂ2Ｓｎはんだバンプ
を用いたＣ４(Controlled Collapse Chip Connection)
工程の例である。以下の説明では、はんだが配線基板上
のメタライズにぬれ拡がり、さらに、溶融はんだの表面
張力によりセルフアライメントが生じた場合に、「良好
な接続」とした。EXAMPLE A 98% by weight Pb-2% by weight Sn solder having a melting point of 320 ° C. (hereinafter referred to as Pb 2 Sn) was used.
An embodiment in which the present invention is applied to mounting of electronic components on a ceramic wiring circuit board (hereinafter abbreviated as ceramic substrate) will be described with reference to the drawings. The embodiment described here is based on C4 (Controlled Collapse Chip Connection) using fine Pb 2 Sn solder bumps.
It is an example of a process. In the following description, "good connection" is defined as the case where the solder spreads over the metallization on the wiring board and self-alignment occurs due to the surface tension of the molten solder.
【００２７】＜実施例１＞本実施例では、セラミック基
板１上に電子部品５を搭載し、はんだリフローにより接
続する際に、酸化膜除去剤として、はんだの融点よりも
沸点の高いペンタエチレングリコール（沸点３７０℃）
を用い、その希釈剤として、はんだの融点よりも沸点の
低いエタノール（沸点７８．３℃）を用いて、はんの表
面処理を行った。本実施例の各工程を図１に示す。<Embodiment 1> In this embodiment, when the electronic component 5 is mounted on the ceramic substrate 1 and connected by solder reflow, pentaethylene glycol having a boiling point higher than the melting point of the solder is used as an oxide film removing agent. (Boiling point 370 ° C)
The surface treatment of the solder was performed using ethanol having a boiling point lower than the melting point of the solder (78.3 ° C.) as a diluent. FIG. 1 shows each step of the present embodiment.
【００２８】まず、ペンタエチレングリコール１重量部
とエタノール５重量部とを混合し、酸化膜除去用組成物
３を調製した。得られた組成物３を、接続パターン２が
形成されたセラミック回路基板１表面に、接続パターン
２を覆うように塗布した（図１（ａ））。なお、組成物
３の塗布量は、塗布面縦横各１５ｍｍあたり、ペンタエ
チレングリコール量に換算して１．０ｍｇとした。First, 1 part by weight of pentaethylene glycol and 5 parts by weight of ethanol were mixed to prepare a composition 3 for removing an oxide film. The obtained composition 3 was applied to the surface of the ceramic circuit board 1 on which the connection pattern 2 was formed so as to cover the connection pattern 2 (FIG. 1A). In addition, the application amount of the composition 3 was 1.0 mg in terms of pentaethylene glycol amount for each 15 mm in the length and width of the application surface.
【００２９】この酸化膜除去用組成物３に覆われた基板
１表面に、あらかじめ接続端子部にはんだボール４が設
けられた電子部品５を、はんだボール４を下にして載置
し、各接続部を位置決めした（図１（ｂ））。これによ
り、電子部品５は、酸化膜除去用組成物３の表面張力に
より基板１上に仮止めされ、リフロー接続までの搬送時
の振動により位置ずれが生じるのを回避できた。なお、
この位置決めは、通常、はんだ４と接続パターン２との
中心を一致させる必要がる。しかし、本実施例では、は
んだ接続時のセルフアライメント効果により、仮決め時
の中心位置が多少ずれていても、問題なく接続できる。On the surface of the substrate 1 covered with the oxide film removing composition 3, an electronic component 5 in which solder balls 4 are provided in advance at connection terminal portions is placed with the solder balls 4 facing down. The part was positioned (FIG. 1 (b)). As a result, the electronic component 5 was temporarily fixed on the substrate 1 by the surface tension of the oxide film removing composition 3, and it was possible to avoid the occurrence of a positional shift due to the vibration at the time of conveyance up to the reflow connection. In addition,
This positioning usually requires that the centers of the solder 4 and the connection pattern 2 coincide with each other. However, in this embodiment, due to the self-alignment effect at the time of solder connection, connection can be made without any problem even if the center position at the time of provisional determination is slightly shifted.
【００３０】つぎに、酸化膜除去用組成物３により電子
部品５が仮固定されたセラミック基板１を、３４５℃に
リフロー加熱した。これにより、まず、組成物３に含ま
れる低沸点成分であるエタノールが蒸発し、図１（ｃ）
に示すように、高沸点成分である微量のペンタエチレン
グリコール６のみが残留して、はんだ４表面を覆うこと
になった。このペンタエチレングリコール６の還元作用
によりはんだ４の表面酸化物が除去された。また、ペン
タエチレングリコール６の沸点がはんだの融点より高い
ことから、露出したはんだ４の非酸化表面がペンタエチ
レングリコール６に覆われた状態のまま、はんだ４が溶
融し接続パターン２と接合するため、接続パターン２に
対するはんだ材４のぬれが良く、電子部品５がはんだ４
上でセルフアライメントし、良好な接続を得ることがで
きた。Next, the ceramic substrate 1 to which the electronic component 5 was temporarily fixed by the oxide film removing composition 3 was reflow-heated to 345 ° C. As a result, first, ethanol, which is a low-boiling component contained in the composition 3, evaporates, and as shown in FIG.
As shown in (1), only a trace amount of pentaethylene glycol 6, which is a high boiling point component, remained and covered the surface of the solder 4. By the reducing action of the pentaethylene glycol 6, the surface oxide of the solder 4 was removed. Further, since the boiling point of pentaethylene glycol 6 is higher than the melting point of the solder, the solder 4 is melted and joined to the connection pattern 2 while the exposed non-oxidized surface of the solder 4 is covered with the pentaethylene glycol 6. The soldering of the solder material 4 to the connection pattern 2 is good, and the electronic component 5
Self-alignment was performed above, and a good connection was obtained.
【００３１】接続後もさらに１０分間２４０℃、０．０
１Ｔｏｒｒ以下に維持してペンタエチレングリコールを
完全に蒸発させたところ、このペンタエチレングリコー
ルははんだを溶解させることなく、残渣のない清浄なは
んだ接合部を得ることができた（図１（ｄ））。以上の
工程により、セラミック基板１上に電子部品５を搭載し
た、信頼性高い電子装置を容易に製造することができ
た。After the connection, the temperature is kept at 240.degree.
When the pentaethylene glycol was completely evaporated while maintaining the pressure at 1 Torr or less, the pentaethylene glycol did not dissolve the solder, and a clean solder joint having no residue could be obtained (FIG. 1D). . Through the above steps, a highly reliable electronic device having the electronic component 5 mounted on the ceramic substrate 1 could be easily manufactured.
【００３２】＜実施例２〉希釈剤として、はんだの融点
付近の沸点を有するポリエチレングリコールモノメチル
エーテル（沸点３０５〜３７２℃）を用いた他は、実施
例１と同様にしてセラミック基板１上に電子部品５を搭
載した。本実施例においては、希釈剤の留去とほぼ並行
してはんだ４が溶融したが、本実施例においても、実施
例１と同様、信頼性高い電子回路を容易に製造すること
ができた。Example 2 An electronic device was formed on a ceramic substrate 1 in the same manner as in Example 1 except that polyethylene glycol monomethyl ether having a boiling point near the melting point of the solder (boiling point: 305 to 372 ° C.) was used as a diluent. Component 5 was mounted. In the present embodiment, the solder 4 was melted almost in parallel with the distilling off of the diluent, but also in this embodiment, as in the first embodiment, a highly reliable electronic circuit could be easily manufactured.
【００３３】＜実施例３〉希釈剤として、はんだの融点
より高い沸点を有するポリプロピレングリコールモノブ
チルエーテル（沸点３５５〜３９５℃）を用いた他は、
実施例１と同様にしてセラミック基板１上に電子部品５
を搭載した。本実施例においては、希釈剤の留去に先立
ってはんだ４が溶融したが、本実施例においても、実施
例１と同様、残渣のない清浄なはんだ接合部を得ること
ができ、信頼性高い電子回路を容易に製造することがで
きた。Example 3 A diluent was polypropylene glycol monobutyl ether (boiling point: 355 to 395 ° C.) having a boiling point higher than the melting point of the solder.
The electronic component 5 is formed on the ceramic substrate 1 in the same manner as in the first embodiment.
Equipped. In this embodiment, the solder 4 was melted before the diluent was distilled off. However, in this embodiment, as in the first embodiment, a clean solder joint having no residue can be obtained, and high reliability can be obtained. Electronic circuits could be easily manufactured.
【００３４】[0034]
【発明の効果】以上説明したように、本発明によれば、
仮止めのための接着剤として機能する程度の量の酸化膜
除去用組成物を用いても、それに含まれる酸化膜除去剤
の量を微量にコントロールできるため、フラックスを用
いることなく、残渣の発生を減少／回避しつつ、Ｓｎ含
有量の多いはんだ材を用いたはんだ付けを行うことがで
きる。従って、本発明によれば、はんだ材の溶出、残渣
の残留による腐食やマイグレーションなどの発生を回避
することができる。さらに、仮止めにより回路基板と電
子部品は搬送等の振動、衝撃による位置ずれ、移動、落
下等を防止することができる。As described above, according to the present invention,
Even if an amount of the oxide film removing composition that functions as an adhesive for temporary fixing is used, since the amount of the oxide film removing agent contained therein can be controlled to a very small amount, generation of residues without using a flux can be achieved. Can be reduced / avoided and soldering using a solder material having a high Sn content can be performed. Therefore, according to the present invention, it is possible to avoid the occurrence of corrosion, migration, and the like due to dissolution of the solder material and residual residue. In addition, the circuit board and the electronic component can be prevented from being misaligned, moved, dropped, or the like due to vibration or impact during transportation due to the temporary fixing.
【図１】 実施例における電子装置の製造工程を示す説
明図である。FIG. 1 is an explanatory diagram illustrating a manufacturing process of an electronic device according to an embodiment.
１…セラミック回路基板、２…接続パターン、３…酸化
膜除去用組成物、４…はんだ材、５…電子部品、６…酸
化膜除去剤。DESCRIPTION OF SYMBOLS 1 ... Ceramic circuit board, 2 ... Connection pattern, 3 ... Composition for oxide film removal, 4 ... Solder material, 5 ... Electronic component, 6 ... Oxide film removal agent.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｃ２３Ｇ 5/032 Ｃ２３Ｇ 5/032 Ｈ０１Ｌ 21/60 ３１１ Ｈ０１Ｌ 21/60 ３１１Ｓ (72)発明者 岩田 泰宏 神奈川県秦野市堀山下１番地 株式会社日 立製作所汎用コンピュータ事業部内 (72)発明者 白井 貢 神奈川県秦野市堀山下１番地 株式会社日 立製作所汎用コンピュータ事業部内 (72)発明者 佐藤 了平 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. 6 Identification code FI C23G 5/032 C23G 5/032 H01L 21/60 311 H01L 21/60 311S (72) Inventor Yasuhiro Iwata 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Address: General Computer Division, Hitachi, Ltd. (72) Inventor: Mitsuru Shirai 1st General Horiyama, Hadano-shi, Kanagawa Prefecture: Computer: 72, Hitachi, Ltd.Ryohei Sato: Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture 292 Hitachi Manufacturing Co., Ltd.
Claims (9)
する酸化膜除去剤供給工程と、 上記酸化膜除去用組成物を介して被接合部材と上記はん
だ材とを仮止めする仮止め工程と、 上記はんだ材を融点以上の温度に加熱して、上記被接合
部材と接合させる接合工程とを、この順で備え、 上記酸化膜除去用組成物は、 酸化膜除去作用を有する有機化合物である酸化膜除去剤
と、希釈剤とを含むことを特徴とするはんだ付け方法。An oxide film removing agent supplying step of supplying an oxide film removing composition to the surface of a solder material, and a temporary fixing of the member to be joined and the solder material through the oxide film removing composition. And a bonding step of heating the solder material to a temperature equal to or higher than the melting point and bonding the solder material to the member to be bonded, in this order, wherein the oxide film removing composition is an organic compound having an oxide film removing action. A soldering method, comprising: an oxide film remover as described in (1) and a diluent.
リエチレングリコールモノメチルエーテル、ポリプロピ
レングリコールモノメチルエーテルおよびポリプロピレ
ングリコールモノブチルエーテルのうちの、少なくとも
いずれかであることを特徴とする請求項１記載のはんだ
付け方法。2. The method according to claim 1, wherein the diluent is at least one of methanol, ethanol, isopropyl alcohol, polyethylene glycol monomethyl ether, polypropylene glycol monomethyl ether, and polypropylene glycol monobutyl ether. Soldering method.
ル、ペンタエチレングリコールモノブチルエーテル、ヘ
キサエチレングリコールモノブチルエーテル、ジエチレ
ングリコールドデシルエーテル、テトラエチレングリコ
ールドデシルエーテル、ペンタデカノール、オクタデカ
ノールおよびイコサノールのうちの、少なくともいずれ
かであることを特徴とする請求項１記載のはんだ付け方
法。3. The oxide film-removing agent includes pentaethylene glycol, hexaethylene glycol, pentaethylene glycol monobutyl ether, hexaethylene glycol monobutyl ether, diethylene glycol dodecyl ether, tetraethylene glycol dodecyl ether, pentadecanol, octadecanol and 2. The soldering method according to claim 1, wherein at least one of icosanol is used.
膜除去剤の濃度は、６．５×１０-2モル／ｄｍ3〜４．
９モル／ｄｍ3であることを特徴とする請求項１記載の
はんだ付け方法。4. The concentration of the oxide film removing agent in the composition for removing an oxide film is 6.5 × 10 −2 mol / dm 3 to 4.
2. The soldering method according to claim 1, wherein the amount is 9 mol / dm 3 .
積１ｍ2当たり８．４〜２０．２ｇであることを特徴と
する請求項１記載のはんだ付け方法。5. A supply amount of the composition for removing an oxide film is 8.4 to 20.2 g per 1 m 2 of the surface area of the solder material in terms of a weight of the oxide film removing agent. The soldering method according to claim 1.
の融点より高く、 上記はんだ付け方法は、 上記接合工程の後に、加熱および減圧の少なくともいず
れかを行うことにより、上記酸化膜除去剤を除去する工
程を、さらに備えることを特徴とする請求項１記載のは
んだ付け方法。6. The method according to claim 6, wherein a boiling point of the oxide film removing agent is higher than a melting point of the solder material, and the soldering method comprises performing at least one of heating and depressurizing after the bonding step to remove the oxide film. 2. The soldering method according to claim 1, further comprising a step of removing an agent.
沸点より低く、 上記はんだ付け方法は、 上記仮付け工程と上記接合工程との間に、または、上記
接合工程において、 加熱および減圧の少なくともいずれかにより、上記希釈
剤を除去することを特徴とする請求項１記載のはんだ付
け方法。7. The soldering method according to claim 7, wherein a boiling point of the diluent is lower than a boiling point of the oxide film removing agent, wherein the soldering method includes heating and heating between the temporary attaching step and the joining step or in the joining step. The soldering method according to claim 1, wherein the diluent is removed by at least one of reduced pressure.
ことを特徴とするはんだ付け方法。8. The soldering method according to claim 1, wherein the solder material contains Pb and Sn, and the Pb content is larger than the Sn content.
電子部品と配線基板との接合を行うことを特徴とする電
子装置の製造方法。9. The method according to claim 1, wherein
A method for manufacturing an electronic device, comprising joining an electronic component and a wiring board.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00239598A JP3732639B2 (en) | 1998-01-08 | 1998-01-08 | Soldering method and electronic device manufacturing method |
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|---|---|---|---|
| JP00239598A JP3732639B2 (en) | 1998-01-08 | 1998-01-08 | Soldering method and electronic device manufacturing method |
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| Publication Number | Publication Date |
|---|---|
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| JP3732639B2 JP3732639B2 (en) | 2006-01-05 |
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| WO2004086493A1 (en) * | 2003-03-25 | 2004-10-07 | Fujitsu Limited | Method for manufacturing electronic component-mounted board |
| JP2008192965A (en) * | 2007-02-07 | 2008-08-21 | Denso Corp | Packaging method of semiconductor chip |
| US7944051B2 (en) | 2007-07-23 | 2011-05-17 | Renesas Electronics Corporation | Semiconductor device having external connection terminals and method of manufacturing the same |
| WO2012131817A1 (en) * | 2011-03-28 | 2012-10-04 | パナソニック株式会社 | Method for mounting semiconductor element |
| JP2012204768A (en) * | 2011-03-28 | 2012-10-22 | Panasonic Corp | Light-emitting device mounting board manufacturing method |
| JP2012204771A (en) * | 2011-03-28 | 2012-10-22 | Panasonic Corp | Semiconductor element mounting method |
| JPWO2016043092A1 (en) * | 2014-09-19 | 2017-07-06 | ソニー株式会社 | Mounting substrate and manufacturing method thereof |
| EP3358918A4 (en) * | 2015-09-30 | 2018-08-08 | Origin Electric Company, Limited | Soldered product manufacturing method |
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| JPH08293665A (en) * | 1995-04-21 | 1996-11-05 | Hitachi Ltd | Manufacture of electronic circuit |
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| JPH07235763A (en) * | 1993-12-28 | 1995-09-05 | Hitachi Ltd | Manufacture of electronic circuit |
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Cited By (12)
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|---|---|---|---|---|
| WO2004086493A1 (en) * | 2003-03-25 | 2004-10-07 | Fujitsu Limited | Method for manufacturing electronic component-mounted board |
| CN100390951C (en) * | 2003-03-25 | 2008-05-28 | 富士通株式会社 | Method for manufacturing electronic component-mounted board |
| US7595228B2 (en) | 2003-03-25 | 2009-09-29 | Fujitsu Limited | Method for manufacturing electronic component-mounted board |
| JP2008192965A (en) * | 2007-02-07 | 2008-08-21 | Denso Corp | Packaging method of semiconductor chip |
| US7944051B2 (en) | 2007-07-23 | 2011-05-17 | Renesas Electronics Corporation | Semiconductor device having external connection terminals and method of manufacturing the same |
| WO2012131817A1 (en) * | 2011-03-28 | 2012-10-04 | パナソニック株式会社 | Method for mounting semiconductor element |
| JP2012204768A (en) * | 2011-03-28 | 2012-10-22 | Panasonic Corp | Light-emitting device mounting board manufacturing method |
| JP2012204771A (en) * | 2011-03-28 | 2012-10-22 | Panasonic Corp | Semiconductor element mounting method |
| CN102822955A (en) * | 2011-03-28 | 2012-12-12 | 松下电器产业株式会社 | Semiconductor device mounting method |
| JPWO2016043092A1 (en) * | 2014-09-19 | 2017-07-06 | ソニー株式会社 | Mounting substrate and manufacturing method thereof |
| EP3358918A4 (en) * | 2015-09-30 | 2018-08-08 | Origin Electric Company, Limited | Soldered product manufacturing method |
| US10843300B2 (en) | 2015-09-30 | 2020-11-24 | Origin Company, Limited | Method for producing soldered product |
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|---|---|
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