JPH11204772A - Charge transferring apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a clock pulse delay and to enable a high speed drive by leading a wiring for applying a driving pulse to a CCD register from a midway of the CCD register. SOLUTION: A first and a second wiring layers 4, 5 and a ground wiring layer 6 are formed from e.g. a first Al layer, and a third and a fourth wiring layers 7, 8 are formed from e.g. a second Al layer and connected to the first and the second wiring layers 4, 5 through contacts 3, respectively, the wiring of a horizontal CCD register 1 is composed of metal layers of the first and the second Al layers, the third and the fourth wiring layers 7, 8 composed of the second Al layer are led from a midway of the CCD register, this permitting the clock voltage to be applied also from the midway of the horizontal CCD register. Thus it is possible to greatly suppress the delay of a driving pulse due to the load capacitance and wiring resistance in the CCD register and drive the horizontal register of large-area CCD elements at a high speed and low voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device suitable for application to a solid-state imaging device such as an area sensor and a line sensor.

[0002]

2. Description of the Related Art In a CCD type solid-state imaging device, one of the major issues is to drive a horizontal CCD register at high speed in order to achieve a large number of pixels and a large size.

FIG. 12 shows a wiring configuration of a horizontal CCD register in a CCD solid-state imaging device of a conventional area sensor, and FIG. 13 shows an equivalent circuit of one of the wirings. Horizontal C in FIG.
The CD register 51 employs a two-phase drive transfer system. A large number of transfer electrodes made of polycrystalline silicon are formed in a horizontal CCD channel 52 to which electric charges are transferred. And the second-phase transfer electrodes H2 are alternately arranged.

[0004] Each first-phase transfer electrode H1 is further connected to the first-phase transfer electrode H1t and the first-phase transfer electrode H1t from just before the transfer direction.
The first phase transfer electrode H1t is composed of a second layer of polycrystalline silicon, and the first phase storage electrode H1s is composed of a first layer of polycrystalline silicon. Further, each second-phase transfer electrode H2 is further divided into a second-phase transfer electrode H2t and a first-phase storage electrode H2s from the front in the transfer direction, and the second-phase transfer electrode H2t is formed of a second-layer polycrystalline silicon. A second phase storage electrode H2
s is constituted by the first polycrystalline silicon layer.

The first-phase transfer electrodes H1 (H1t, H1t)
s) is a first layer made of an Al layer via the contact portion 53.
And the transfer electrodes H2 (H
2t, H2s) is connected to a second wiring layer 55 made of an Al layer via a contact portion 53. First wiring layer 5
The fourth and second wiring layers 55 are arranged near the contact portion 53 in parallel with the transfer direction, and are connected to the bonding pads P ₁ and P ₂ by changing their directions in an L shape just before the transfer direction. Clock pulses φH1 and φH2 applied to the first wiring layer 54 and the second wiring layer 55 are applied to the bonding pads P ₁ and P ₂ , respectively.

Further, the horizontal C is opposed to the first wiring layer 54.
On the side opposite to the CD channel 52, a ground wiring layer 56 is formed in parallel with the transfer direction.
It is connected to the bonding pads P _G ground, where the ground potential V _GND is applied.

In the horizontal CCD register 51,
The clock is applied from only one side of the horizontal CCD register 51. Then, the equivalent circuit is approximately a circuit as shown in FIG. Therefore, the time constant τ3 of the delay in this case is
Becomes very large as τ3 = CR.

However, in a large-sized CCD solid-state imaging device, the load capacity and wiring resistance of the horizontal CCD register increase due to the increase in the number of transfer electrodes. At this time, the waveform of the high-speed clock pulse applied to the horizontal CCD register becomes dull due to the delay due to the large load capacity and the wiring resistance of the horizontal register, so that the clock pulse having the required waveform can be applied to the entire register. become unable.

[0009]

In order to solve the above-mentioned problem, there has been proposed a horizontal CCD register in which clock pulses are applied from both sides of the horizontal CCD register.

FIG. 14 shows a wiring configuration of a horizontal CCD register when clock pulses are applied from both sides, and FIG.
An equivalent circuit of one wiring is shown. The horizontal CCD register 61 shown in FIG. 14 employs a two-phase drive transfer method similarly to the horizontal CCD register shown in FIG.
In the CD channel 62, a large number of transfer electrodes made of polycrystalline silicon are formed.
The transfer electrodes H1 of the phase and the transfer electrodes H2 of the second phase are alternately arranged.

Each first-phase transfer electrode H1 is further connected to the first-phase transfer electrode H1t and the first
The first phase transfer electrode H1t is composed of a second layer of polycrystalline silicon, and the first phase storage electrode H1s is composed of a first layer of polycrystalline silicon. Further, each second-phase transfer electrode H2 is further divided into a second-phase transfer electrode H2t and a first-phase storage electrode H2s from the front in the transfer direction, and the second-phase transfer electrode H2t is formed of a second-layer polycrystalline silicon. A second phase storage electrode H2
s is constituted by the first polycrystalline silicon layer.

Each first phase transfer electrode H1 (H1t, H1
s) is a first layer made of an Al layer via the contact portion 63.
And the transfer electrodes H2 (H
2t, H2s) is connected to a second wiring layer 65 made of an Al layer via a contact portion 63. First wiring layer 6
The fourth and second wiring layers 65 are arranged in the vicinity of the contact portion 63 in parallel with the transfer direction, and are connected to the bonding pads P ₁ and P ₂ by changing their directions in an L shape just before the transfer direction. Clock pulses φH1 and φH2 applied to the first wiring layer 54 and the second wiring layer 55 are applied to the bonding pads P ₁ and P ₂ , respectively.

The horizontal C is opposed to the first wiring layer 64.
On the side opposite to the CD channel 62, a ground wiring layer 66 is formed in parallel with the transfer direction.
It is connected to the bonding pads P _G ground, where the ground potential V _GND is applied.

In the horizontal CCD register 61,
Further, for the first wiring layer 64 and the second wiring layer 65,
It has a third wiring layer 67 and a fourth wiring layer 68 that connect the bonding pads P ₁ and P ₂ and the leading-edge transfer electrode in parallel.

The first wiring layer 64, the second wiring layer 65, and the ground wiring layer 66 are formed of, for example, a first Al layer. The third wiring layer 67 and the fourth wiring layer 68 include, for example, portions 67A and 68A parallel to the transfer direction formed by the second Al layer and the transfer direction formed by the first Al layer. Are formed by the first wiring layer 64 made of the first Al layer, and the portions 67B, 68B formed by the first Al layer are formed by the first wiring layer 64, The second wiring layer 65 is formed in common with the second wiring layer 65, and the contact portion 69 forms the second layer Al
Portions 67A and 68 formed by layers and parallel to the transfer direction
A is connected.

As shown in FIG. 15, the equivalent circuit in the case of the horizontal CCD register 61 is a circuit in which parallel lines are connected to the circuit shown in FIG. In this case, the capacitance C is located at a position of R / 2 from each end where the drive pulse is applied.
Can be considered approximately as hanging. Therefore, the time constant τ2 of the delay of the horizontal CCD register 61
Is τ2 = CR / 4.

For example, in a trial calculation with a large image sensor, C = 500 pF and R = 40Ω. in this case,
τ2 = 5 ns. With such a large time constant,
For example, it seems that it is almost impossible to realize a driving frequency of 74.25 MHz (one cycle of about 13.5 ns) used for HDTV (high definition TV).

Therefore, with the above configuration, it was not possible to perform a sufficiently high-speed driving yet.

In order to solve the above-mentioned problem, the present invention reduces the delay of the clock pulse,
An object of the present invention is to provide a charge transfer device capable of high-speed driving.

[0020]

According to the charge transfer device of the present invention, a wiring for applying a driving pulse to a CCD register is connected to a C
It is also drawn from the middle of the CD register.

According to the configuration of the present invention described above, the wiring for applying the drive pulse to the CCD register is also drawn out from the middle of the CCD register, so that the drive pulse without delay is applied to a plurality of portions of the CCD register. Therefore, the delay of the driving pulse in the CCD register can be reduced.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is a charge transfer device for drawing out wiring for applying a drive pulse to a CCD register even from the middle of the CCD register.

Further, according to the present invention, in the above-described charge transfer device, a wiring for applying a driving pulse to the CCD register is provided by C
A first layer metal wiring connected to the transfer electrode of the CD register;
A second-layer metal wiring connected to the first-layer metal wiring and pulled out from a middle stage of the CCD register is provided.

Further, according to the present invention, in the above charge transfer device, the second layer metal wiring is connected to a plurality of connection pads,
The plurality of connection pads are connected to a plurality of inner leads of the package by wires, and the plurality of inner leads are commonly connected to external terminals of the package.

Further, according to the present invention, in the above-described charge transfer device, a wiring for applying a drive pulse to the CCD register is formed by dividing the metal wiring, and each of the divided metal wirings is formed of the same metal as the light-shielding metal layer. It is configured to be connected to the transfer electrode via the layer.

Hereinafter, an embodiment of the charge transfer device of the present invention will be described with reference to the drawings. This embodiment shows a case where the charge transfer device of the present invention is applied to a horizontal CCD register of an area sensor using a CCD solid-state imaging device. The horizontal CCD register 1 shown in FIG. 1 employs a two-phase drive transfer method, and a horizontal CCD channel 2 to which electric charges are transferred is provided.
A large number of transfer electrodes made of polycrystalline silicon are formed, and the polycrystalline silicon transfer electrodes are formed by alternately arranging first-phase transfer electrodes H1 and second-phase transfer electrodes H2.

Each first-phase transfer electrode H1 is further connected to the first-phase transfer electrode H1t and
The first phase transfer electrode H1t is composed of a second layer of polycrystalline silicon, and the first phase storage electrode H1s is composed of a first layer of polycrystalline silicon. Further, each second-phase transfer electrode H2 is further divided into a second-phase transfer electrode H2t and a second-phase storage electrode H2s from the near side in the transfer direction, and the second-phase transfer electrode H2t is formed of a second-layer polysilicon. A second phase storage electrode H2
s is constituted by the first polycrystalline silicon layer.

Each first phase transfer electrode H1 (H1t, H1
s) is connected to the first wiring layer 4 made of an Al layer via a contact portion (not shown), and the transfer electrode H of each second layer
2 (H2t, H2s) is connected to a second wiring layer 5 made of an Al layer via a contact portion (not shown). The first wiring layer 4 and the second wiring layer 5 are arranged in parallel with the transfer direction.

In the present embodiment, in particular, the first wiring layer 4 and the second wiring layer 5 are connected to the first wiring layer 4 and the second wiring layer 5 by three equally spaced three wiring layers. The section is divided into four sections, one section of which is about half of the section, and the third wiring layer 7 and the fourth wiring layer 8 are respectively drawn from each section. Third wiring layer 7 and fourth wiring layer 8
Are connected to the first wiring layer 4 and the second wiring layer 5 via the contact portion 3, respectively, and the other is connected to the bonding pads P ₁ and P ₂ while changing the direction in an L-shape. . _First bonding pads P ₁ and P ₂
Clock pulse φ applied to the wiring layer 4 and the second wiring layer 5
H1 and φH2 are applied.

In each of the divided sections, a ground wiring layer 6 is formed on the side opposite to the first wiring layer 4 and opposite to the horizontal CCD channel 2 in parallel with the transfer direction. It is connected to the bonding pads P _G ground, where the ground potential V _GND is applied.

The first wiring layer 4, the second wiring layer 5, and the ground wiring layer 6 are formed of, for example, a first Al layer, and the third wiring layer 7 and the fourth wiring layer 8 are formed of, for example, Second
The first wiring layer 4 and the second wiring layer 5 are formed by a contact portion 3 respectively.

As described above, the wiring of the horizontal CCD register 1 is configured by the two-layer metal wiring of the first layer of Al and the second layer of Al, and the third and third layers of the second layer of Al are formed. By adopting a configuration in which the fourth wiring layers 7 and 8 are drawn from a stage in the middle of the CCD register, a clock voltage can be applied also from a stage in the middle of the horizontal CCD register.

FIG. 2 shows an approximate equivalent circuit of one wiring (φH1 side) in the horizontal CCD register shown in FIG. The resistor is divided into seven by R / 7, and a capacitance of C / 7 or C / 3.5 hangs in the GND portion. In the equivalent circuit of FIG. 2A, when the resistance and the capacitance are combined into one, they are R / 49 and C, respectively, and are equivalent to the equivalent circuit in FIG. 2B.

As can be seen from the equivalent circuit of FIG. 2B,
The time constant τ1 of the delay is τ1 to CR / 49. This value is about 1/10 of that of the prior art. For example,
According to a trial calculation of a certain large image sensor, C = 500 pF, R
= 40Ω. When the horizontal CCD register of the present embodiment is applied, in this case, the time constant is τ1 to 0.4 ns. If the time constant can be suppressed to this extent, for example, HDTV
, A driving frequency of about 74.25 MHz (one cycle of about 13.5 ns) can be realized.

Further, a detailed configuration of the CCD register according to the present embodiment will be described. FIG. 3 shows the transfer electrodes H1t and H1.
s, H2t, H2s, the first wiring 4 and the second wiring 5
3 is an enlarged plan view showing a connection state of FIG. The third wiring 7 and the fourth wiring 8 in the upper layer are indicated by chain lines. First phase transfer electrode H
1t and H1s are formed in a comb shape under the first wiring 4 so as to commonly connect a plurality of the same transfer electrodes H1t or H1s in parallel with the first wiring 4. Then, under the first wiring 4, the second narrow-width second electrode is formed on the first-phase storage electrode H1s made of the wide first-layer polycrystalline silicon layer.
A first-phase transfer electrode H1t made of a polycrystalline silicon layer is formed so as to overlap, and both transfer electrodes H1s, H
The contact portion 10 is formed at the step portion of 1t, and is connected to the first wiring 4. On the other hand, the second-phase transfer electrode H2t,
H2s is connected to both transfer electrodes H2t and H2 under the second wiring 5.
A contact portion 10 is formed over s and is connected to the second wiring 5. The transfer electrodes H2t and H2s of the second phase are:
It is not directly connected to the next same transfer electrode H2t or H2s.

Each transfer electrode can adopt a general two-phase drive electrode configuration as shown in a sectional view in FIG. 4, for example. In FIG. 4, the above-mentioned first-phase transfer electrode H1t is formed on the surface of the N-type region 13 formed in a part of the P ⁻ well region 12 formed on the N ⁻ substrate 11 via the insulating film 15. , A first-phase storage electrode H1s, a second-phase transfer electrode H2t, and a second-phase storage electrode H
2s are respectively formed. Each storage electrode H1
s and H2s are formed by a first polycrystalline silicon layer, and the transfer electrodes H1t and H2t are formed by a second polycrystalline silicon layer. A part of the first and second polycrystalline silicon layers is vertically arranged. The duplication improves the efficiency of the transfer. The substrate surface under each of the transfer electrodes H1t and H2t made of the second polycrystalline silicon layer is an N ⁻ region 14, and each of the storage electrodes H1s,
The potential is shallower than below H2s. On the other hand, on the right ground wiring side in the drawing, a ground potential V _GND is applied from a P ⁺ region 16 formed on the surface of the P ⁻ well region 12.

The wirings 7 and 8 made of the second Al layer are connected to bonding pads P ₁ and P ₂ , one for each section. Ground wiring 6
Similarly, one bonding pad P is provided in each section.
Connected to _G. The plurality of bonding pads are connected by wires to a plurality of inner leads of a package surrounding the element, and the plurality of inner leads are commonly connected to external terminals of the package.

FIGS. 5 and 6 are schematic diagrams showing one configuration of the connection to the package. FIG. 5 shows the horizontal CCD register 1
Bonding pads P ₁ for applying a clock pulse for driving the, P ₂ and 5 sets of the bonding pads P _G for ground wiring as a set _{(P A, P B, P} C,
3 shows a configuration having bonding pads (P _D , P _E ). Each bonding pad P _1, P _2, similarly to the bonding pad P _G is other wiring is connected from the chip 20 by wire 21 to the die pad 22 of the package 25 (see cross-sectional view of FIG. 6). The die pad 22 is connected to an external terminal 24 such as a terminal pin outside the package 25 via an internal wiring 23. In FIG. 5, the five sets of bonding pads described above are grouped for each drive pulse applied by the internal wiring 23, and are connected to one external terminal 24, respectively. In FIG. 6, reference numeral 26 denotes glass provided for protecting the chip 20 and transmitting incident light.

As described above, the plurality of internal wirings 23 connected to the plurality of connection pads are connected to the external terminals 2 of the package 25.
4, the number of external terminals 24 can be suppressed. As a result, the degree of freedom in design is increased, and the size of the entire apparatus can be reduced.

Next, as another embodiment of the charge transfer device of the present invention, a configuration is shown in which the wiring layer connected to the transfer electrode is the same metal layer as the light-shielding metal layer. In the present embodiment,
As in the previous embodiment, the charge transfer device of the present invention is
The case where the present invention is applied to a horizontal CCD register of an area sensor using a CD solid-state imaging device is shown.

In this embodiment, as shown in FIG. 7, the structure of the pixel portion is such that an N-type region 32n is formed in a P ⁻ well region 31 formed on a semiconductor substrate, and the N-type region 32n is formed. 32n, a light receiving section 32 having a P ⁺ region 32p formed on the surface thereof to constitute a photodiode.
2 constitutes a pixel. On the substrate surface other than the light receiving section 32, a transfer electrode 33 is formed via a gate insulating film. The transfer electrode 33 is formed in two stages of a first layer and a second layer in FIG. An interlayer insulating film 35 is formed between the two-stage transfer electrodes 33 and over the entire surface of the transfer electrodes 33. Then, a light-shielding metal layer 36 made of, for example, aluminum, tungsten, or the like is formed on the interlayer insulating film 35 to prevent light from entering the transfer electrode 33.
An opening is formed in the light shielding metal layer 36 at a portion above the light receiving portion 32 so that light is incident on the light receiving portion 32.

FIG. 8 shows the horizontal CCD register 40 in this embodiment. This horizontal CCD register 4
0 is divided into a plurality of sections similarly to the horizontal CCD register 1 shown in FIG. 1, and a drive pulse applied from the bonding pad is supplied to each section. And
A first wiring layer 4 and a second wiring layer 5 connected to the transfer electrodes H1 and H2 of the horizontal CCD register 1 shown in FIG.
Are made of the same metal layer (such as a tungsten layer) as the light-shielding metal layer 36 shown in FIG. The third wiring layer 7 and the fourth wiring layer 8 are made of Al as in the case of FIG.
Formed by layers. Other details of the configuration are the same as those in FIG.

9A and 9B are sectional views taken along lines AA 'and BB' in FIG. 8, respectively. 9A and 9B
In FIG. 7, the transfer electrodes H1 of the first phase and the second
The transfer electrodes H2 of the phases are shown without being divided.
In FIG. 9A, the second wiring layer 5 (also used as the light-shielding metal layer 36) is connected to the transfer electrode H2 of the second phase, and the contact portion 3 of the fourth wiring layer 8 covers the transfer electrode H2. In FIG. 9B, an interlayer insulating layer 9 made of BPSG (boron-phosphorus silicate glass) or the like is provided between the second wiring layer 5 (also used as the light shielding metal layer 36) and the fourth wiring layer 8.

As described above, by using the same metal layer as the light shielding metal layer 36 and the first wiring layer 4 and the second wiring layer 5, both film formation steps can be performed simultaneously, and the manufacturing process can be performed. The process can be simplified.

Next, as another embodiment of the charge transfer device of the present invention, a wiring for applying a drive pulse to the CCD register is formed by dividing the wiring shown in FIG. 2 shows a configuration in which the semiconductor device is connected to a transfer electrode via the same metal layer. This embodiment also shows a case where the charge transfer device of the present invention is applied to a horizontal CCD register of an area sensor using a CCD solid-state imaging device, as in the above-described embodiments. The horizontal CCD register 41 shown in FIG.
As in the case of the horizontal CCD register 1 shown in FIG. 1, it is divided into a plurality of sections, and a drive pulse applied from the bonding pads P ₁ and P ₂ is supplied to each section.

Each first-phase transfer electrode H1 is connected to a first wiring layer 44 composed of a plurality of divided Al layers via a contact portion (not shown), and each second-phase transfer electrode H2 is connected to the first wiring layer 44.
Is connected to a second wiring layer 45 made of a plurality of divided Al layers via a contact portion (not shown). First
The wiring layer 44 and the second wiring layer 45 are formed in an L-shape and have a portion parallel to the transfer direction and a portion connected to the bonding pads P ₁ and P _{2 in} a direction perpendicular to the transfer direction. Consists of

A third wiring layer 42 and a fourth wiring layer 43 also serving as a light-shielding metal layer 36 made of aluminum, tungsten, or the like shown in FIG. Formed, each of the first wiring layers 4
4. The second wiring layer 45 is connected to the second wiring layer 45 via the contact portion 46, and the first wiring layers 44 and the second wiring layers 45 in the adjacent sections are electrically connected to each other. Other configurations of the transfer electrodes and the like are the same as those of the above-described embodiment of FIGS.

11A, 11B and 11C are sectional views taken along lines CC ', DD' and EE 'in FIG.
C. In FIGS. 11A, 11B, and 11C, the first-phase transfer electrode H1 and the second-phase transfer electrode H2 are not divided for simplicity.

In FIG. 11A, the fourth wiring layer 43
(Also used as the light-shielding metal layer 36) is connected to the transfer electrode H2 of the second phase, and through this, the second wiring layer 45 made of an Al layer is connected.
Is connected to In this part, the fourth wiring layer 43
Is not provided, the transfer electrode H2 of the second phase and the second wiring layer 4
5 may be directly contacted. In FIG. 11B, the fourth wiring layer 43 (also used as the light shielding metal layer 36) and the second
Interlayer insulating layer 9 made of BPSG or the like between
There is.

Then, at the intersections between the wirings 42 and 44 to which the first-phase driving pulse is applied and the wirings 43 and 45 to which the second-phase driving pulse is applied, as shown in FIG. 11C, they cross each other. The third wiring layer 42 (light shielding metal layer 36)
Is formed, the first wiring layer 44 is connected to the third wiring layer 42 via the contact portion 46, and the second wiring layer 45 is formed between the second wiring layer 44 and the third wiring layer 45. Wiring layer 4
2 is formed so as to pass above.

For example, the miniaturization and miniaturization of the CCD solid-state image pickup device have advanced, and in FIG.
6, the interlayer insulating film 35 between them becomes narrower.
Increases the capacity. The horizontal CCD shown in FIG.
In the register 40, when the distance is reduced in this way, in FIGS. 9A and 9B, the distance between the second wiring layer 45 also serving as the light shielding metal layer 36 and the first-phase transfer electrode H1 is reduced. During this time, a large capacitance is generated. This large capacity causes a delay in the transfer.

On the other hand, in the configuration of the present embodiment, the third wiring layer 42 and the fourth wiring layer 43 also serving as the light shielding metal layer 36 are formed, and other unconnected transfer electrodes (third wiring layer) are formed. Of the second-layer transfer electrode H2,
Since a portion where the distance between the fourth wiring layer 43 and the first-phase transfer electrode 43 is small and a large capacitance is generated is limited only to an adjacent portion between the divided sections, FIG. FIG.
Thus, high-speed transfer can be performed with less delay than the configuration shown in FIG.

In each of the above embodiments, the metal wiring layer is
Although the l-layer and the light-shielding metal layer are made of an Al layer or a tungsten layer, the present invention is not limited to these materials.

In each of the above-described embodiments, the charge transfer device of the present invention is connected to the horizontal CC of the CCD solid-state imaging device of the area sensor.
Applied to D register, but other line sensor CCD
The present invention can be applied to a CCD register, a delay element, and the like of a solid-state imaging device.

The charge transfer device of the present invention is not limited to the above-described embodiment, but may take various other configurations without departing from the gist of the present invention.

[0056]

According to the charge transfer device of the present invention described above, the wiring for applying the driving pulse to the CCD register is connected to the CC.
By pulling out even from the middle of the D register, the delay of the driving pulse due to the load capacitance and the wiring resistance in the CCD register can be largely suppressed. Thus, the horizontal register of a large-area CCD element can be driven at high speed and at low voltage.

Further, when the light shielding metal layer and one of the two metal wirings are used, the manufacturing process can be simplified.

Even if the wiring is divided into a plurality of parts, an increase in the number of external terminals can be suppressed by devising the internal wiring of the package.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram (plan view) of a horizontal CCD register to which a charge transfer device of the present invention is applied.

2A and 2B are equivalent circuits of the horizontal CCD register of FIG. 1;

FIG. 3 is an enlarged view near a transfer electrode of the horizontal CCD register of FIG. 1;

FIG. 4 is a cross-sectional view showing one configuration of a transfer electrode.

FIG. 5 is a plan view showing one configuration of a package and wiring of the horizontal CCD register of FIG. 1;

FIG. 6 is a cross-sectional view showing one configuration of a package and wiring of the horizontal CCD register of FIG. 1;

FIG. 7 is a schematic configuration diagram (cross-sectional view) of a pixel unit of the CCD solid-state imaging device.

FIG. 8 shows another horizontal CC to which the charge transfer device of the present invention is applied.
FIG. 3 is a schematic configuration diagram (plan view) of a main part of a D register.

9 is a sectional view taken along line AA 'of FIG. 8; B It is sectional drawing in BB 'of FIG.

FIG. 10 is a schematic configuration diagram (plan view) of a main part of still another horizontal CCD register to which the charge transfer device of the present invention is applied.

FIG. 11A is a sectional view taken along the line CC ′ of FIG. 10; B It is sectional drawing in DD 'of FIG. C It is sectional drawing in EE 'of FIG.

FIG. 12 is a schematic configuration diagram (plan view) of a conventional horizontal CCD register.

FIG. 13 is an equivalent circuit of the horizontal CCD register of FIG.

FIG. 14 shows a horizontal C having a configuration in which drive pulses are applied from both ends.
It is a schematic structure figure (top view) of a CD register.

FIG. 15 is an equivalent circuit of the horizontal CCD register of FIG. 14;

[Explanation of symbols]

1,40,41 horizontal CCD register, 2 horizontal CCD
Channel, 3 contact part, 4 first wiring layer, 5
2nd wiring layer, 6 ground wiring layer, 7 third wiring layer, 8 fourth wiring layer, 9 interlayer insulating layer, 10 contact portion, 11 substrate, 12 P ⁻ well region, 13
N type region, 14 N ⁻ region, 15 insulating film, 16
P ⁺ region, 20 chips, 21 wires, 22 die pad, 23 internal wiring, 24 external terminals, 25 package, 26 glass, 31 P ^- well region, 32 light receiving section, 33 transfer electrode, 34 gate insulating film, 35 interlayer insulation Film, 36 light shielding metal layer, 42 third wiring layer, 4
3 fourth wiring layer, 44 first wiring layer, 45 second wiring layer, 46 contact section, 51, 61 horizontal CCD
Registers, 52, 62 horizontal CCD channels, 53, 6
3, 69 contact portion, 54, 64 first wiring layer,
55, 65 second wiring layer, 56, 66 ground wiring layer, 67 third wiring layer, 68 fourth wiring layer, H1
First phase transfer electrode, H2 Second phase transfer electrode, H1t,
H2t transfer electrodes, H1s, H2s storage _{electrode, P 1, P 2, P} G bonding pads, V
_GND ground potential

Claims (4)

[Claims] 2. A charge transfer device according to claim 1, wherein a wiring for applying a drive pulse to the CCD register is also drawn out of the CCD register. 2. A wiring for applying a drive pulse to the CCD register, a first-layer metal wiring connected to a transfer electrode of the CCD register, and the CCD connected to the first-layer metal wiring.
2. The charge transfer device according to claim 1, wherein the charge transfer device includes a second-layer metal wiring extending from a middle stage of the register. 3. The second-layer metal wiring is connected to a plurality of connection pads, and the plurality of connection pads are connected to a plurality of inner leads of a package by wires. The charge transfer device according to claim 2, wherein the charge transfer device is commonly connected to an external terminal of the package. 4. A wiring for applying a drive pulse to the CCD register is formed by dividing a metal wiring, and each of the divided metal wirings is connected to a transfer electrode via the same metal layer as a light-shielding metal layer. The charge transfer device according to claim 1, wherein: