JPH11204748A - Semiconductor memory cell and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory cell which has a large storage information readout window (current difference) of the cell and can surely write/read the information and can minimize its size. SOLUTION: A semiconductor memory cell is composed of a first conductivity type first transistor TR1 having a source/drain region composed of a surface region of a region SC1 and a region SC4 and channel forming region CH1 composed of a surface region of a region SC2 , second conductivity type second transistor TR2 having a source/drain region composed of a region SC3 and a region SC2 and channel forming region CH2 composed of a surface region of a region SC2 , and a first conductivity type current-controlling junction type transistor TR3 having a gate region composed of a region SC5 and part of region SC3 opposed thereto, channel forming region CH3 composed of a region SC1 sandwiches between regions SC5 , SC3 and source/drain region composed of a region SC3 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory cell comprising a read transistor, a write transistor, and a current control junction transistor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a highly integrated semiconductor memory cell, a dynamic memory cell, also called a one-transistor memory cell, comprising one transistor and one capacitor as shown in FIG. 53 has been used. In such a memory cell, the charge stored in the capacitor needs to be a charge that causes a voltage change in the bit line. However, as the planar dimensions of the semiconductor memory cell are reduced, the size of the capacitor formed in the shape of a parallel plate is reduced. As a result, when information stored as charges in the capacitor of the memory cell is read, such information is Is buried in noise, or
Since the floating capacitance of the bit line increases with each generation of the semiconductor memory cell, the problem that only a small voltage change occurs on the bit line has become significant. As one means for solving this problem, a dynamic memory cell having a trench capacitor cell structure (see FIG. 54) or a stacked capacitor cell structure has been proposed. However, there is a limit in processing technology in the depth of the trench (groove) and the height of the stack (lamination), so that the capacity of the capacitor is also limited. Therefore, dynamic memory cells having these structures are said to reach their limits in the dimension region below the low sub-micron rule unless expensive new materials for capacitors are introduced.

Also, with regard to transistors constituting a semiconductor memory cell, problems such as deterioration of drain withstand voltage and punch-through from a drain region to a source region occur in a plane dimension less than the low submicron rule. There is a high possibility that current leakage will occur even below. Therefore, when the memory cell is miniaturized, it becomes difficult to normally operate the memory cell with the conventional transistor structure.

In order to solve such a limitation of the capacitor, the present applicant has disclosed in Japanese Patent Application No. 5-246264 (Japanese Patent Application Laid-Open No. 7-99251) two transistors or one transistor. A semiconductor memory cell consisting of transistors integrated with the above was proposed. This Japanese Unexamined Patent Publication No. 7
Of JP -99,251 15 (A) and a semiconductor memory cell disclosed in (B) includes a first semiconductor region SC ₁ of the first conductivity type formed on the semiconductor substrate surface region or an insulating substrate , A first conductive region SC ₂ provided in a surface region of _first semiconductor region SC ₁ and in contact with forming a rectifying junction
When, a second semiconductor region SC ₃ of the second conductivity type and the and the first conductive region SC ₂ provided on a first surface region of the semiconductor region SC ₁ are spaced apart, the second semiconductor Area S
A second conductive region SC ₄ in contact with and form a rectifying junction formed in a surface region of the C _3, the first semiconductor region SC ₁ and the second conductive region SC _4, and the first conductive region SC ₂ and comprises a second semiconductor region SC ₃ from conductive gate G provided through the barrier layer as to bridge, the conductive gate G is
The first conductive region SC ₂ is connected to a first wiring for selecting a memory cell, and the first conductive region SC ₂ is connected to a write information setting line,
Conductive region SC ₄ of is connected to the second wiring for memory cell selection.

The first semiconductor region SC ₁ (corresponding to the channel formation region Ch ₂ ) and the first conductive region S
C ₂ (corresponding to source / drain regions) and second semiconductor region SC ₃ (corresponding to source / drain regions)
And the conductive gate G, the switching transistor T
R ₂ is configured. In addition, a second semiconductor region SC ₃ (corresponding to the channel formation region Ch ₁ ), a first semiconductor region SC ₁ (corresponding to the source / drain region), and a second conductive region SC ₄ (source / drain (Corresponds to the drain region)
And the conductive gate G, the information storage transistor T
R ₁ is configured.

[0006]

BRIEF Problem to be Solved] In this semiconductor memory cell, during writing of information, the transistor TR ₂ is rendered conductive switch, as a result, information, potential in the channel formation region Ch ₁ of the information storing transistor TR ₁ Alternatively, they are stored in the form of electric charges. When reading information in the information storing transistor TR _1, the channel forming region C
The information storage transistor TR as viewed from the conductive gate G depends on the potential or charge (information) stored in h _1.
The threshold value of ₁ changes. Therefore, when reading the information, by applying the appropriate selection potentials to the conductive gate G, it is possible to determine the information storage state of the information storage transistor TR ₁ in the magnitude of the channel current (0 included) . This information storage transistor TR ₁
The information is read out by detecting the operation state of.

Namely, when reading the information, the information storing transistor TR _1, depending on the stored information is turned on or off. Since the second conductive region SC ₄ is connected to the second wiring, the information storage transistor T 4 depends on the stored information (“0” or “1”).
The current flowing in R ₁ is large or small. Thus, it is possible to read out the stored information by the information storing transistor TR _1.

However, when reading the information, does not have a mechanism for controlling the current flowing through the first electrically conductive region SC ₂ first semiconductor region SC ₁ sandwiched between the second semiconductor region SC ₃ . Therefore, when detecting the information stored in the information storage transistor TR ₁ by the conductive gate G,
The first semiconductor region SC ₁ to margins of the current flowing in the second conductive region SC ₄ is small, the second wiring (bit line)
However, there is a problem that the number of semiconductor memory cells that can be connected to the device is limited.

Therefore, an object of the present invention is to provide a transistor with a stable operation, a large storage information read window (current difference) in a memory cell, reliable writing / reading of information, and a reduction in size. A semiconductor memory cell that can be miniaturized or a semiconductor memory cell for logic, a semiconductor memory cell including at least three transistors, a semiconductor memory including at least two transistors integrated into one, and further including one transistor An object of the present invention is to provide a semiconductor memory cell comprising a cell or a transistor obtained by fusing at least three transistors into one, and a method for manufacturing the same.

[0010]

Means for Solving the Problems To achieve the above object,
The semiconductor memory cell according to the first aspect of the present invention
As shown in the principle diagram in FIG.
Two main surfaces A₁, A_TwoA semiconductor layer having:
First reading transistor TR having conductivity type₁
And a second transistor for writing having a second conductivity type
TA TR_TwoAnd a junction type transistor for controlling current having a first conductivity type.
Transistor TR_Three(A) first main surface A₁From the first
Main surface A of 2_TwoA first conductive layer provided on the semiconductor layer
Semiconductor first region SC having electric shape₁, (B) 1st
Main surface A of₁From the second main surface A_TwoOver the semiconductor layer
And the first area SC₁Having a second conductivity type in contact with
Conductive second region SC_Two, (C) the first area SC₁No.
Main surface A of 2_TwoRegion SC in the surface region including_TwoSeparated from
And the first area SC₁And rectifying junction
Semiconductor or conductive third region SC formed and contacted_Three,
(D) Second area SC_TwoFirst principal surface A of₁Including surface area
In the first area SC₁And the second
Area SC_TwoTo form a rectifying junction with
Conductive fourth region SC_Four, (E) the first area SC₁No.
Main surface A of 1₁Region SC in the surface region including_TwoSeparated from
And the first area SC₁And rectifying junction
Semiconductor or conductive fifth region SC formed and in contact therewith_Five,
(F) First main surface A₁On the barrier layer formed in
Area SC₁And the fourth area SC_FourIs set up like a bridge
First transistor TR₁Gate G of₁, And
(G) Second main surface A_TwoThe second layer is formed on the barrier layer
Area SC_TwoAnd the third area SC_ThreeIs set up like a bridge
The second transistor TR_TwoGate G of_Two, Having a half
A conductive memory cell, comprising: (A-1) a first transistor
TA TR₁One of the source / drain regions is a first region
SC₁First principal surface A of₁Consisting of a surface area containing
(A-2) First transistor TR₁The other source of /
The drain region is a fourth region SC_FourAnd (A
-3) First transistor TR₁Channel forming region C
H₁Is the first area SC₁First principal surface A of₁The surface comprising
Area and fourth area SC_FourThe second area SC sandwiched between_Two
First principal surface A of₁(B-
1) Second transistor TR_TwoOne source / dray
Area is a third area SC_Three(B-2)
Second transistor TR_TwoOther source / drain area of
The area is the second area SC_TwoSecond principal surface A of_TwoIncluding surface area
And (B-3) the second transistor TR_Twoof
Channel formation region CH_TwoIs the third area SC_ThreeAnd the second territory
Area SC_TwoSecond principal surface A of_TwoBetween the surface area containing
The first area SC₁Second principal surface A of_TwoSurface area containing
(C-1) junction type transistor TR_ThreeNo
The port area is the fifth area SC_FiveAnd the fifth region S
C_FiveThird area SC opposite to_Three(C-
2) Junction type transistor TR_ThreeChannel region CH_ThreeIs
Fifth area SC _FiveAnd the third area SC_ThreeThe first sandwiched between
Area SC₁(C-3) Joining type tiger
Transistor TR_ThreeOne of the source / drain regions is
Type transistor TR_ThreeChannel region CH_ThreeFrom one end of
And the first transistor TR₁One source of /
Drain region and second transistor TR_TwoChannel
Forming area CH_TwoThe first area SC constituting₁From the part
(C-4) junction type transistor TR_ThreeThe other of
The source / drain region is a junction transistor TR_Threeof
Channel region CH_ThreeArea SC extending from the other end of₁of
(D) first transistor TR₁of
Gate G₁And the second transistor TR_TwoGate G of
_TwoAre connected to a first wiring for selecting a memory cell,
(E) Third area SC_ThreeIs connected to the write information setting line.
(F) Fourth region SC_FourIs the second
(G) junction type transistor TR_Three
The other source / drain region is connected to a predetermined potential line
(H) Fifth area SC_FiveIs a second predetermined potential line
Is connected to the terminal.

[0011] In the semiconductor memory cell according to the first aspect of the present invention, as shown in the principle diagram in FIG. 1 (B), the region SC ₅ of the fifth, connected to the second predetermined potential line Alternatively, a structure for connecting to the write information setting line can be adopted. Thus, the wiring structure of the semiconductor memory cell can be simplified.

[0012] Alternatively, in the semiconductor memory cell according to the first aspect of the present invention, as shown in the principle diagram in FIG. 8 (A), the fourth region SC _4, the second memory cell selection Instead of connecting to the wiring of, connect to a predetermined potential line,
The other source / drain region of the junction-type transistor TR _3, instead of connecting to a predetermined potential line, may be a structure for connecting the second wiring for memory cell selection.
Also in this case, as shown in the principle diagram of FIG. 8B, the fifth area SC ₅ is connected to a write information setting line instead of being connected to a second predetermined potential line. You can also.

The semiconductor memory according to the first embodiment of the present invention
In the recell, the third area SC _ThreeIs the write information setting.
The structure connected to the constant line includes a third region SC_ThreeIs written
A structure that is common to a part of the only information setting line is also included. No.
4 area SC_FourIs connected to the second wiring for memory cell selection
In the structure obtained, the fourth area SC_FourIs for memory cell selection
Of the second wiring is also included. Change
Has a fifth area SC_FiveIs connected to the second predetermined potential line.
The fifth structure SC_FiveIs the second predetermined potential line
The structure which is common with a part of is also included. Alternatively,
5 area SC_FiveConnected to the write information setting line
Has a fifth area SC_FiveIs part of the write information setting line
Also included are structures that are common to Further, the fourth area SC
_FourAre connected to a predetermined potential line, the fourth region S
C_FourIs common to a part of the predetermined potential line
You.

The second object of the present invention to achieve the above object.
The semiconductor memory cell according to the aspect of FIG.
As shown in the diagram, first and second opposed two main surfaces
A₁, A_TwoHaving a first conductivity type
First transistor TR for reading₁And the second conductivity type
Writing second transistor TR having_TwoAnd the second
Junction transistor TR for current control having one conductivity type
_Three(A) first main surface A₁From the second main surface A_TwoTo
A half of a first conductivity type provided over the semiconductor layer.
Conductive first region SC₁, (B) First main surface A₁From the first
Main surface A of 2_TwoOver the semiconductor layer over the first region.
Area SC₁A second semiconductor having a second conductivity type in contact with
Area SC_Two, (C) the first area SC₁Second principal surface A of_TwoTo
The second area SC in the surface area including_TwoIs set apart from
And the first area SC₁To form a rectifying junction
Semiconductor or conductive third region SC_Three, (D) second
Area SC_TwoFirst principal surface A of₁The first area in the surface area containing
Area SC₁And the second region SC_Two
To form a rectifying junction with the semiconductor or conductive fourth
Area SC_Four, (E) fourth area SC_FourProvided in the surface area of
And the fourth area SC_FourTo form a rectifying junction
Semiconductor or conductive fifth region SC_Five, (F)
Main surface A of 1₁The first region S is formed on the barrier layer formed in
C₁And the fourth area SC_FourThe first was established like a bridge
Transistor TR₁Gate G of₁, And (g) the second
Main surface A of_TwoThe second region SC is formed on the barrier layer formed in_Two
And the third area SC_ThreeThe second to be provided as if to bridge
Transistor TR_TwoGate G of_Two, Having a semiconductor memory
(A-1) First transistor TR₁of
One source / drain region is a first region SC₁No.
Main surface A of 1₁(A-2)
First transistor TR₁Other source / drain area of
The area is the fourth area SC_FourAnd (A-3) the first
Transistor TR₁Channel forming region CH₁Is the first
Area SC₁First principal surface A of₁A fourth surface region comprising:
Area SC_FourThe second area SC sandwiched between_TwoFirst major surface of
A₁And (B-1) a second region.
Transistor TR_TwoOne of the source / drain regions is
3 area SC_ThreeAnd (B-2) the second transformer.
Jista TR_TwoThe other source / drain region of the second
Area SC_TwoSecond principal surface A of_TwoComposed of a surface area containing
(B-3) Second transistor TR_TwoChannel type
Area CH_TwoIs the third area SC_ThreeAnd the second area SC_Twoof
Second main surface A_TwoA first region sandwiched between said surface region and
Area SC₁Second principal surface A of_TwoComposed of a surface area containing
(C-1) junction type transistor TR_ThreeThe gate area
Is the fifth area SC_FiveAnd the fifth area SC_FiveAnd opposite
Second area SC_Two(C-2)
Junction type transistor TR_ThreeChannel region CH_ThreeIs the fifth
Area SC _FiveAnd the second area SC_TwoThe part sandwiched between
4 area SC_Four(C-3) junction type
Transistor TR_ThreeOne source / drain region of
Junction type transistor TR_ThreeChannel region CH_ThreeOne end of
And the first transistor TR₁The other saw of
Region SC constituting a drain / drain region_FourPart of
(C-4) junction type transistor TR_ThreeOther
One of the source / drain regions is a junction type transistor TR
_ThreeChannel region CH_ThreeArea SC extending from the other end of
_FourAnd (D) the first transistor TR₁
Gate G of₁And the second transistor TR_TwoGate section
G_TwoAre connected to a first wiring for selecting a memory cell,
(E) Third area SC_ThreeIs connected to the write information setting line.
(F) First area SC₁Is connected to a predetermined potential line.
(G) junction type transistor TR_ThreeThe other source of /
The drain region is connected to the second wiring for selecting a memory cell.
(H) Fifth area SC_FiveIs a second predetermined potential line
Is connected to the terminal.

In the semiconductor memory cell according to the second embodiment of the present invention, as shown in FIG.
The region SC ₅ of the fifth, instead of connecting to a second predetermined potential line may have a structure to be connected to the second region SC _2. Thus, the wiring structure of the semiconductor memory cell can be simplified.

[0016] Alternatively, in the semiconductor memory cell according to the second aspect of the present invention, as shown in the principle diagram in FIG. 16 (A), the other source / drain region of the junction-type transistor TR _3, memory Instead of being connected to the second wiring for cell selection, it is connected to a predetermined potential line, and the first region is connected to the second wiring for memory cell selection instead of being connected to the predetermined potential line. It can also be structured. Also in this case, as shown in the principle diagram of FIG. 16B, the fifth region SC ₅ is connected to the second region SC ₂ instead of being connected to the second predetermined potential line. It can be.

The semiconductor memory according to the second embodiment of the present invention
In the recell, the third area SC _ThreeIs the write information setting.
The structure connected to the constant line includes a third region SC_ThreeIs written
A structure that is common to a part of the only information setting line is also included. Ma
The fifth area SC_FiveIs connected to a second predetermined potential line
Structure has a fifth region SC_FiveOf the second predetermined potential line
A structure common to a part is also included.

The third object of the present invention to achieve the above object.
In the semiconductor memory cell according to the embodiment, as shown in a principle diagram in FIG. 18, a sixth region SC ₆ is further formed in the structure of the semiconductor memory cell according to the second embodiment of the present invention,
Second junction type transistor TR ₄ for current control with a conductivity type is added.

That is, the semiconductor memory cell according to the third aspect of the present invention comprises two first and second opposed main surfaces A ₁ ,
Comprising a semiconductor layer having a A _2, current having a first transistor TR ₁ for reading having the first conductivity type, the second transistor TR ₂ for writing having a second conductivity type, the first conductivity type First junction type transistor T for control
R ₃ and a second junction type transistor TR ₄ for controlling current having a first conductivity type. (A) The semiconductor layer extends from the _first main surface A ₁ to the second main surface A _2. The first provided in
A semiconductor first region SC ₁ having a conductivity type, (b) provided in the semiconductor layer from the _first main surface A ₁ to the second main surface A ₂ , and a first region SC ₁ A semiconductor second region SC ₂ having a second conductivity type in contact with the second region SC ₂ , (c) a surface region including the second main surface A ₂ of the first region SC ₁ , separated from the _second region SC ₂ ; A semiconductor or conductive third region S provided and in contact with the first region SC ₁ by forming a rectifying junction.
C _3, (d) from the first region SC ₁ are spaced apart from each other in the surface area containing the first main surface A ₁ of the second region SC _2, and the second region SC ₂ and rectifying junction semiconductive or conductive fourth region SC ₄ in contact to form, provided (e) the surface area of the fourth region SC _4, and in contact to form a rectifying junction with the fourth region SC ₄ A semiconductor or conductive fifth region SC ₅ , (f) provided in a surface region including the first main surface A ₁ of the first region SC ₁ so as to be separated from the _second region SC ₂ , and , the first region SC ₁ in contact to form a rectifying junction semiconductor or conductive sixth region SC _6, (g) first
On the formed main surface A ₁ barrier layer, the first region SC ₁
The _{second portion} is formed on the gate portion G _{1 of} the first transistor TR ₁ provided so as to bridge the fourth region SC ₄ and the barrier layer formed on the (h) second main surface A 2. a semiconductor memory cell having a second gate portion G ₂ of the transistor TR _2, provided as to bridge the region SC ₂ and the third region SC _3, (a-1) of the first transistor TR ₁ One source / drain region is the first region of the first region SC ₁ .
Is composed from a surface region including a main face A _1, (A-2) the other source / drain region of the first transistor TR ₁ is composed of the fourth region SC _4, (A-3) first the channel forming region CH ₁ of the transistor TR ₁ is surface region including a first main surface a ₁ of the first region SC ₁ and is sandwiched between the fourth region SC _4, the second region SC ₂ First principal surface A of
Is composed from a surface region containing _{1, (B-1)} one source / drain region of the second transistor TR _2, the third
Consists of areas SC _3, (B-2) the other source / drain region of the second transistor TR ₂ is composed of the surface region containing the second main surface A ₂ of the second region SC _2,
(B-3) a second channel formation region CH ₂ of the transistor TR _2, the third region SC ₃ and the second second region SC ₂
A first region SC ₁ sandwiched by the surface region including the main surface A ₂ of the first region SC ₁ and a surface region including the second main surface A ₂ of the first region SC ₁ ,
(C-1) gate regions of the first junction type transistor TR ₃ is the fifth region SC _5, and is configured from the second region SC ₂ of a portion facing the region SC ₅ of the fifth, ( C-
2) a channel region C of the first junction type transistor TR ₃
H ₃ is composed of a portion of a _fourth region SC ₄ sandwiched between the fifth region SC ₅ and the portion of the second region SC ₂ , and (C
-3) one source / drain region of the first junction type transistor TR ₃ extends from one end of the first channel region CH ₃ of the junction-type transistor TR _3, and, first the other source of the transistor TR ₁ / and a fourth portion of the region SC ₄ constituting the drain region, (C-4) the other source / drain region of the first junction type transistor TR ₃ is a first channel of the junction transistor TR ₃ (D-1) The second junction transistor TR _{4 is} composed of a _fourth region SC ₄ extending from the other end of the region CH _3.
Is composed of a sixth region SC ₆ and a third region SC ₃ opposed to the _sixth region SC _6, and (D
-2) channel region CH ₄ of the second junction type transistor TR ₄ is composed of a first region SC ₁ of the portion sandwiched between the region SC ₆ of the sixth and the third region SC _3, (D -3)
One source / drain area of the second junction type transistor TR ₄ extends from one end of the second junction type transistor TR ₄ of the channel region CH _4, and, the first one of the source / drain region of the transistor TR ₁ And a first transistor forming a channel formation region CH ₂ of the second transistor TR ₂ .
Constructed from the portion of the region SC _1, (D-4) the other source / drain region of the second junction type transistor TR _4, the channel region of the second junction type transistor TR ₄ C
Is constructed from a first region SC ₁ portion extending from the other end of the H _4, (E) the gate portion G ₂ of the gate portion G ₁ and the second transistor TR ₂ of the first transistor TR _1, the memory cell selection (F) Third region SC
₃ is connected to the write information setting line, (G) the other source / drain region of the second junction type transistor TR ₄ is connected to a predetermined potential line, and (H) the first junction type transistor TR ₃ The other source / drain region is connected to a second wiring for selecting a memory cell, and (I) the fifth region SC ₅ and the sixth region SC ₆ are connected to a second predetermined potential line. It is characterized by being.

[0020] In the third semiconductor memory cell according to the aspect of the present invention, the principle diagram as shown in FIG. 21, the other source / drain region of the first junction type transistor TR _3, for memory cell selection instead of connecting the second wiring is connected to a predetermined potential line, the other source / drain region of the second junction type transistor TR _4, instead of connecting to a predetermined potential line, for memory cell selection A structure for connecting to the second wiring may be employed.

Alternatively, in the semiconductor memory cell according to the third aspect of the present invention, the fifth region SC ₅ is formed by the second region SC ₅ .
Instead of connecting to the predetermined potential line of the second region SC ₂
Can be connected. Further, instead of connecting the sixth region SC6 to the second predetermined potential line, a structure may be employed in which the _sixth region SC6 is connected to a write information setting line.
Further, as shown in the principle diagram of FIG.
_5, instead of connecting to a second predetermined potential line, connected to the second region SC _2, the region SC ₆ of the sixth, instead of connecting to a second predetermined potential line, the writing information setting A structure for connecting to a wire can also be used. Also in these cases, to illustrate the principle diagram in FIG. 28, the other source / drain region of the first junction type transistor TR _3, instead of connecting the second wiring for memory cell selection, a predetermined connected to the potential line, and the other source / drain region of the second junction type transistor TR _4, instead of connecting to a predetermined potential line, to a structure for connecting the second wiring for memory cell selection Can also.

The semiconductor memory according to the third embodiment of the present invention
In the recell, the third area SC _ThreeIs the write information setting.
The structure connected to the constant line includes a third region SC_ThreeIs written
A structure that is common to a part of the only information setting line is also included. Ma
The fifth area SC_FiveAnd the sixth area SC₆Is the second predetermined
Of the fifth region SC_Fiveas well as
Sixth area SC₆Is common to a part of the second predetermined potential line
Is included. Further, the sixth area SC₆Book
The structure connected to the writing information setting line includes a sixth area S
C₆Is common to a part of the write information setting line
included.

The fourth object of the present invention to achieve the above object.
As shown in FIG. 30, the semiconductor memory cell according to the third aspect has a structure similar to that of the semiconductor memory cell according to the second aspect of the present invention, and has a third write type having the second conductivity type. transistor TR ₅ is added to.

That is, the semiconductor memory according to the fourth aspect of the present invention.
The molycell comprises two first and second opposite major surfaces A₁,
A_TwoA semiconductor layer having a first conductivity type
First transistor TR for output₁And the second conductivity type
Write second transistor TR_TwoAnd the first guide
Current-controlled junction transistor TR
_ThreeAnd a third transistor for writing having a second conductivity type.
Star TR_Five(A) first main surface A₁From the second Lord
Surface A_TwoThe first conductivity type provided in the semiconductor layer over the
Semiconductor first region SC having₁, (B) First main surface
A₁From the second main surface A_TwoOver the semiconductor layer
First area SC₁Semiconductor with second conductivity type in contact with
Of the second area SC_Two, (C) the first area SC₁Second Lord of
Surface A_TwoRegion SC in the surface region including_TwoAway from
And the first area SC₁To form a rectifying junction
Semiconductor or conductive third region SC in contact_Three, (D)
Second area SC_TwoFirst principal surface A of₁First in the surface area containing
Area SC₁And the second region
SC_TwoSemiconductor or conductive to form a rectifying junction with
Of the fourth area SC_Four, (E) fourth area SC_FourSurface area of
And the fourth area SC_FourForms a rectifying junction with
And conductive fifth region SC_Five,
(F) First main surface A₁On the barrier layer formed in
Area SC₁And the fourth area SC_Four, And the second area SC_Two
And the fifth area SC_FiveThe first to be provided like a bridge
Transistor TR₁And the third transistor TR_FiveAnd common
Gate (G₁+ G_Five) And (g) the second main surface A_Two
The second region SC is formed on the barrier layer formed in_TwoAnd the third
Area SC_ThreeThe second Transistis was set up like a bridge
TA TR_TwoGate G of_TwoA semiconductor memory cell having
Therefore, (A-1) the first transistor TR₁One of the
Source / drain region is a first region SC₁First major surface of
A₁(A-2) the first region
Transistor TR₁The other source / drain region of
4 area SC_Four(A-3) The first transformer
Jista TR₁Channel forming region CH₁Is the first area S
C₁First principal surface A of₁Surface region including the fourth region SC
_FourThe second area SC sandwiched between_TwoFirst principal surface A of₁Including
(B-1) a second transistor
TA TR_TwoOne of the source / drain regions is a third region
SC_ThreeAnd (B-2) the second transistor T
R_TwoThe other source / drain region of the second region SC_Two
Second principal surface A of_Two(B-
3) Second transistor TR_TwoChannel forming region CH_Two
Is the third area SC_ThreeAnd the second area SC_TwoSecond principal surface A of
_TwoFirst region SC sandwiched between the surface region including₁No.
Main surface A of 2_Two(C-1)
Junction type transistor TR_ThreeGate region is a fifth region
SC_FiveAnd the fifth area SC_FiveThe second area opposite to
SC_Two(C-2) junction type transistor
Star TR_ThreeChannel region CH_ThreeIs the fifth area SC _FiveWhen
Second area SC_TwoRegion SC sandwiched between the portion_Four
And (C-3) junction type transistor T
R_ThreeOne of the source / drain regions is a junction transistor
Star TR_ThreeChannel region CH_ThreeExtends from one end of
First transistor TR₁Other source / drain area of
Fourth area SC constituting the area_FourIs composed of
(C-4) Junction type transistor TR_ThreeThe other source of /
The drain region is a junction transistor TR_ThreeChannel
Area CH_ThreeArea SC extending from the other end of_FourFrom the part
(D-1) Third transistor TR_FiveOne of
Of the first transistor TR₁
Channel forming region CH₁(D-2)
3 transistors TR_FiveOther source / drain region of
Is the fifth area SC_FiveAnd (D-3) the third
Transistor TR_FiveChannel forming region CH_FiveIs the first
Transistor TR₁From the other source / drain region of
(E) the first transistor TR₁And the third
Transistor TR_FiveAnd a common gate (G₁+ G_Five)
And the second transistor TR_TwoGate G of_TwoIs the memory
(F) The third region S is connected to the first wiring for selecting
C_ThreeIs connected to the write information setting line, and (G) the first area
Area SC₁Is connected to a predetermined potential line, and (H) junction type
Transistor TR_ThreeThe other source / drain region of
Connected to the second wiring for recell selection
And

[0025] of the present invention in a semiconductor memory cell according to the fourth aspect, the principle diagram as shown in FIG. 34, the other source / drain region of the junction-type transistor TR _3, second for memory cell selection instead of connecting to the wiring, and connected to a predetermined potential line, a first region SC _1, instead of connecting to a predetermined potential line, also be structured to be connected to the second wiring for memory cell selection it can.

A semiconductor memo according to the fourth embodiment of the present invention
In the recell, the third area SC _ThreeIs the write information setting.
The structure connected to the constant line includes a third region SC_ThreeIs written
A structure that is common to a part of the only information setting line is also included.

According to a fifth aspect of the present invention, there is provided the above-mentioned object.
As shown in a principle diagram in FIG. 36, the semiconductor memory cell according to the aspect of the present invention has a structure of the semiconductor memory cell according to the third aspect of the present invention and a structure of the semiconductor memory cell according to the fourth aspect of the present invention. Has a combined structure. That is, a sixth region SC ₆ is further formed in the structure of the semiconductor memory cell according to the second embodiment of the present invention, and a second junction type transistor TR ₄ having a first conductivity type for controlling current is added. , furthermore, the third transistor TR ₅ for writing having the second conductivity type is added.

That is, the semiconductor memory cell according to the fifth embodiment of the present invention comprises two first and second opposed main surfaces A ₁ ,
Comprising a semiconductor layer having a A _2, current having a first transistor TR ₁ for reading having the first conductivity type, the second transistor TR ₂ for writing having a second conductivity type, the first conductivity type First junction type transistor T for control
R ₃ , a second junction type transistor TR ₄ having a first conductivity type for current control, and a third transistor TR ₅ for writing having a second conductivity type. A _first semiconductor region SC ₁ having a first conductivity type, provided in the semiconductor layer from A ₁ to the second main surface A ₂ .
(B) A _second semiconductor region having a second conductivity type provided in the semiconductor layer from the _first main surface A ₁ to the second main surface A ₂ and in contact with the _first region SC _1. SC _2, (c) a second region S in the surface region containing the second main surface a ₂ of the first region SC ₁
The C ₂ are spaced apart, and the first region SC ₁ and rectifying junction is formed in contact with the semiconductor or conductive third region SC _3, (d) of the second region SC ₂ second A surface area including the _first main surface A ₁ is provided apart from the _first area SC ₁ ,
And a semiconductor or conductive fourth region SC ₄ which is in contact with the second region SC ₂ by forming a rectifying junction, (e) is provided in the surface region of the fourth region SC ₄ , and Area SC ₄
And a fifth conductive or conductive rectifying junction
Region SC _5, (f) a first main surface A ₁ of the first region SC ₁
A semiconductor or conductive sixth region SC ₆ , which is provided on the surface region including the second region SC ₂ and is separated from the second region SC ₂ and forms a rectifying junction with and contacts the first region SC ₁ . 1)
On the formed main surface A ₁ barrier layer, the first region SC ₁
When the first transistor T the fourth region SC _4, and a second region SC ₂ and the area SC ₅ of the fifth provided as to bridge
A common gate portion (G for R ₁ and third transistor TR _5)
1 + G ₅ ) and (h) a second transistor provided on the barrier layer formed on the second main surface A ₂ so as to bridge the second region SC ₂ and the third region SC _3. a semiconductor memory cell having a gate portion G ₂ of the TR _2,, (A-
1) one source / drain region of the first transistor TR ₁ is composed of a surface region including a first main surface A ₁ of the first region SC _1, (A-2) a first transistor TR
The other source / drain region _1, and a fourth region SC _4, (A-3) a first channel formation region CH ₁ of the transistor TR _1, a first main of the first region SC ₁ surface area including the surface a ₁ and is sandwiched between the fourth region SC _4,
Is composed from a surface region including a first main surface A ₁ of the second region SC _2, (B-1) one source / drain region of the second transistor TR ₂ is composed of the third region SC ₃ is, (B-2) the other source / drain region of the second transistor TR _2, a second main surface a ₂ of the second region SC ₂
Is composed from a surface region containing, (B-3) a second channel formation region CH ₂ of the transistor TR _2, the third region S
C ₃ and sandwiched between the surface region containing the second main surface A ₂ of the second region SC _2, is constructed from the surface region containing the second main surface A ₂ of the first region SC _1, (C-1) gate regions of the first junction type transistor TR ₃ is the fifth region SC _5, and is configured from the second region SC ₂ of a portion facing the region SC ₅ of the fifth, ( C-2) a channel region CH ₃ of the first junction type transistor TR ₃ includes a fifth region SC ₅ second
And a fourth region SC ₄ of the portion sandwiched between the partial region SC _2, (C-3) one source / drain region of the first junction type transistor TR ₃ is first joined extending from one end of the channel region CH ₃ types transistor TR _3, and, the first transistor TR ₁ other source /
Consists portion of the fourth region SC ₄ constituting the drain region, (C-4) the other source / drain region of the first junction type transistor TR _3, the channel region of the first junction type transistor TR ₃ and a fourth portion of the region SC ₄ extending from the other end of CH _3, (D-1) gate regions of the second junction type transistor TR _4, the area of the 6 S
C ₆ and a third region S opposed to the _sixth region SC ₆
Consists C _3, (D-2) a channel region CH ₄ of the second junction type transistor TR ₄ is first region SC ₁ sandwiched between the region SC ₆ of the sixth and the third region SC ₃ And (D-3) the second junction type transistor TR ₄
One source / drain region of the extends from one end of the second channel region CH ₄ of the junction-type transistor TR _4, and a first transistor one TR ₁ of the source / drain region and the second transistor TR ₂ is constructed from a first region SC ₁ part forming a channel formation region CH _2, (D-4) the other source / drain region of the second junction type transistor TR _4, the second junction type transistor TR ₄ is constructed from a first region SC ₁ portion extending from the other end of the channel region CH _4, (E-1) one source / drain region of the third transistor TR ₅ includes a first transistor TR ₁ channel consists formation region CH _1, (E-2) the other source / drain region of the third transistor TR ₅ is a fifth region SC _5,
(E-3) a channel forming region CH ₅ of the third transistor TR ₅ is the first transistor TR ₁ other source /
Is composed from the drain region, (F) a first transistor TR ₁ and the common gate portion between the third transistor _{TR 5 (G 1 + G 5} ) and the gate portion G ₂ of the second transistor TR _2, the memory cell Connected to the first wiring for selection,
(G) the third region SC ₃ is connected to a write information setting line, (H) the other source / drain region of the second junction transistor TR ₄ is connected to a predetermined potential line,
(I) the other source / drain region of the first junction type transistor TR ₃ is connected to the second wiring for memory cell selection, (J) region SC ₆ of the sixth, the second predetermined potential Characterized by being connected to a wire.

In the fifth embodiment of the present invention, as shown in FIG. 39, the first junction transistor TR ₃
Of the other of the source / drain regions, instead of connecting the second wiring for memory cell selection, and connected to a predetermined potential line, a second junction transistor TR ₄ other source /
Instead of connecting the drain region to a predetermined potential line, a structure in which the drain region is connected to a second wiring for selecting a memory cell can be employed.

Alternatively, in the fifth embodiment of the present invention, as shown in FIG.
₆ may be connected to a write information setting line instead of being connected to the second predetermined potential line. In this case, the principle diagram as shown in FIG. 46, the other source / drain region of the first junction type transistor TR _3,
Instead of being connected to the second wiring for selecting a memory cell, it is connected to a predetermined potential line and the second junction transistor TR ₄
The other source / drain region may be connected to a second wiring for selecting a memory cell, instead of being connected to a predetermined potential line.

The semiconductor memory according to the fifth embodiment of the present invention
In the recell, the third area SC _ThreeIs the write information setting.
The structure connected to the constant line includes a third region SC_ThreeIs written
A structure that is common to a part of the only information setting line is also included. Ma
The sixth area SC₆Is connected to a second predetermined potential line
Structure has a sixth region SC₆Of the second predetermined potential line
A structure common to a part is also included. Furthermore, the sixth area
Area SC₆Is connected to the write information setting line,
Sixth area SC₆Is common to part of the write information setting line
Is included.

The semiconductor memory cell of the present invention can be formed on an insulator (insulating layer). That is, it is preferable to have a so-called SOI structure or TFT structure.

The junction type transistors (JFET) TR ₃ , TR for controlling the current in the semiconductor memory cell of the present invention.
₄ optimizes distance (thickness of the channel region) between the opposing gate region of the junction-type transistor TR _3, TR _4, and, a junction transistor TR _3, impurities in each of the gate region facing the TR ₄ It can be formed by optimizing the concentration and the impurity concentration in the channel regions CH ₃ and CH ₄ of the junction transistors TR ₃ and TR ₄ . The distance between the gate regions (channel region C)
If the thicknesses of H ₃ and CH ₄ ) and the impurity concentration in the gate region and the channel regions CH ₃ and CH ₄ are not optimized, the depletion layer does not spread, and the ON / OFF of the junction transistor is reduced.
The off operation cannot be obtained. These optimizations need to be performed by computer simulations and experiments.

The first object of the present invention for achieving the above object is as follows.
The method for manufacturing a semiconductor memory cell according to the aspect is a method for manufacturing the semiconductor memory cell according to the first aspect of the present invention. That is, the first and second opposed two main surfaces A
_1, comprises a semiconductor layer having a A _2, the first transistor TR ₁ for reading having the first conductivity type, the second transistor TR ₂ for writing having a second conductivity type, the first
Junction type transistor TR ₃ having conductivity type for current control
(A) a first semiconductor-type region SC ₁ having the first conductivity type, provided in the semiconductor layer from the _first main surface A ₁ to the second main surface A ₂ , b) from the first major surface a ₁ second
Of over the main surface A ₂ provided on the semiconductor layer, the second region SC ₂ semiconducting having a second conductivity type in contact with the first region SC _1, (c) of the first region SC ₁ and the second region SC ₂ spaced from each other in the surface region containing the second main surface a _2,
And, the first region SC ₁ in contact to form a rectifying junction semiconductor or conductive third region SC _3, (d) a surface region comprising a first major surface A ₁ of the second region SC ₂ In the first area S
A semiconductor or conductive fourth region SC ₄ formed apart from C ₁ and in contact with the second region SC ₂ by forming a rectifying junction, (e) a first region SC ₁ of the _first region SC ₁ A surface area including the _first main surface A1 is provided apart from the _second area SC2;
And, the first region SC ₁ in contact to form a rectifying junction semiconductor or conductive fifth region SC _5, (f) the first main surface A ₁ in the formed barrier layer, the first On the gate portion G _{1 of} the first transistor TR ₁ provided so as to bridge the region SC ₁ and the fourth region SC _4, and on the barrier layer formed on the second main surface A _2. , The second area SC ₂ and the third area
The gate portion G ₂ of the second transistor TR ₂ of the region SC ₃ provided as to bridge has, (A-1) a surface region comprising a first major surface A ₁ of the first region SC ₁ (A-2) Fourth region S
The other source / drain region composed of C ₄ , (A
-3) from the first region sandwiched between the surface region and the fourth region SC ₄ including a first major surface of the SC _1, a surface area including the second of the first major surface of the region SC ₂ the first transistor TR ₁ having a channel formation region CH _1, which is configured, (B-
1) the third region SC ₃ one of the source / drain region made up of, (B-2) the other source configured from the surface region containing the second main surface A ₂ of the second region SC ₂ / Drain region, (B-3) third region SC ₃ and second region S
A channel forming region CH ₂ composed of a surface region including the second main surface A ₂ of the first region SC ₁ sandwiched between the surface region including the _second main surface A 2 of C ₂ . a second transistor TR ₂ having, (C-1) the fifth region SC _5, and the third region SC ₃ gates area consists facing the region SC ₅ said 5, (C-2) fifth region SC ₅ and the third region SC ₃ and the first region SC ₁ of the channel region composed of parts CH ₃ sandwiched between, (C-3) a channel region CH ₃ of the junction-type transistor TR ₃ extending from one end, and a first channel of one of the source / drain region and the second transistor TR ₂ of the transistor TR ₁ forming region CH ₂
The first region SC ₁ part one of the source / drain regions consist constituting a, (C-4) a first portion of the region SC ₁ extending from the other end of the channel region CH ₃ of the junction-type transistor TR ₃ And a junction type transistor TR ₃ having the other source / drain region composed of:
After forming the barrier layer on the first main surface A ₁ of the surface, the gate portion G ₁ of the first transistor TR ₁ is formed on the barrier layer, the barrier layer on the second main surface A ₂ of surface after forming, a step of forming a gate part G ₂ of the second transistor TR ₂ to the barrier layer, is optimized distance between the gate region facing the (b) junction transistor TR _3, and, The first region SC ₁ , the third region SC _3, and the fifth region SC ₃ are optimized so that the impurity concentration in each of the opposing gate regions of the junction transistor TR _{3 and} the impurity concentration in the channel region CH ₃ are optimized. Forming each of the SCs ₅ by ion implantation in an arbitrary order.

The second object of the present invention for achieving the above object is as follows.
The method for manufacturing a semiconductor memory cell according to
Manufacturing semiconductor memory cells according to second to fifth aspects
The way to do it. That is, the first and second opposed
A semiconductor layer having two main surfaces;
First reading transistor TR having conductivity type ₁
And a second transistor for writing having a second conductivity type
TA TR_TwoAnd a junction type transistor for controlling current having a first conductivity type.
Transistor TR_Three(A) first main surface A₁From the first
Main surface A of 2_TwoA first conductive layer provided on the semiconductor layer
Semiconductor first region SC having electric shape₁, (B) 1st
Main surface A of₁From the second main surface A_TwoOver the semiconductor layer
And the first area SC₁Having a second conductivity type in contact with
Conductive second region SC_Two, (C) the first area SC₁No.
Main surface A of 2_TwoRegion SC in the surface region including_TwoSeparated from
And the first area SC₁And rectifying junction
Semiconductor or conductive third region SC formed and contacted_Three,
(D) Second area SC_TwoFirst principal surface A of₁Including surface area
In the first area SC₁And the second
Area SC_TwoTo form a rectifying junction with
Conductive fourth region SC_Four, (E) fourth area SC_FourTable
A fourth region SC provided in the surface region and_FourAnd rectifying junction
Semiconductor or conductive fifth region SC in contact with
_Five, (F) first main surface A₁On the barrier layer formed in
1 area SC₁And the fourth area SC_FourIs set up like a bridge
First transistor TR₁Gate G of₁, And
(G) Second main surface A_TwoThe second layer is formed on the barrier layer
Area SC_TwoAnd the third area SC_ThreeIs set up like a bridge
The second transistor TR_TwoGate G of_Two, At least
(A-1) first area SC₁First principal surface A of₁To
One source / drain region composed of a surface region including
Area, (A-2) fourth area SC_FourThe other consisting of
Source / drain region, (A-3) first region SC₁of
First main surface A₁Surface region including the fourth region SC_FourAnd in
Second region SC sandwiched_TwoFirst principal surface A of₁Including surface
Channel formation region CH composed of regions₁Having
First transistor TR₁, (B-1) third area SC_Three
, One of the source / drain regions (B-
2) Second area SC_TwoSecond principal surface A of_TwoSurface area containing
The other source / drain region composed of (B-3)
Third area SC_ThreeAnd the second area SC_TwoSecond principal surface A of_TwoTo
First region SC sandwiched between the surface region₁Second
Main surface A of_TwoOf channel composed of surface region containing
Area CH_Two, The second transistor TR having_Two, (C-
1) Fifth area SC_FiveAnd the fifth area SC_FiveAnd opposite
Second area SC_TwoGate area consisting of
Area, (C-2) fifth area SC_FiveAnd the second area SC_TwoThe
Fourth area SC sandwiched between parts_FourConsists of
Channel region CH_Three, (C-3) junction type transistor
TR_ThreeExtending from one end of the channel region of the first
Transistor TR₁Configure the other source / drain region of
The fourth area SC_FourOne of which consists of
/ Drain region, (C-4) junction type transistor TR
_ThreeRegion SC extending from the other end of the channel region of FIG._FourPart of
Other source / drain regions composed of
Junction transistor TR_ThreeAt least from each of the
The method for manufacturing a semiconductor memory cell according to
Main surface A of 1₁After forming a barrier layer on the surface of the
The first transistor TR on the layer₁Gate G of₁Form
And the second main surface A_TwoAfter forming a barrier layer on the surface of
A second transistor TR on the barrier layer_TwoGate G of_TwoTo
Forming step and (b) junction type transistor TR_ThreePair of
The distance between the opposing gate regions is optimized and the junction
Type transistor TR_ThreeOf each opposing gate region
Concentration and channel region CH_ThreeImpurity in
So that the concentration of the substance is optimized._Two,
4 area SC_FourAnd the fifth area SC_FiveEach of the
Forming by ion implantation in this order.
It is characterized by the following.

In the first or second method of manufacturing a semiconductor memory cell according to the present invention, the first transistor T
And forming a gate part G ₁ in R _1, the second transistor TR ₂
The order of formation of the gate portion G ₂ of the may be determined depending on the structure of a semiconductor memory cell to be produced. Furthermore, the formation of the gate portion G ₁ of the first transistor TR _1, the formation of the gate portion G ₂ of the second transistor TR _2, and the formation of the respective gate region opposite the junction transistor TR _3, channel the order of the formation area CH ₃ also may be determined depending on the structure of a semiconductor memory cell to be produced.

The channel formation region or the channel region can be formed from silicon, GaAs, or the like. Each gate portion can be formed by a conventional method from metal, doped or doped silicon, amorphous silicon or polysilicon, silicide, GaAs doped with high concentration, or the like. The barrier layer is made of SiO ₂ , Si ₃ N ₄ , Al ₂ by a conventional method.
It can be formed from O ₃ , GaAlAs, or the like. Each region is doped with silicon, amorphous silicon or polysilicon, silicide, a two-layer structure of a silicide layer and a semiconductor layer, and highly doped with impurities by a conventional method according to the required characteristics and structure. Ga
It can be formed from As or the like.

In the semiconductor memory cell according to the first embodiment of the present invention, the third region SC ₃ , the fourth region SC ₄ and the fifth region SC ₅ are made of silicide, metal or metal compound. Although it may be good, it is preferred to be constituted from a semiconductor. In the semiconductor memory cell according to the second and fourth aspects of the present invention, the fourth area SC ₄ is preferably made of a semiconductor, while the third area SC ₃ and the fifth area SC ₅ may be composed of a silicide, a metal or a metal compound, but is preferably composed of a semiconductor. In the semiconductor memory cells according to the third and fifth aspects of the present invention, the fourth region S
C ₄ is preferably composed of a semiconductor, while the third region SC ₃ , the fifth region SC ₅ and the sixth region SC ₆
May be composed of a silicide, a metal, or a metal compound, but is preferably composed of a semiconductor.
Note that in the case where the conductive region is formed of silicide, a metal, or a metal compound and the conductive region is connected to a wiring, the conductive region is formed of a common material with the wiring ( For example, it can be made of a material such as titanium silicide or TiN used as a barrier layer and a glue layer. That is, a structure in which the conductive region is shared with a part of the wiring can be employed.

In the semiconductor memory cell of the present invention, the respective gate portions of the first transistor TR ₁ and the second transistor TR ₂ face each other via the semiconductor layer.
The chip area can be reduced. Also, each of the gate portion G _1, G ₂ of the first transistor TR ₁ and the second transistor TR ₂ is because it is connected to the first wiring for the selected memory cell, the first for memory cell selection Wiring is 1
A book is sufficient, and the chip area can be reduced.

[0040] In the semiconductor memory cell of the present invention, the second region SC ₂ which is the other of the source / drain regions of the second transistor TR _2, a channel formation region CH ₁ of the first transistor TR ₁ is configured ing. The third region SC ₃ corresponding to the second one of the source / drain region of the transistor TR ₂ is connected to the write information setting line. Then, by appropriately selecting the potential of the first line for memory cell selection, the first transistor TR ₁ and the second transistor TR ₂ On
The off state can be controlled. That is, when writing information, the potential of the first wiring when the second transistor TR ₂ is set to a potential which becomes sufficiently on, the second transistor TR ₂ is turned, depending on the potential of the write information setting line charge is charged in the first region SC ₁ and the second capacitor formed between region SC ₂ of the second transistor TR _2. As a result, the information is stored in the first transistor TR ₁
Of the first channel forming region CH ₁ (second region SC ₂ )
Is accumulated in the potential or charge in the form of a region SC _1. When reading information, in the first transistor TR _1, the accumulated potential or charge in the channel formation region CH ₁ (information), the second region SC ₂ and the other of the source corresponding to the channel formation region CH ₁ / It is converted into a potential difference or charge between the _fourth region SC ₄ corresponding to the drain region and a charge, and depending on the charge (information), the threshold value of the _first transistor TR ₁ viewed from the gate portion G _1. Changes. Therefore, when reading the information, by applying the appropriate selection potentials to the gate portion G _1, it may control the first ON / OFF operation transistor TR _1. Therefore, by detecting the first operation state of the transistor TR _1, it is possible to perform reading of information.

Further, in the semiconductor memory cell of the present invention, in addition to the first transistor TR ₁ and the second transistor TR ₂ , at least the junction type transistor TR ₃
Is provided. This junction type transistor TR ₃
When reading information, the control of the on / off operation is performed, the first region SC ₁ to the fourth region SC ₄ margins very large take the results of the current flowing, the second for the memory cell selected for example The number of semiconductor memory cells that can be connected to the wiring is less likely to be limited, and the information retention time (retention time) of the semiconductor memory cells can be lengthened.

[0042] In the semiconductor memory cell according to the fifth aspect of the present invention, the third transistor TR ₅ is provided in addition to the junction transistor, when reading information,
Since the on / off operation is controlled, the first area SC
₁ to the fourth region SC ₄ to more reliably very large take result margin of the current through, for example, hardly more restricted to the number of semiconductor memory cell may be connected to the second wiring for memory cell selection.

The semiconductor memory cell of the present invention holds information in the form of a potential, a potential difference, or an electric charge. However, since the information is eventually attenuated by a leak current such as a junction leak, a refresh is required. Works.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the invention (hereinafter abbreviated as embodiments). In the drawings, “first wiring” means a first wiring for selecting a memory cell, “second wiring” means a second wiring for selecting a memory cell, and “predetermined potential”. Means a predetermined potential line, and "second predetermined potential" means a second predetermined potential line.

(Embodiment 1) Embodiment 1 relates to the present invention.
The semiconductor memory cell according to the first aspect,
Method for manufacturing semiconductor memory cell according to first aspect of the present invention
About. FIG. 1A shows a principle diagram, and FIG.
As shown in an example of a schematic partial cross-sectional view in FIG.
The semiconductor memory cell according to the first aspect has a first conductivity type (for example, n
Transistor TR for reading having the shape
₁For writing having a second conductivity type (for example, p-type)
Second transistor TR_TwoAnd a first conductivity type (for example, n
Controlled Junction Transistor TR_ThreeOr
Consisting of The semiconductor memo of the first embodiment shown in FIG.
In the recell, the first transistor TR₁Gate of
Part G₁And the second transistor TR_TwoGate G of_TwoIs
First and second main surfaces A with a semiconductor layer interposed therebetween ₁, A_TwoOn it
These arrangements are arranged vertically.
And slightly off. Also, the semiconductor memory cell is supported
Formed by being surrounded by an insulating layer formed on the substrate,
It has a so-called SOI structure. In addition, the implementation shown in FIG.
In the semiconductor memory cell according to the first aspect, the support
Substrate, insulating layer, second transistor TR_TwoGate section
G_Two, The first transistor TR₁Gate G of₁Arranged in the order
Is placed.

The semiconductor memory cell according to the first embodiment has a first conductivity type (for example, (a) provided in the semiconductor layer from the _first main surface A ₁ to the second main surface A ₂ ). the first region SC ₁ of semiconducting having n-type), (b) provided from the first major surface a ₁ in the second semiconductor layer over the main surface a ₂ of the first region SC ₁ and A semiconductive second region SC ₂ having a second conductivity type (for example, p ^{+ type} ) opposite to the first conductivity type,
(C) a surface region comprising a second main surface A ₂ of the first region SC ₁ and the second region SC ₂ provided separated, and, first
Semiconductor region having the second conductivity type (for example, p ^{+ type} ), or a conductive third region S made of silicide, metal, metal compound, or the like, which is in contact with the region of the semiconductor device by forming a rectifying junction.
C _3, (d) from the first region SC ₁ are spaced apart from each other in the surface area containing the first main surface A ₁ of the second region SC _2, and the second region SC ₂ and rectifying junction A semiconductor having a first conductivity type (for example, n ^{+ type} ), or
A conductive fourth region SC ₄ made of silicide, a metal, a metal compound, or the like; and (e) a second region SC ₂ in a surface region including the first main surface A ₁ of the first region SC ₁ . Is provided at a distance and is in contact with the first region SC ₁ by forming a rectifying junction, and has a second conductivity type (for example, ap ^{+ type} ), or is made of silicide, a metal, a metal compound, or the like. The fifth conductive region SC ₅ thus formed, and (f) the first region SC ₁ and the fourth region SC ₄ are provided on the barrier layer formed on the first main surface A ₁ so as to bridge. The second region SC ₂ and the third region SC ₃ are bridged on the gate portion G _{1 of} the first transistor TR ₁ and the barrier layer formed on the second main surface A _2. The gate portion G _{2 of} the second transistor TR ₂ is provided so as to be passed.

First transistor TR₁about,
(A-1) One source / drain region is a first region
SC₁First principal surface A of₁Consisting of a surface area containing
(A-2) The other source / drain region is a fourth region
SC_Four(A-3) channel forming region CH₁
Is the first area SC₁First principal surface A of₁The surface region comprising
And the fourth area SC_FourThe second area SC sandwiched between_TwoNo.
Main surface A of 1 ₁Is comprised from the surface area containing.

Also, the second transistor TR_TwoAbout
(B-1) One source / drain region is a third source / drain region.
Area SC_ThreeAnd (B-2) the other source / source
The rain area is the second area SC_TwoSecond principal surface A of_Twoincluding
(B-3) Channel forming region C composed of a surface region
H_TwoIs the third area SC_ThreeAnd the second area SC_TwoSecond Lord of
Surface A_TwoFirst region SC sandwiched between the surface region including₁
Second principal surface A of _TwoIs comprised from the surface area containing.

[0049] Further, with respect to junction transistor TR _3, (C-1) gate regions, a fifth region SC _5, and, and a third region SC ₃ facing the region SC ₅ of the fifth , (C-2) the channel region CH ₃ is a first region SC interposed between the fifth region SC ₅ and the third region SC _3.
Is composed of _one part, (C-3) one source / drain region of the extends from one end of the channel region CH ₃ of the junction-type transistor TR _3, and the first transistor TR ₁
The first region S forming one of the source / drain regions and the channel forming region CH ₂ of the second transistor TR ₂
Consists portion C _1, (C-4) the other source / drain region is constituted by a first region SC ₁ portion extending from the other end of the channel region CH ₃ of the junction-type transistor TR _3.

The junction transistor TR ₃ has a distance (channel region CH ₃ ) between opposing gate regions (a fifth region SC ₅ and a third region SC ₃ opposing the fifth region SC ₅ ). thick) to optimize and each gate region opposite (fifth region SC ₅ and the third region SC ₃ impurity concentration in) and the channel region CH ₃ facing the region SC ₅ for the fifth ( Specifically, the first area S
It is formed by optimizing the impurity concentration in C ₁ ).

Then, the first transistor TR₁Game
G₁And the second transistor TR _TwoGate G of_TwoIs
Connects to a first wiring (for example, a word line) for selecting a memory cell.
Followed by a third area SC_ThreeIs connected to the write information setting line
Have been. Also, the fourth area SC_FourIs the memory cell selection
Connected to a second wiring (for example, a bit line)
Transistor TR_ThreeThe other source / drain region of
The fifth region SC_FiveIs the second predetermined
Are connected to the potential line.

FIGS. 2B and 3A and 3B are schematic partial cross-sectional views of a modification of the semiconductor memory cell of the first embodiment. Figure In the example shown in (B) of 2, unlike the example shown in FIG. 2 (A), the first gate portion G ₁ of the transistor TR ₁ and the second transistor TR ₂
Arrangement of the gate portion G ₂ of are generally aligned in the vertical direction. With such a structure, the area of the semiconductor memory cell can be reduced. (A) of FIG.
In the semiconductor memory cell shown in and (B), from the bottom, the supporting substrate, an insulating layer, the gate portion G ₁ of the first transistor TR _1, are arranged in the order of the gate portion G ₂ of the second transistor TR ₂ . The vertical positional relationship between the respective regions is opposite to the vertical positional relationship between the respective regions in the semiconductor memory cell shown in FIG. In the example shown in FIG. 3 (B), unlike the example shown in FIG. 3 (A), the first gate portion G ₁ of the transistor TR ₁ second transistor T
Arrangement of the gate portion G ₂ of R ₂ are generally aligned in the vertical direction.

FIGS. 4, 5, 6, and 7 are schematic partial cross-sectional views of a modification of the semiconductor memory cell of the first embodiment. Principle diagrams of the semiconductor memory cell shown in these figures are as shown in FIG. The semiconductor memory cells shown in FIGS. 4A and 4B and FIGS. 6A and 6B are modifications of the semiconductor memory cells shown in FIGS. 2A and 2B. (A), (B) and the semiconductor memory cells shown in FIGS. 7A and 7B are modifications of the semiconductor memory cells shown in FIGS. 3A and 3B.

In these semiconductor memory cells, the fifth region SC ₅ is connected to a write information setting line instead of being connected to a second predetermined potential line. The connection to the write information setting line means that the third area S
It is equivalent when connected to a C _3. Specifically, the fifth
Region SC ₅ and the connection between the third region SC _3, for example, a portion of the third region SC ₃ was Zaisa first extending up to the main surface A ₁ of the semiconductor layer, the first outer area SC ₁ In the fifth area SC ₅
By the the third extension Mashimashi portion and such that contact structure of the region SC _3, it can be obtained. With such a structure of the semiconductor memory cell, the wiring structure of the semiconductor memory cell can be simplified.

Alternatively, in the semiconductor memory cell according to the first embodiment, a principle diagram is shown in FIG.
As shown in a schematic partial cross-sectional view of FIG.
The region SC _4, instead of connecting the second wiring for memory cell selection, and connected to a predetermined potential line, the other source / drain region of the junction-type transistor TR _3, are connected to a predetermined potential line Alternatively, a structure for connecting to a second wiring for selecting a memory cell can be adopted. Again, in this case,
Shows a principle diagram in (B) of FIG. 8, a schematic partial cross-sectional view as shown in (B) of FIG. 9, instead of the region SC ₅ of the fifth, connected to the second predetermined potential line to, it may be a structure to be connected to the write information setting line (third is equivalent structure connecting to the region SC ₃ of). In addition, (A) of FIG.
It is needless to say that the structure of the semiconductor memory cell illustrated in (B) can be applied to the structure of the semiconductor memory cell illustrated in FIGS.

The method of manufacturing the semiconductor memory cell according to the first embodiment shown in FIG. 2B will be described below with reference to FIGS. 48 to 52 which are schematic partial cross-sectional views of a support substrate and the like. I do.

[Step-10] First, the silicon semiconductor substrate 10 is etched to leave a region of the silicon semiconductor substrate 10 in which a semiconductor memory cell is to be formed in a projection shape. 11 and the surface of the projection of the silicon semiconductor substrate 10 is exposed. Note that the insulating layer 11 corresponds to an element isolation region. Next, a first region SC ₁ of semiconducting having a first conductivity type (e.g., n-type) in portions of the silicon semiconductor substrate 10 protruding. The order of the formation of the first region SC ₁ and the protrusion-shaped silicon semiconductor substrate regions may be reversed. Thereafter, a silicon oxide film 12 (corresponding to a barrier layer) having a thickness of, for example, about 10 nm is formed on the surface of the protruding silicon semiconductor substrate 10 based on a known silicon oxide film forming method. This state is shown in FIG. 48A as a schematic partial cross-sectional view. Incidentally, this protruding surface of the silicon semiconductor substrate 10 corresponding to the second main surface A _2. The height of the protruding silicon semiconductor substrate 10 is 0.3 to
It may be 0.4 μm.

[0058] [Step -20] Then, the resist 20 as a mask, the oblique ion implantation method to form a second region SC ₂ semiconducting having a second conductivity type (e.g., p ⁺ -type). Thus, the first main surface provided on the semiconductor layer 10A over from (described later) to the second main surface A ₂ (corresponding to the portion of the silicon semiconductor substrate 10 projecting), the first conductivity type ( (For example, n-type) semiconductor first region S
C ₁ and a second layer provided on the semiconductor layer 10A from the first main surface to the second main surface A ₂ and in contact with the _first region SC ₁ .
Conductivity type (e.g., p ⁺ -type) to form a second region SC ₂ semiconducting having (see (B) in FIG. 48). Then, based on the known method, a polysilicon or the gate portion G ₂ for the second transistor having a polycide structure containing an impurity. This state is shown in FIG. 49A as a schematic partial cross-sectional view.

[0059] [Step -30] After that, the resist 21 as a mask, ion implantation is performed, then, by performing oblique ion implantation, the surface region comprising a second main surface A ₂ of the first region SC ₁ and the second region SC ₂ provided apart from, and to form a third region SC ₃ which is in contact to form a first region SC ₁ and the rectifying junction. This state is shown in FIG. 49B as a schematic partial cross-sectional view. Thereafter, an interlayer insulating layer 13A is formed on the entire surface, an opening is provided in the interlayer insulating layer 13A above the _third region SC3, and a wiring material layer is formed on the entire surface of the interlayer insulating layer 13A including the inside of the opening.
Next, by patterning the wiring material layer,
Third region SC ₃ conducts the provision of written information setting line with. The third region SC ₃ is not necessarily provided by an ion implantation method. When forming the write information setting line, for example, a barrier layer or a glue layer made of titanium silicide or TiN is formed, and the barrier layer or the glue layer is formed in the first region SC exposed at the bottom of the opening.
Also formed on the surface of ₁ . Thereby, a portion of the written information setting line (more specifically, a portion of the barrier layer and glue layer) a third region SC ₃ is common to the first
It can be formed in the region SC ₁ surface.

[Step-40] Then, as shown in FIG. 50A, the insulating layer 13B made of, for example, SiO ₂ is
The insulating layer 13B is formed over the entire surface by the VD method, and the surface of the insulating layer 13B is polished to flatten the surface. Then, after bonding the surface of the insulating layer 13B and the support substrate 14 (see FIG. 50B), the silicon semiconductor substrate 10 is polished from the back surface to expose the bottom 11A of the insulating layer 11 (FIG. 51). (A)). The semiconductor layer 10A corresponding to the protrusion of the silicon semiconductor substrate 10 is left in the insulating layer 11. The semiconductor layer 1
Surface of 0A corresponds to the first main surface A _1.

[Step-50] Thereafter, a silicon oxide film 15 having a thickness of, for example, about 10 nm is formed on the surface of the semiconductor layer 10A.
After forming a barrier layer (corresponding to a barrier layer) based on a known silicon oxide film forming method, a gate portion G ₁ for a first transistor having, for example, an impurity-containing polysilicon or polycide structure is formed based on a known method. (See FIG. 51B). Note that the gate portion G ₁ of the first transistor and the gate portion G ₂ of the second transistor is provided across the semiconductor layer 10A, these positional relationships are substantially aligned in the vertical direction.

[Step-60] Next, ion implantation is performed using the resist 22 as a mask, and then oblique ion implantation is performed to form a _fourth region SC4 (see FIG. 52A). .

[Step-70] Further, ion implantation is performed using the resist 23 as a mask to form a _fifth region SC5 (see FIG. 52B).

[0064] [Step -80] After that, an insulating layer is formed on the entire surface, the fourth region SC _4, the fifth region SC _5, the first region SC ₁ extending on the first main surface A ₁ An opening is formed in the upper insulating layer, and a wiring material layer is formed on the insulating layer including the inside of the opening. Next, a second wiring, a predetermined potential line, and a second predetermined potential line are formed by patterning the wiring material layer. Thus, a semiconductor memory cell having the structure shown in FIG. 2B is completed. The area SC ₅ of the fourth region SC ₄ and 5 need not necessarily be provided by ion implantation. When forming the second wiring and the second predetermined potential line, for example, a barrier layer or a glue layer made of titanium silicide or TiN is formed.
Also formed in the region SC ₁ and the second region SC ₂ of the surface.
As a result, the fourth region SC ₄ and the fifth region S which are common to the second wiring and a part of the second predetermined potential line (more specifically, a part of the barrier layer or the glue layer) are used.
The C _5, can be formed in the first region SC ₁ and the second region SC ₂ of the surface. In the semiconductor memory cell described below, when various conductive regions are formed of silicide, a metal, or a metal compound, and when the conductive region is connected to a wiring, the conductive region is not conductive. The conductive region can be made of a material common to the wiring (for example, a material such as titanium silicide or TiN used as a barrier layer or a glue layer). Thus, a structure in which the conductive region is common to part of the wiring can be formed. Note that a state in which a conductive region is formed from a compound formed by a reaction between a wiring material and silicon of a silicon semiconductor substrate is also included in a structure in which the conductive region is common to a part of the wiring.

The manufacturing process of the semiconductor memory cell is not limited to the above method. For example, the formation of the second region SC _2, instead of performing in [Step -20], [Step -5
0], for example, after forming a silicon oxide film 15 having a thickness of about 10 nm on the surface of the semiconductor layer 10A. The order of formation of each region by ion implantation depends on the process, but is essentially arbitrary.

Note that, depending on the ion implantation conditions, the junction type
Jista TR_ThreeDistance between opposing gate areas (channel
Area CH_ThreeThickness) and the junction transformer
Jista TR_ThreeOpposing gate regions (third region)
Area SC_ThreeAnd the fifth area SC _Five)
And the junction type transistor TR_ThreeChannel region CH_Three(Ingredients
Physically, the first area SC₁)
Optimize. Here, the condition of the ion implantation of impurities and the structure
Optimization is achieved through computer simulations and experiments
Just do it.

(Embodiment 2) Embodiment 2 relates to a semiconductor memory cell according to the second aspect of the present invention.
The present invention relates to a method for manufacturing a semiconductor memory cell according to a second aspect of the present invention. FIG. 10A shows a principle diagram, FIG. 11A shows an example of a schematic partial cross-sectional view, and FIG. 14A shows a schematic arrangement of a gate portion and each region. like,
The semiconductor memory cell of the second embodiment has a first transistor TR for reading having a first conductivity type (for example, n-type).
_1, a transistor TR ₂ second write preparative having a second conductivity type (e.g., p-type), a first conductivity type (e.g., n
Consisting junction transistor TR ₃ for current control have the form). In the semiconductor memory cell of the second embodiment shown in FIG. 11 (A), the gate of the first transistor TR ₁ G ₁ and the gate portion G ₂ of the second transistor TR _2, across the semiconductor layer They are provided on the first and second main surfaces A ₁ and A ₂ , respectively, and their positional relationship is slightly shifted in the vertical direction. Also, the semiconductor memory cell
It has a so-called SOI structure formed by being surrounded by an insulating layer formed over a supporting substrate. In the semiconductor memory cell according to the second embodiment shown in FIG. 11A, from the bottom, the support substrate, the insulating layer, the gate portion G ₂ of the _second transistor TR ₂ , and the gate of the first transistor TR ₁ They are arranged in order of part G _1. In FIG. 14A,
Illustration of the gate portion G ₂ and the third region SC ₃ is omitted.

In the semiconductor memory cell of the second embodiment, (a) the first conductivity type (a) provided in the semiconductor layer from the _first main surface A ₁ to the second main surface A _2. For example, n
(B) a _first region SC ₁ having semiconductor shape
A _second conductivity type (for example, p ^{+ type} ) that is provided in the semiconductor layer from the main surface A ₁ to the second main surface A ₂ and is in contact with the first region SC ₁ and that is opposite to the first conductivity type. second region SC ₂ semiconducting having, (c) a surface region comprising a second main surface a ₂ of the first region SC ₁ and the second region SC ₂ provided separated,
Forming a rectifying junction with the first region SC ₁ and in contact therewith;
The third region SC ₃ made of semiconductor having the second conductivity type (for example, p ^{+ type} ) or made of conductivity such as silicide, metal, or metal compound, and (d) the second region SC ₂ 1
A _first conductivity type (for example, an n ^{+ type)} which is provided on the surface region including the main surface A ₁ of the first region SC so as to be separated from the first region SC ₁ and forms a rectifying junction with and contacts the second region SC _2. semiconducting with), or silicide and metal, the fourth region SC ₄ conductive, which is composed of a metal compound such as provided in (e) the surface area of the fourth region SC _4, and the fourth contact with the region SC ₄ forming a rectifying junction, a second conductivity type (e.g., p
⁺ Type) semiconductor, or silicide or metal,
Conductive fifth region S composed of a metal compound or the like
C ₅ , (f) On the barrier layer formed on the first main surface A ₁ ,
The gate portion G _{1 of} the first transistor TR ₁ provided so as to bridge the first region SC ₁ and the fourth region SC ₄ , and (g) a barrier layer formed on the second main surface A ₂ above,
A gate portion G _{2 of} the second transistor TR ₂ is provided so as to bridge the second region SC ₂ and the third region SC ₃ .

First transistor TR₁about,
(A-1) One source / drain region is a first region
SC₁First principal surface A of₁Consisting of a surface area containing
(A-2) The other source / drain region is a fourth region
SC_Four(A-3) channel forming region CH₁
Is the first area SC₁First principal surface A of₁The surface region comprising
And the fourth area SC_FourThe second area SC sandwiched between_TwoNo.
Main surface A of 1 ₁Is comprised from the surface area containing.

The second transistor TR_TwoAbout
(B-1) One source / drain region is a third source / drain region.
Area SC_ThreeAnd (B-2) the other source / source
The rain area is the second area SC_TwoSecond principal surface A of_Twoincluding
(B-3) Channel forming region C composed of a surface region
H_TwoIs the third area SC_ThreeAnd the second area SC_TwoSecond Lord of
Surface A_TwoFirst region SC sandwiched between the surface region including₁
Second principal surface A of _TwoIs comprised from the surface area containing.

Further, with respect to the junction transistor TR ₃ , the (C-1) gate region is formed from the fifth region SC ₅ and the portion of the second region SC ₂ facing the _fifth region SC _5. is configured, (C-2) a channel region CH ₃ is composed of a fourth part of the region SC ₄ sandwiched by the fifth region SC ₅ and the second partial region SC _2, (C- 3) One source / drain region is a junction type transistor TR ₃
Extending from one end of the channel region CH _3, and, and a fourth portion of the region SC ₄ constituting the first other source / drain region of the transistor TR _1, (C-4)
The other source / drain region is a junction type transistor T
Fourth region S extending from the other end of channel region CH ₃ of R ₃
And a portion of the C _4.

The junction transistor TR ₃ has a distance (channel region) between opposing gate regions (a fifth region SC ₅ and a portion of the second region SC ₂ opposing the fifth region SC ₅ ). CH ₃ ) and the impurity concentration and the channel region CH in each of the opposing gate regions (the fifth region SC ₅ and the second region SC ₂ opposing the fifth region SC ₅ ). ₃ (fourth area SC ₄ )
Is optimized by optimizing the impurity concentration in the semiconductor device.

Then, the first transistor TR₁Game
G₁And the second transistor TR _TwoGate G of
_TwoIs a first wiring (for example, word
Line) and a third region SC_ThreeIs the write information setting
Connected to the wire. Also, the first area SC₁Is a given
Connected to the potential line, and the junction type transistor TR_ThreeThe other of
The source / drain region is provided with a second line for selecting a memory cell.
Line (for example, a bit line) and the fifth region SC
_FiveAre connected to a second predetermined potential line.

FIGS. 11B and 12 are schematic partial cross-sectional views of a modification of the semiconductor memory cell of the second embodiment.
(A) and (B). In the example shown in (B) of FIG. 11, unlike the example shown in (A) of FIG. 11, the arrangement of the gate portion G ₂ of the first gate G ₁ of the transistor TR ₁ and the second transistor TR ₂ The relationship is generally aligned in the vertical direction. With such a structure, the area of the semiconductor memory cell can be reduced. In the semiconductor memory cells shown in FIGS. 12A and 12B,
From below, the support substrate, the insulating layer, the first transistor TR ₁
Gate portion G ₁ of the second transistor TR _2
They are arranged in the order of ₂ . The vertical positional relationship of each region is opposite to the vertical positional relationship of each region in the semiconductor memory cell shown in FIG. Figure In the example shown in (B) of 12, unlike the example shown in (A) of FIG. 12, the arrangement of the gate portion G ₂ of the first gate G ₁ of the transistor TR ₁ and the second transistor TR ₂ The relationship is generally aligned in the vertical direction.

FIGS. 13 and 15 are schematic partial cross-sectional views of a modification of the semiconductor memory cell of the second embodiment. Further, FIG. 14B shows a schematic layout of the gate portion and each region in the semiconductor memory cell shown in FIG. 13A, and FIG. 14B shows the gate portion G in FIG.
₂ and not shown in the third region SC _3. The principle diagram of the semiconductor memory cell shown in these figures is as shown in FIG. That is, in these semiconductor memory cell, region SC ₅ of the fifth, instead of being connected to a second predetermined potential line, is connected to the second region SC _2. Specifically, the connection between the fifth region SC ₅ and the second region SC _2, for example, by extending the second part of the area SC ₂ to the first main surface A ₁ of the semiconductor layer, the outside the region SC ₄ of 4, by the fifth region SC ₅ and the second region SC ₂ of the extending Mashimashi portion and such that contact structures can be obtained. With such a structure of the semiconductor memory cell, the wiring structure of the semiconductor memory cell can be simplified. Here, the semiconductor memory cells shown in FIGS. 13A and 13B are modifications of the semiconductor memory cells shown in FIGS. 11A and 11B, and FIGS. 15A and 15B.
The semiconductor memory cell shown in FIG. 13 is a modification of the semiconductor memory cell shown in FIGS.

Alternatively, in the semiconductor memory cell according to the second embodiment, the principle diagram is shown in FIG. 16A, and a schematic partial cross-sectional view is shown in FIG. the other source / drain region of the transistor TR _3, instead of connecting the second wiring for memory cell selection, and connected to a predetermined potential line, a first region SC _1,
Instead of connecting to a predetermined potential line, it may be connected to a second wiring for selecting a memory cell. In this case as well, the principle diagram is shown in FIG. 16B, and the fifth region SC ₅ is set to the second predetermined potential as shown in a schematic partial cross-sectional view of FIG. instead of connecting the line, it may be a structure for connecting the second region SC _2. In addition, (A) of FIG.
The structure of the semiconductor memory cell illustrated in FIG.
Needless to say, the present invention can be applied to the structure of the semiconductor memory cell shown in FIG.

The semiconductor memory cell according to the second embodiment is
Except for the difference in the formation of the fifth region SC5, the _fifth region SC5 can be manufactured substantially by the method of manufacturing a semiconductor memory cell described in the first embodiment, and thus detailed description is omitted.

(Embodiment 3) Embodiment 3 relates to a semiconductor memory cell according to the third aspect of the present invention.
The present invention relates to a method for manufacturing a semiconductor memory cell according to a second aspect of the present invention. FIG. 18 shows a principle diagram, and FIG. 19A shows an example of a schematic partial cross-sectional view of the third embodiment.
Semiconductor memory cell includes a first transistor TR ₁ for reading having a first conductivity type (for example, n-type), a second transistor TR ₂ for writing having a second conductivity type (for example, p-type), A first junction-type transistor TR ₃ for controlling current having a first conductivity type (for example, n-type) and a second junction-type transistor TR ₄ for controlling current having first conductivity type (for example, n-type) Become. That is, the semiconductor memory cell of the third embodiment is different from the structure of the semiconductor memory cell according to the second aspect of the present invention described in the second embodiment in that a semiconductor or conductive sixth region SC ₆ is further added. Formed first
It has a structure in which a second junction type transistor TR ₄ for conductivity control having a conductivity type is added.

[0079] In (A) in a semiconductor memory cell according to the third embodiment shown in FIG. 19, the gate portion of the first gate G ₁ of the transistor TR ₁ and the second transistor TR ₂ G ₂
Are slightly shifted in the vertical direction. Further, the semiconductor memory cell has a so-called SOI structure formed by being surrounded by an insulating layer formed over a supporting substrate. In the semiconductor memory cell according to the third embodiment shown in FIG. 19A, the support substrate, the insulating layer, the second
The gate portion G ₂ of the transistor TR _2, are arranged in the order of the gate portion G ₁ of the first transistor TR _1.

In the semiconductor memory cell of the third embodiment, the first area SC ₁ , the second area SC ₂ , and the third area S
The arrangement of C ₃ , the fourth area SC ₄ and the fifth area SC ₅ is as follows:
This is the same as the semiconductor memory cell of the second embodiment.

The structures of the first transistor TR ₁ , the second transistor TR ₂ and the first junction transistor TR ₃ are the same as the structure of the semiconductor memory cell described in the second embodiment.

In the third embodiment, the first area SC
A surface region including a first main surface A ₁ of ₁ provided apart from the second region SC _2, and the semiconductor or conductive contact to form the first region SC ₁ and rectifying junction Sixth area S
C ₆ is formed.

[0083] With respect to the second junction transistor TR _4, (D-1) gate regions, region SC ₆ of the sixth, and the configuration from the third region SC ₃ facing the region SC ₆ of the sixth (D-2) The channel region CH ₄ is a first region SC sandwiched between a _sixth region SC ₆ and a third region SC _3.
Is composed of _one part, (D-3) one source / drain region of the extends from one end of the second junction type transistor TR ₄ of the channel region CH _4, and, the first one of the source of the transistor TR ₁ / Drain region and the first channel forming region CH ₂ of the second transistor TR ₂
Constructed from the portion of the region SC _1, (D-4) the other source / drain region, the second junction type transistor TR
The first region SC extending from the _fourth end of the channel region CH _4
It consists of _one part.

The junction type transistor TR for controlling the current
_Three, TR_FourRepresents the gate region (the fifth region SC)_Five
And the fifth area SC_FiveIn the second area SC facing_Twoof
Part and the sixth area SC₆And the sixth region S
C₆3rd area SC facing to _Three) Distance (channel
Area CH_Three, CH_FourThickness) and facing each other
Each gate region (fifth region SC_FiveAnd this
5 area SC_FiveIn the second area SC facing_TwoPart, row
In the sixth area SC₆And the sixth area SC₆Facing
Third area SC_Three) And impurity concentration in the channel
Area CH_Three, CH _Four(Fourth area SC_FourAnd the first area S
C₁By optimizing the impurity concentration in
It is formed.

Then, the first transistor TR₁Game
G₁And the second transistor TR _TwoGate G of
_TwoIs a first wiring (for example, word
Line) and a third region SC_ThreeIs the write information setting
Connected to the wire. Also, a second junction type transistor
TR_FourThe other source / drain region of the
Connected, the first junction transistor TR_ThreeOf the other
Source / drain region is a second wiring for selecting a memory cell.
(For example, a bit line) and the fifth region SC_Fiveas well as
Sixth area SC₆Is connected to a second predetermined potential line.
You.

FIGS. 19B and 20 are schematic partial cross-sectional views of a modification of the semiconductor memory cell of the third embodiment.
(A) and (B). In the example shown in (B) of FIG. 19, unlike the example shown in (A) of FIG. 19, the arrangement of the gate portion G ₂ of the first gate G ₁ of the transistor TR ₁ and the second transistor TR ₂ The relationship is generally aligned in the vertical direction. With such a structure, the area of the semiconductor memory cell can be reduced. In the semiconductor memory cells shown in FIGS. 20A and 20B,
From below, the support substrate, the insulating layer, the first transistor TR ₁
Gate portion G ₁ of the second transistor TR _2
They are arranged in the order of ₂ . The vertical positional relationship of each region is opposite to the vertical positional relationship of each region in the semiconductor memory cell shown in FIG. Figure In the example shown in (B) of 20, unlike the example shown in (A) of FIG. 20, the arrangement of the gate portion G ₂ of the first gate G ₁ of the transistor TR ₁ and the second transistor TR ₂ The relationship is generally aligned in the vertical direction.

[0087] Alternatively, in the semiconductor memory cell in the third embodiment, shows a principle diagram in FIG. 21, a schematic partial cross-sectional view as shown in FIG. 22, the other of the first junction type transistor TR ₃ the source / drain regions, instead of connecting the second wiring for memory cell selection, and connected to a predetermined potential line, the other source / drain region of the second junction type transistor TR _4, a predetermined potential Instead of being connected to a line, it may be connected to a second wiring for selecting a memory cell. It is needless to say that the structure of the semiconductor memory cell illustrated in FIG. 22 can be applied to the structure of the semiconductor memory cell illustrated in FIGS.

FIGS. 24 and 2 are schematic partial cross-sectional views of a modification of the semiconductor memory cell in the third embodiment.
FIG. 6 shows the principle of these semiconductor memory cells.
Shown in In these semiconductor memory cells, the fifth area SC ₅ is connected to the second area SC ₂ instead of being connected to the second predetermined potential line, and the sixth area SC ₆ is
Instead of being connected to the second predetermined potential line, it is connected to a write information setting line. Note that is connected to the write information setting line, is equivalent to being connected to the third region SC _3. Fifth area SC ₅ and second area S
The connection with C ₂ can be made by the method described in the second embodiment. The connection between the _sixth area SC ₆ and the write information setting line (the sixth area SC ₆ and the third area SC ₃
Connection with the fifth region S described in the first embodiment.
It can be performed through the process similar to the method of connecting the C ₅ and the third region SC _3. 24A and 24B and FIG.
5A and 5B are basically the same as the semiconductor memory cells shown in FIGS. 19A and 19B, respectively. The structure of the semiconductor memory cell shown in each of FIGS. 26A and 26B and FIGS. 27A and 27B is the same as that of the semiconductor memory cell shown in FIGS. 20A and 20B. Since the structure is basically the same as the cell structure, a detailed description is omitted. In some cases, the fifth region SC ₅ may be connected to the second region SC ₂ instead of being connected to the second predetermined potential line. Alternatively, instead of connecting the sixth region SC ₆ to the second predetermined potential line,
A structure for connecting to the write information setting line may be employed.

FIG. 29 is a schematic partial cross-sectional view of a further modified example of the semiconductor memory cell in the third embodiment, and FIG. 28 is a principle diagram of the semiconductor memory cell. In this semiconductor memory cell, the first junction type transistor T
The other source / drain region of R ₃ is connected to a predetermined potential line instead of being connected to the second wiring for selecting a memory cell, and the other source / drain region of the second junction transistor TR ₄ is connected. Are connected to a second wiring for selecting a memory cell instead of being connected to a predetermined potential line. Since the structure of the semiconductor memory cell shown in FIG. 29 is basically the same as the structure of the semiconductor memory cell shown in FIG. 24A, detailed description will be omitted. FIG. 29
It is needless to say that the structure of the semiconductor memory cell shown in FIG. 1 can be applied to the structure of the semiconductor memory cell shown in FIGS.

The semiconductor memory cell according to the third embodiment is
Except that the fifth region SC ₅ and the sixth region SC ₆ are formed differently, they can be manufactured substantially by the method of manufacturing a semiconductor memory cell described in the first embodiment.
Detailed description is omitted.

(Embodiment 4) Embodiment 4 relates to a semiconductor memory cell according to a fourth aspect of the present invention.
The present invention relates to a method for manufacturing a semiconductor memory cell according to a second aspect of the present invention. FIG. 30 shows a principle diagram, and FIG. 31A shows an example of a schematic partial cross-sectional view, and FIG. 31B shows a schematic layout diagram of a gate portion and each region. The semiconductor memory cell according to the fourth embodiment has a first conductivity type (for example, n
Transistor TR for reading having the shape
_1, the second transistor TR ₂ for writing having a second conductivity type (e.g., p-type), a first conductivity type (e.g., n
Controlled Junction Transistor TR
_3, and a third transistor TR ₅ Metropolitan for writing having a second conductivity type (e.g., p-type). That is, the semiconductor memory cell according to the fourth embodiment has a structure similar to the structure of the semiconductor memory cell according to the second embodiment of the present invention described in the second embodiment, and has a second conductivity type for writing. transistor TR ₅ of 3 has been added. FIG.
1B, the gate portion G ₂ and the third region SC ₃
Are not shown.

[0092] In the semiconductor memory cell of the fourth embodiment shown in (A) in FIG. 31, the common gate portion G ₁ + G ₅ in the first transistor TR ₁ and the third transistor TR ₅
(Hereinafter sometimes referred to as common gate portion G ₁ + G ₅₎ from the positional relationship of the gate portion G ₂ of the second transistor TR _2, it is offset slightly in the vertical direction. Further, the semiconductor memory cell has a so-called SOI structure formed by being surrounded by an insulating layer formed over a supporting substrate. In the semiconductor memory cell according to the fourth embodiment shown in FIG. 31A, the support substrate, the insulating layer, the second transistor T
The gate portion G ₂ of R _2, are arranged in order of the common gate portion (G ₁ + G _5).

In the semiconductor memory cell according to the fourth embodiment, the first area SC ₁ , the second area SC ₂ ,
The arrangement of the region SC ₃ , the fourth region SC _4, and the fifth region SC ₅ is the same as that of the semiconductor memory cell of the second embodiment.

The structures of the first transistor TR ₁ , the second transistor TR _2, and the junction transistor TR ₃ are the same as the structure of the semiconductor memory cell described in the second embodiment. The semiconductor memory cell of the fourth embodiment is different from the semiconductor memory cell of the second embodiment in that the first region SC ₁ and the fourth region SC ₁ are formed on the barrier layer formed on the first main surface A ₁ . The area SC ₄ , the second area SC ₂ and the fifth area S
A first transistor TR ₁ provided to bridge C ₅
And common common gate portion between the third transistor _{TR 5 (G 1 + G 5} ) lies in is formed. That is, the common gate portion (G ₁ + G ₅ ) has a structure extending to the end of the surface region of the fourth region SC ₄ , and the fifth region SC ₅ can be formed in a self-aligned manner.

[0095] Regarding the third transistor TR _5, (D-1) one source / drain region of the is composed of the channel forming region CH ₁ of the first transistor TR _1, (D-2) the other source / drain regions, and a fifth region SC _5, and a (D-3) a channel forming region CH _5, the other of the source / drain regions of the first transistor TR _1.

The junction transistor TR ₃ has a distance (channel region) between the opposing gate regions (the fifth region SC ₅ and the portion of the second region SC ₂ opposing the fifth region SC ₅ ). CH ₃ ) and the impurity concentration and the channel region CH in each of the opposing gate regions (the fifth region SC ₅ and the second region SC ₂ opposing the fifth region SC ₅ ). ₃ (region SC ₄ ) by optimizing the impurity concentration.

The common gate (G ₁ + G ₅ ) and the gate G ₂ of the second transistor TR ₂ are connected to a first wiring (for example, a word line) for selecting a memory cell. The third area SC ₃ is connected to a write information setting line, the first area SC ₁ is connected to a predetermined potential line,
The other source / drain region of the junction-type transistor TR ₃ and the second wiring for the selected memory cell (e.g., bit line)
It is connected to the.

Modification of Semiconductor Memory Cell of Fourth Embodiment
32 and FIG. 33A are schematic partial cross-sectional views of FIG.
And (B). In the example shown in FIG.
Unlike the example shown in (A) of FIG.₁+
G_Five) And the second transistor TR _TwoGate G of_TwoArrangement
The relationship is generally aligned in the vertical direction. like this
The structure reduces the area of the semiconductor memory cell.
Can be planned. The half shown in (A) and (B) of FIG.
In conductive memory cells, from the bottom, the support substrate, the insulation
Layer, common gate (G₁+ G_Five), The second transistor T
R_TwoGate G of_TwoAre arranged in this order. And each territory
The upper and lower positional relations of the region are the same as those shown in FIGS.
Contrary to the vertical positional relationship of each area in a conductor memory cell
Has become. In the example shown in FIG.
3A, unlike the example shown in FIG.₁+
G_Five) And the second transistor TR_TwoGate G of_TwoArrangement
The relationship is generally aligned in the vertical direction.

[0099] Alternatively, in the semiconductor memory cell in this embodiment, shows a principle diagram in FIG. 34, a schematic partial cross-sectional view as shown in Figure 35, the junction-type transistor TR ₃ other source / drain region, instead of being connected to the second wiring for memory cell selection are connected to a predetermined potential line, first region SC _1, instead of being connected to a predetermined potential line, the memory cell selection May be connected to the second wiring. It is needless to say that the structure of the semiconductor memory cell illustrated in FIG. 35 can be applied to the structure of the semiconductor memory cell illustrated in FIGS.

The semiconductor memory cell of the fourth embodiment is
Formation of common gate portion (G ₁ + G ₅ ) and fifth region SC
Embodiment 1 is substantially the same as Embodiment 1 except that the formation of ₅ is different.
Since the semiconductor memory cell can be manufactured by the method for manufacturing a semiconductor memory cell described above, detailed description will be omitted.

(Embodiment 5) Embodiment 5 relates to the present invention.
The semiconductor memory cell according to the fifth aspect of the present invention,
Method for manufacturing semiconductor memory cell according to second aspect of the present invention
About. FIG. 36 shows the principle diagram, and FIG.
As shown in an example of a schematic partial cross-sectional view, Embodiment 5
Semiconductor memory cells have a first conductivity type (eg, n-type).
Read first transistor TR₁And the second guide
A second transformer for writing having an electric shape (for example, p-type)
Jista TR_TwoAnd an electrode having a first conductivity type (for example, n-type).
First junction type transistor TR for current control_ThreeAnd the first guide
Second junction type for current control having electric type (for example, n type)
Transistor TR_FourAnd a second conductivity type (for example, p-type)
Write third transistor TR_FiveConsisting of
You. That is, the semiconductor memory cell of the fifth embodiment is
The semiconductor memory according to the third aspect of the present invention described in the third embodiment.
The structure of the molycell and the structure of the present invention described in Embodiment 4
Combination with the structure of the semiconductor memory cell according to the fourth aspect
The structure has That is, the half according to the second aspect of the present invention.
A semiconductive or conductive sixth structure is added to the structure of the conductive memory cell.
Area SC₆Is further formed, the current control having the first conductivity type.
Your second junction transistor TR_FourIs added and
Has a third transistor for writing having a second conductivity type.
Star TR _FiveIs added.

In the semiconductor memory cell of the fifth embodiment shown in FIG. 37A, the arrangement relationship between the common gate portion (G ₁ + G ₅ ) and the gate portion G ₂ of the second transistor TR ₂ is as follows.
It is slightly displaced in the vertical direction. Further, the semiconductor memory cell has a so-called SOI structure formed by being surrounded by an insulating layer formed over a supporting substrate. In the semiconductor memory cell according to the fifth embodiment shown in FIG. 37A, the support substrate, the insulating layer, the second transistor T
The gate portion G ₂ of R _2, are arranged in order of the common gate portion (G ₁ + G _5).

Then, in the semiconductor memory cell of the fifth embodiment, the first area SC ₁ , the second area SC ₂ ,
The arrangement of the region SC ₃ , the fourth region SC ₄ , the fifth region SC _5, and the sixth region SC ₆ is the same as that of the semiconductor memory cell of the third embodiment.

Further, the structures of the first transistor TR ₁ , the second transistor TR ₂ , the first junction transistor TR ₃ and the second junction transistor TR ₄ are also the same as those of the semiconductor memory described in the third embodiment. It has the same structure as the cell. The semiconductor memory cell of the fifth embodiment is different from the semiconductor memory cell of the third embodiment.
The difference from the first embodiment is that the first region SC ₁ and the fourth region SC ₄ , and the second region SC ₂ and the fifth region SC ₄ are formed on the barrier layer formed on the first main surface A ₁ . The first transistor TR ₁ and the third transistor TR ₁ are provided so as to bridge the area SC ₅ of FIG.
(G ₁ + G ₅ ) common to transistor TR ₅
Is formed. Also, the region SC ₅ of the 5 also differs that is not connected to the second predetermined potential line.

[0105] With respect to the third transistor TR _5, in the same manner as described in the fourth embodiment, (E-1) one source / drain region of the channel forming region CH ₁ of the first transistor TR ₁ is configured, (E-2) the other source / drain region, and a fifth region SC _5, (E-3) a channel forming region CH _5, the first other source / drain of the transistor TR ₁ It consists of an area.

The junction transistor TR for current control
_Three, TR_FourRepresents the gate region (the fifth region SC)_Five
And the fifth area SC_FiveIn the second area SC facing_Twoof
Part and the sixth area SC₆And the sixth region S
C₆3rd area SC facing to _Three) Distance (channel
Area CH_Three, CH_FourThickness) and facing each other
Each gate region (fifth region SC_FiveAnd this
5 area SC_FiveIn the second area SC facing_TwoPart, row
In the sixth area SC₆And the sixth area SC₆Facing
Third area SC_ThreeConcentration and channel area in)
Area CH_Three, CH_Four(Fourth area SC_FourAnd the first area S
C₁By optimizing the impurity concentration in
It is formed.

The common gate (G ₁ + G ₅ ) and the gate G ₂ of the second transistor TR ₂ are connected to a first wiring (for example, a word line) for selecting a memory cell. The third region SC ₃ is connected to a write information setting line, the other source / drain region of the second junction transistor TR ₄ is connected to a predetermined potential line, and the _third junction SC ₃ is connected to a predetermined potential line. the other source / drain region is connected to a second wiring for the selected memory cell (e.g. bit line), a region SC ₆ of the sixth is connected to the second predetermined potential line.

FIGS. 37B and 38 are schematic partial cross-sectional views of a modification of the semiconductor memory cell of the fifth embodiment.
(A) and (B). In the example shown in FIG. 37B, unlike the example shown in FIG. 37A, the arrangement relationship between the common gate portion (G ₁ + G ₅ ) and the gate portion G ₂ of the second transistor TR ₂ is different. , In the vertical direction. With such a structure, the area of the semiconductor memory cell can be reduced. In the semiconductor memory cell shown in (A) and (B) in FIG. 38, from the bottom, the supporting substrate, an insulating layer, a common gate unit (G ₁ + G _5), the order of the gate portion G ₂ of the second transistor TR ₂ Are located.
The vertical positional relationship of each region is opposite to the vertical positional relationship of each region in the semiconductor memory cell shown in FIG. In the example shown in FIG.
(A), the common gate portion (G ₁ +
G ₅ ) and the gate portion G ₂ of the second transistor TR ₂ are substantially aligned in the vertical direction.

Alternatively, the semiconductor according to the fifth embodiment
FIG. 39 shows a principle diagram of the memory cell,
As shown in FIG.
Transistor TR_ThreeThe other source / drain region of
Instead of being connected to the second wiring for recell selection,
And the second junction transistor TR _Four
The other source / drain region is connected to a predetermined potential line
Instead, a second wiring for selecting a memory cell (for example,
(For example, bit line).
You. The structure of such a semiconductor memory cell is shown in FIGS.
Application to the structure of the semiconductor memory cell shown in FIG.
It goes without saying that you can do it.

FIGS. 42 to 45 are schematic partial cross-sectional views of a further modification of the semiconductor memory cell of the fifth embodiment.
FIG. 41 shows the principle diagram. In this semiconductor memory cell, unlike the semiconductor memory cell shown in FIG. 37A, the sixth region SC ₆ is connected to a write information setting line instead of being connected to a second predetermined potential line. Have been.
Note that is connected to the write information setting line is equivalent if it is connected to the third region SC _3. Note that FIG.
(A), (B), and (A), (B) of FIG. 43 are basically shown in (A), (B) of FIG. 37, respectively. The structure of the semiconductor memory cell shown in each of FIGS. 44 (A) and (B) and FIGS. 45 (A) and (B) is basically the same as that of the semiconductor memory cell shown in FIG. 38 (A), (B)
Since the structure is the same as that of each of the semiconductor memory cells shown in FIGS. As shown in FIG. 46 showing a principle diagram and FIG. 47 showing a schematic partial cross-sectional view,
The other source / drain region of the first junction type transistor TR _3, instead of connecting the second wiring for memory cell selection, and connected to a predetermined potential line, the other of the second junction type transistor TR ₄ May be connected to a second wiring (for example, a bit line) for selecting a memory cell, instead of connecting the source / drain region of FIG.
The structure of the semiconductor memory cell shown in FIG.
Needless to say, the present invention can be applied to the structure of the semiconductor memory cell shown in FIGS.

The semiconductor memory cell of the fifth embodiment is
Except that the formation of the common gate portion (G ₁ + G ₅ ) and the formation of the fifth region SC ₅ and the sixth region SC ₆ are different.
Since the semiconductor memory cell can be manufactured substantially by the method for manufacturing a semiconductor memory cell described in the first embodiment, detailed description will be omitted.

The operation of the semiconductor memory cells according to the first to fifth embodiments will be described below. The operation principle of the semiconductor memory cells according to the first to fifth embodiments is substantially the same.

At the time of writing, the potential at each part is as shown in Table 1 below.

[0114]

[Table 1] First wiring for memory cell selection: V _W write information setting line When writing "0": V _{0 When} writing "1": V ₁

At the time of reading, the potential at each part is set as shown in Table 2 below. At the time of reading, the potential of the second wiring for selecting a memory cell is as shown in Table 2 below.
The wiring first region SC ₁ or fourth region SC ₄ is connected are given predetermined potential including zero potential.

[0116]

[Table 2] First wiring for memory cell selection: V _R Second wiring for memory cell selection: V ₂

[0117] During reading, it is as the first transistor TR ₁ of threshold value table 3 below as viewed from the gate portion. Also, setting the potential of the relationship in the first transistor TR ₁ as shown in Table 3 below. Note that "0"
When reading and, in the time of reading of "1", the potential of the channel formation region CH ₁ is different. In response to this,
"When reading, and," 0 during the read 1 ", the first threshold value of the transistor TR ₁ as viewed from the gate portion G ₁ is changed. However, it sized to conventional DRAM requires No capacitors are required.
Note that when the on / off current ratio of the junction transistor TR ₃ is _{large, | V R | ≧ | V} TH_11 | But no erroneous reading, can be read.

[0118]

[Table 3] When "0" is read: V _{TH_10 When} "1" is read: V _{TH_11} | V _{TH_11} |> | V _R |> | V _{TH_10} |

[Writing of Information] At the time of writing information of "0" (potential of the write information setting line: V ₀ ) or "1" (potential of the write information setting line: V ₁ ), the potential of the first wiring Is V _W (<0). As a result, the potential of the gate portion G ₂ of the second transistor TR ₂ is also V _W (<0). Accordingly, the second transistor TR ₂ is turned on.
Therefore, the potential of the channel formation region CH ₁ of the first transistor TR ₁ is V ₀ (for information of “0”) or V ₁ (for information of “1”. | V _W | <| V ₁ + V _TH2
In the case of |, V _W -V _TH2 ).

After information is written and in an information holding state before reading, the potential of each portion of each transistor is set so that the first transistor TR ₁ and the second transistor TR ₂ do not conduct. For this purpose, for example, the potential of the first wiring may be set to 0 (V) and the potential of the write information setting line may be set to V ₁ .

When writing information, the first transistor T
R₁Gate G of₁Is V_W(<0). Follow
And the first transistor TR₁Is off. like this
When writing “0” or “1” information, the first trigger
Transistor TR₁Channel forming region CH₁Is V
₀(In case of "0" information) or V₁Or V_W-V
_TH2(In the case of information of “1”), and this state
Until reading, the leakage current (the first transistor TR₁
Channel forming region CH₁And, for example, between semiconductor substrates, the second
Transistor TR_TwoChanges over time due to
However, it is kept within an allowable range. Note that the first transition
Star TR₁Channel forming region CH₁Change of the potential of
Before the read operation becomes large enough to give an error,
Perform a fresh operation.

[Reading Information] When reading "0" or "1" information, the potential of the first wiring is V _R (> 0). As a result, the potential of the gate of the second transistor TR ₂ is V _R (> 0), and the second transistor TR ₂
Is off.

The potential of the gate portion G ₁ of the first transistor TR ₁ is V _R (> 0). Further, the threshold value of the first transistor TR ₁ as viewed from the gate portion is V
_{TH_10} or V _{TH_11} . This first transistor TR
₁ of threshold value depends on the state of the potential channel formation region CH _1. Between these _{potential, | V TH_11 |> | V} R |> | V TH_10 | relationship that. Therefore, when the stored information is "0", the first transistor TR ₁ is turned on. Also, if the stored information is "1", the first transistor TR ₁ is turned off. However, if the on / off current ratio of the junction transistor TR ₃ is large, | V _R | ≧
| V _TH — ₁₁ | can be read without erroneous reading.

Furthermore, the third region SC ₃ and the fifth region S 3 forming the gate region of the junction transistor TR ₃
C ₅ or the first transistor TR based on the bias condition for the second region SC ₂ and the fifth region SC ₅ .
₁ is controlled by the junction transistor TR _3. That is, when the stored information is “0”, the junction transistor TR ₃ is turned on, and when the stored information is “1”, the junction transistor TR ₃ is turned off.

In this way, depending on the stored information, the first
Transistor TR₁Is on or off
Becomes Fourth area SC_FourAlternatively, the first area SC₁Hame
Connected to the second wiring (for example, bit line) for selecting the memory cell
The stored information ("0" or "0")
1 ″) depending on the first transistor TR₁Current
Flow or not. In this way, the accumulated information
First transistor TR ₁Can be read by
You.

The first transistor T described above
Table 4 summarizes the operation states of R ₁ , the second transistor TR _2, and the junction transistor TR ₃ . In Table 4, the value of each potential is an example, and any value may be used as long as the value satisfies the above condition.

[0127]

[Table 4]

Although the semiconductor memory cell of the present invention has been described based on the preferred embodiments of the present invention, the present invention is not limited to these embodiments. The structure of the semiconductor memory cell and the numerical values of the voltage, the potential, and the like described in the embodiments of the invention are merely examples, and can be changed as appropriate. Further, for example, in the semiconductor memory cell of the present invention described in each embodiment of the present invention, the first transistor TR ₁ for reading and the junction type transistor T for current control are used.
R ₃ and TR ₄ are p-type transistors, and the second
A third transistor TR ₅ of the transistor TR ₂ and for writing may be n-type transistors. The arrangement of each element in each transistor is an example, and can be changed as appropriate. The introduction of impurities into various regions can be performed not only by the ion implantation method but also by a diffusion method. In addition, not only a silicon semiconductor but also GaAs
The present invention can be applied to a memory cell composed of an s-based compound semiconductor or the like.

In the method of manufacturing a semiconductor memory cell described in the embodiment of the present invention, a projection is formed on a semiconductor substrate, an insulator (insulating layer) is formed over the entire surface, and then the insulator (insulating layer) is formed. ) And a supporting substrate, and then a semiconductor memory cell having a so-called SOI structure was manufactured based on a so-called bonded substrate obtained by grinding and polishing the semiconductor substrate from the back surface. A semiconductor memory cell having a TFT structure can also be manufactured. That is, a gate portion is formed on an insulator (insulating layer), and then, for example, an amorphous silicon layer or a polysilicon layer is formed over the entire surface by a CVD method or the like.
Zone melting crystallization using a laser beam or electron beam,
A silicon layer is formed by various known single crystallization techniques such as a lateral solid crystal growth method for growing a crystal through an opening provided in an insulator (insulating layer), and the silicon layer is used as a semiconductor layer. A memory cell can also be manufactured. Alternatively, after a gate portion is formed on a supporting substrate, a polysilicon layer or an amorphous silicon layer is formed on the entire surface, and then a semiconductor memory cell is manufactured by using the polysilicon layer or the amorphous silicon layer as a semiconductor layer. be able to.

[0130]

According to the semiconductor memory cell of the present invention,
The operation of the first transistor for reading is defined depending on the potential or charge (information) accumulated in the channel formation region of the first transistor for reading, and the current of the transistor read within the refresh time is defined. Even if the information is additionally added, the information does not depend on the size of the capacitor capacity (for example, the capacity of the gate unit + the additional capacity). Therefore, the problem of the capacitance of the conventional semiconductor memory cell can be solved. Even if an additional capacitor is added for adjusting the refresh time, an extremely large capacitor like the conventional DRAM is required. do not do. The maximum area of the semiconductor memory cell is equal to or smaller than the area of the two transistors.

Furthermore, a junction type transistor for current control is provided, and this junction type transistor for current control is turned on / off at the time of reading information.
As a result, the margin of the current flowing through the second region to the third region can be made very large, so that the number of semiconductor memory cells connected to the bit lines is hardly limited, and the information retention time (retention time) of the semiconductor memory cells is reduced. ) Can be longer.

In the semiconductor memory cell according to the fifth aspect of the present invention, the gate portion has a structure extending to the end of the surface region of the fourth region, and the fifth region is formed in a self-aligned manner. Therefore, the area of the semiconductor memory cell can be further reduced.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a semiconductor memory cell according to a first embodiment of the present invention.

FIG. 2 is a schematic partial cross-sectional view of the semiconductor memory cell according to the first embodiment of the present invention;

FIG. 3 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the first embodiment of the present invention;

FIG. 4 is a schematic partial sectional view of a modification of the semiconductor memory cell according to the first embodiment of the present invention;

FIG. 5 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the first embodiment of the present invention;

FIG. 6 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the first embodiment of the present invention;

FIG. 7 is a schematic partial sectional view of a modification of the semiconductor memory cell according to the first embodiment of the present invention;

FIG. 8 is a principle diagram of a modification of the semiconductor memory cell according to the first embodiment of the present invention.

FIG. 9 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the first embodiment of the present invention;

FIG. 10 is a principle diagram of a semiconductor memory cell according to a second embodiment of the present invention.

FIG. 11 is a schematic partial cross-sectional view of a semiconductor memory cell according to a second embodiment of the present invention.

FIG. 12 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the second embodiment;

FIG. 13 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the second embodiment of the present invention;

FIG. 14 is a schematic layout diagram of a gate portion and each region in a semiconductor memory cell and a modification thereof according to the second embodiment of the invention;

FIG. 15 is a schematic partial sectional view of a modification of the semiconductor memory cell according to the second embodiment of the present invention;

FIG. 16 is a principle diagram of a modification of the semiconductor memory cell according to the second embodiment of the present invention.

FIG. 17 is a schematic partial sectional view of a modification of the semiconductor memory cell according to the second embodiment of the present invention;

FIG. 18 is a principle diagram of a semiconductor memory cell according to a third embodiment of the present invention.

FIG. 19 is a schematic partial cross-sectional view of a semiconductor memory cell according to a third embodiment of the present invention.

FIG. 20 is a schematic partial sectional view of a modification of the semiconductor memory cell according to the third embodiment of the present invention;

FIG. 21 is a principle diagram of a modification of the semiconductor memory cell according to the third embodiment of the present invention.

FIG. 22 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the third embodiment of the present invention.

FIG. 23 is a principle diagram of a modification of the semiconductor memory cell according to the third embodiment of the present invention.

FIG. 24 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the third embodiment of the present invention.

FIG. 25 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the third embodiment of the present invention.

FIG. 26 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the third embodiment of the present invention.

FIG. 27 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the third embodiment of the present invention.

FIG. 28 is a principle diagram of a modification of the semiconductor memory cell according to the third embodiment of the present invention.

FIG. 29 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to Embodiment 3 of the present invention;

FIG. 30 is a principle diagram of a semiconductor memory cell according to a fourth embodiment of the present invention.

FIG. 31 is a schematic partial cross-sectional view of a semiconductor memory cell according to Embodiment 4 of the present invention, and a schematic layout diagram of a gate portion and each region.

FIG. 32 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to Embodiment 4 of the present invention;

FIG. 33 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to Embodiment 4 of the present invention;

FIG. 34 is a principle diagram of a modification of the semiconductor memory cell according to the fourth embodiment of the present invention.

FIG. 35 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell according to the fourth embodiment of the present invention.

FIG. 36 is a view showing the principle of a semiconductor memory cell according to a fifth embodiment of the present invention;

FIG. 37 is a schematic partial cross-sectional view of a semiconductor memory cell according to a fifth embodiment of the present invention.

FIG. 38 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the fifth embodiment.

FIG. 39 is a view showing the principle of modification of the semiconductor memory cell according to the fifth embodiment of the present invention;

FIG. 40 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the fifth embodiment.

FIG. 41 is a view showing the principle of modification of the semiconductor memory cell according to the fifth embodiment of the present invention;

FIG. 42 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the fifth embodiment.

FIG. 43 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the fifth embodiment.

FIG. 44 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the fifth embodiment.

FIG. 45 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the fifth embodiment.

FIG. 46 is a view showing the principle of modification of the semiconductor memory cell according to the fifth embodiment of the present invention;

FIG. 47 is a schematic partial cross-sectional view of a modification of the semiconductor memory cell in the fifth embodiment.

FIG. 48 is a schematic partial cross-sectional view of a support substrate and the like for describing the method for manufacturing the semiconductor memory cell of the first embodiment of the present invention;

FIG. 49 is a schematic partial cross-sectional view of a supporting substrate and the like for illustrating the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 48;

FIG. 50 is a schematic partial cross-sectional view of a supporting substrate and the like for describing the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 49;

FIG. 51 is a schematic partial cross-sectional view of a supporting substrate and the like for explaining the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 50;

FIG. 52 is a schematic partial cross-sectional view of the support substrate and the like for illustrating the method for manufacturing the semiconductor memory cell of the first embodiment of the invention, following FIG. 51;

FIG. 53 is a conceptual diagram of a conventional one-transistor memory cell.

FIG. 54 is a cross-sectional view of a memory cell having a conventional trench capacitor cell structure.

[Explanation of symbols]

TR ₁ · · · first transistor, TR ₂ · · · second transistor, TR _3, TR ₃ · · · junction transistor,
TR ₅ ··· third transistor, SC ₁ ··· first region, SC ₂ ··· second area, SC ₃ ··· third of the area,
SC4: _fourth area, SC5: _fifth area, SC
₆ ... sixth region, CH ₁ , CH ₂ , CH ₅ ... channel forming region, CH ₃ , CH ₄ ... channel region, G ₁ ,
G ₂ , G ₅ ... Gate part, A ₁ .. first main surface, A _2.
..Second principal surface, 10... Silicon semiconductor substrate, 10
A: semiconductor layer, 11, 14: silicon oxide film,
12 ... insulating layer, 12A ... bottom of insulating layer, 13
..Support substrates, 20, 21, 22, 23... Resist

Claims (20)

[Claims] A first transistor having a first conductivity type for reading and a second transistor for writing having a second conductivity type, comprising: a semiconductor layer having first and second opposed two main surfaces; And a junction type transistor for current control having a first conductivity type, and (a) a first conductivity type provided on the semiconductor layer from the first main surface to the second main surface. (B) a semiconductor region having a second conductivity type provided in the semiconductor layer from the first main surface to the second main surface and in contact with the first region; A second region, (c) a semiconductor which is provided on the surface region including the second main surface of the first region so as to be separated from the second region and which is in contact with the first region by forming a rectifying junction. (D) a surface region including the first main surface of the second region, separated from the first region; A semiconductor- or conductive fourth conductive region that is provided in contact with the second region by forming a rectifying junction, and (e) a second conductive region formed on the surface region including the first main surface of the first region. A fifth region which is provided apart from the first region and is in contact with the first region by forming a rectifying junction, and (f) a barrier layer formed on the first main surface. A gate portion of the first transistor provided so as to bridge the first region and the fourth region; and (g) a second region on the barrier layer formed on the second main surface. A semiconductor memory cell having a gate portion of a second transistor provided so as to bridge the third region, wherein (A-1) one source / drain region of the first transistor is a first region (A-2) the other surface of the first transistor. Over scan / drain regions, and a fourth region, (A-3) a channel forming region of the first transistor,
(B-1) the first region includes a surface region including the first main surface of the second region and sandwiched between the surface region including the first main surface of the first region and the fourth region; (B-2) The other source / drain region of the second transistor includes a second main surface of the second region. (B-3) a channel formation region of the second transistor,
(C-1) bonding comprising a surface region including the second main surface of the first region, sandwiched between the third region and the surface region including the second main surface of the second region; The gate region of the transistor is composed of a fifth region and a third region facing the fifth region. (C-2) The channel region of the junction transistor is the fifth region.
And (C-3) one source / drain region of the junction transistor extends from one end of the channel region of the junction transistor, And (C-4) the other source / drain region of the junction transistor, which comprises one source / drain region of the first transistor and a first region forming a channel formation region of the second transistor. Comprises a first region extending from the other end of the channel region of the junction transistor, and (D) a gate portion of the first transistor and a gate portion of the second transistor are provided with a first portion for selecting a memory cell. (E) a third region is connected to a write information setting line, (F) a fourth region is connected to a second line for selecting a memory cell, and (G) The other source / drain region of the case-type transistor is connected to a predetermined potential line, (H) the fifth region, the semiconductor memory cell, characterized by being connected to a second predetermined potential line. 2. The semiconductor memory cell according to claim 1, wherein the fifth region is connected to a write information setting line instead of being connected to a second predetermined potential line. 3. The fourth region is connected to a predetermined potential line instead of being connected to a second wiring for selecting a memory cell, and the other source / drain region of the junction transistor is
2. The semiconductor memory cell according to claim 1, wherein the semiconductor memory cell is connected to a second wiring for selecting a memory cell, instead of being connected to a predetermined potential line. 4. The semiconductor memory cell according to claim 3, wherein the fifth region is connected to a write information setting line instead of being connected to a second predetermined potential line. 5. A first transistor for reading having a first conductivity type and a second transistor for writing having a second conductivity type, comprising a semiconductor layer having first and second opposed main surfaces. And a junction type transistor for current control having a first conductivity type, and (a) a first conductivity type provided on the semiconductor layer from the first main surface to the second main surface. (B) a semiconductor region having a second conductivity type provided in the semiconductor layer from the first main surface to the second main surface and in contact with the first region; A second region, (c) a semiconductor which is provided on the surface region including the second main surface of the first region so as to be separated from the second region and which is in contact with the first region by forming a rectifying junction. (D) a surface region including the first main surface of the second region, separated from the first region; A semiconductor or conductive fourth region which is formed in contact with the second region to form a rectifying junction, and (e) is provided in the surface region of the fourth region, and A semiconductor or conductive fifth region which forms and contacts a rectifying junction; (f) is provided on the barrier layer formed on the first main surface so as to bridge the first region and the fourth region. A gate portion of the first transistor, and (g) a gate of the second transistor provided on the barrier layer formed on the second main surface so as to bridge the second region and the third region. (A-1) one of the source / drain regions of the first transistor is constituted by a surface region including the first main surface of the first region; 2) The other source / drain region of the first transistor is formed from the fourth region. Is, (A-3) a channel forming region of the first transistor,
(B-1) the first region includes a surface region including the first main surface of the second region and sandwiched between the surface region including the first main surface of the first region and the fourth region; (B-2) The other source / drain region of the second transistor includes a second main surface of the second region. (B-3) a channel formation region of the second transistor,
(C-1) bonding comprising a surface region including the second main surface of the first region, sandwiched between the third region and the surface region including the second main surface of the second region; The gate region of the transistor is composed of a fifth region and a portion of the second region facing the fifth region. (C-2) The channel region of the junction transistor is the fifth region.
And (C-3) one source / drain region of the junction transistor is connected to one end of a channel region of the junction transistor. And (C-4) the other source / drain region of the junction transistor is formed of a fourth region that extends from the first transistor and constitutes the other source / drain region of the first transistor. (D) the gate portion of the first transistor and the gate portion of the second transistor are connected to a first wiring for selecting a memory cell, (E) the third region is connected to a write information setting line, (F) the first region is connected to a predetermined potential line, and (G) the other source / drain region of the junction transistor is It is connected to the second wiring for Moriseru selection, (H) the fifth region, the semiconductor memory cell, characterized by being connected to a second predetermined potential line. 6. The semiconductor memory cell according to claim 5, wherein the fifth region is connected to the second region instead of being connected to a second predetermined potential line. 7. The other source / drain region of the junction transistor is connected to a predetermined potential line instead of being connected to a second wiring for selecting a memory cell, and the first region is
6. The semiconductor memory cell according to claim 5, wherein the semiconductor memory cell is connected to a second wiring for selecting a memory cell instead of being connected to a predetermined potential line. 8. The semiconductor memory cell according to claim 7, wherein the fifth region is connected to the second region instead of being connected to a second predetermined potential line. 9. A first transistor for reading having a first conductivity type and a second transistor for writing having a second conductivity type, comprising a semiconductor layer having first and second opposed main surfaces. , A first junction type transistor for current control having a first conductivity type, and a second junction type transistor for current control having a first conductivity type.
A semiconductor first region having a first conductivity type, provided in the semiconductor layer from the first main surface to the second main surface;
(B) a second semiconductor region having a second conductivity type provided in the semiconductor layer from the first main surface to the second main surface and in contact with the first region; A surface area including the second main surface of the area is provided separately from the second area; and
A semiconductor or conductive third region which is in contact with the first region by forming a rectifying junction, and (d) a surface region including the first main surface of the second region, separated from the first region. Provided, and
A semiconductor or conductive fourth region that forms and contacts a rectifying junction with the second region, (e) is provided in the surface region of the fourth region, and forms a rectifying junction with the fourth region. A fifth semiconductor or conductive region that is in contact with the first region; A semiconductor or conductive sixth region that forms a junction and is in contact with the semiconductor region, and (g) is provided on the barrier layer formed on the first main surface so as to bridge the first region and the fourth region. A gate portion of the first transistor; and (h) a gate portion of the second transistor provided on the barrier layer formed on the second main surface so as to bridge the second region and the third region. And (A-1) one of the source / drain regions of the first transistor (A-2) The other source / drain region of the first transistor is formed of a fourth region, and (A-3) is formed of a surface region including the first main surface of the first region. The channel formation region of the first transistor is
(B-1) the first region includes a surface region including the first main surface of the second region and sandwiched between the surface region including the first main surface of the first region and the fourth region; (B-2) The other source / drain region of the second transistor includes a second main surface of the second region. (B-3) a channel formation region of the second transistor,
And (C-1) the first region includes a surface region including the second main surface of the first region, sandwiched between the third region and the surface region including the second main surface of the second region. The gate region of the junction transistor 1 is
(C-2) a channel region of the first junction type transistor includes a fifth region and a second region. The fourth part sandwiched between
(C-3) one source / source of the first junction type transistor
The drain region extends from one end of the channel region of the first junction type transistor, and includes a portion of a fourth region forming the other source / drain region of the first transistor; (C-4) The other source of one junction transistor /
The drain region includes a portion of a fourth region extending from the other end of the channel region of the first junction transistor. (D-1) The gate region of the second junction transistor includes:
(D-2) The channel region of the second junction type transistor includes the sixth region and the third region. The sixth region includes a third region opposed to the sixth region. And (D-3) one source / source of the second junction transistor.
The drain region extends from one end of the channel region of the second junction transistor, and extends from one source / drain region of the first transistor and a portion of the first region forming a channel forming region of the second transistor. (D-4) the other source / source of the second junction transistor
The drain region is composed of a portion of a first region extending from the other end of the channel region of the second junction transistor. (E) The gate portion of the first transistor and the gate portion of the second transistor are connected to the memory cell (F) The third region is connected to a write information setting line, and (G) The other source / drain region of the second junction transistor is connected to a predetermined potential line. (H) the other source / drain region of the first junction transistor is connected to a second wiring for selecting a memory cell; and (I) the fifth region and the sixth region are A semiconductor memory cell connected to a predetermined potential line. 10. The other junction / source region of the first junction type transistor is connected to a predetermined potential line instead of being connected to a second wiring for selecting a memory cell. 10. The semiconductor memory cell according to claim 9, wherein the other source / drain region is connected to a second wiring for selecting a memory cell instead of being connected to a predetermined potential line. 11. The fifth region is connected to a second region instead of being connected to a second predetermined potential line, and the sixth region is connected to a second predetermined potential line. 10. The semiconductor memory cell according to claim 9, wherein the semiconductor memory cell is connected to a write information setting line instead. 12. The other junction / transistor region of the first junction transistor is connected to a predetermined potential line instead of being connected to a second wiring for selecting a memory cell. 12. The semiconductor memory cell according to claim 11, wherein the other source / drain region is connected to a second wiring for selecting a memory cell instead of being connected to a predetermined potential line. 13. A first transistor for reading having a first conductivity type and a second transistor for writing having a second conductivity type, comprising a semiconductor layer having first and second opposed main surfaces. , A junction type transistor for controlling current having the first conductivity type, and a third transistor for writing having the second conductivity type. (A) From the first main surface to the second main surface A first region of semiconductor conductivity having a first conductivity type provided in the semiconductor layer over the semiconductor layer; (b) provided in the semiconductor layer from the first main surface to the second main surface; A second semiconductor region having a second conductivity type in contact with the first region, (c) being provided on the surface region including the second main surface of the first region, separated from the second region; And a semiconductor or conductive third region which is in contact with the first region by forming a rectifying junction; A semiconductor or conductive fourth region which is provided at a distance from the first region in a surface region including the first main surface of the region, and is in contact with the second region by forming a rectifying junction; (E) a semiconductor or conductive fifth region which is provided on the surface region of the fourth region and is in contact with the fourth region by forming a rectifying junction; (f) formed on the first main surface A gate portion common to the first transistor and the third transistor provided on the barrier layer so as to bridge the first region and the fourth region, and the second region and the fifth region; (G) a semiconductor memory cell having a gate portion of a second transistor provided on a barrier layer formed on the second main surface so as to bridge the second region and the third region. (A-1) One source / drain region of the first transistor is the first region of the first region. (A-2) the other source / drain region of the first transistor is composed of a fourth region; (A-3) the channel formation region of the first transistor is ,
(B-1) the first region includes a surface region including the first main surface of the second region and sandwiched between the surface region including the first main surface of the first region and the fourth region; (B-2) The other source / drain region of the second transistor includes a second main surface of the second region. (B-3) a channel formation region of the second transistor,
(C-1) bonding comprising a surface region including the second main surface of the first region, sandwiched between the third region and the surface region including the second main surface of the second region; The gate region of the transistor is composed of a fifth region and a portion of the second region facing the fifth region. (C-2) The channel region of the junction transistor is the fifth region.
And (C-3) one source / drain region of the junction transistor is connected to one end of a channel region of the junction transistor. And (C-4) the other source / drain region of the junction transistor is formed of a fourth region that extends from the first transistor and constitutes the other source / drain region of the first transistor. (D-1) one of the source / drain regions of the third transistor is formed of a channel formation region of the first transistor, and (D-1) 2) The other source / drain region of the third transistor is composed of a fifth region. (D-3) The channel formation region of the third transistor is
And (E) a gate portion common to the first transistor and the third transistor and a gate portion of the second transistor, the first transistor and the third transistor having a gate portion for selecting a memory cell. (F) the third region is connected to a write information setting line, (G) the first region is connected to a predetermined potential line, and (H) the other source / drain of the junction transistor. A semiconductor memory cell, wherein the region is connected to a second wiring for selecting a memory cell. 14. The other source / drain region of the junction transistor is connected to a predetermined potential line instead of being connected to a second wiring for selecting a memory cell, and the first region is connected to a predetermined potential line. 14. The semiconductor memory cell according to claim 13, wherein the semiconductor memory cell is connected to a second wiring for selecting a memory cell instead of being connected to a line. 15. A first transistor for reading having a first conductivity type and a second transistor for writing having a second conductivity type, comprising a semiconductor layer having first and second opposed main surfaces. , A first junction type transistor for current control having a first conductivity type, a second junction type transistor for current control having a first conductivity type, and a second junction type transistor for writing having a second conductivity type. (A) a first semiconductor region having a first conductivity type provided in the semiconductor layer from the first main surface to the second main surface; A second conductive semiconductor region having a second conductivity type provided in the semiconductor layer from the first main surface to the second main surface and in contact with the first region; (c) a first region of the first region The second region is provided at a surface region including the main surface of the second region and is spaced from the first region. A semiconductor or conductive third region that is in contact with and forms a junction; (d) a third region provided on the surface region including the first main surface of the second region, separated from the first region; A semiconductor or conductive fourth region that forms a rectifying junction with the second region, and (e) is provided in the surface region of the fourth region and forms a rectifying junction with the fourth region to make contact with the fourth region. (F) a fifth region which is semiconductive or conductive; (f) is provided at a surface region including the first main surface of the first region, away from the second region, and is rectifying junction with the first region. Forming a semiconductor or conductive sixth region, and (g) forming a first region and a fourth region, and a second region and a second region on a barrier layer formed on the first main surface. A gate portion common to the first transistor and the third transistor provided so as to bridge the region of No. 5, and (h) a second main surface A semiconductor memory cell having a gate portion of a second transistor provided so as to bridge the second region and the third region on the barrier layer formed in (A-1). One source / drain region of the transistor includes a surface region including a first main surface of the first region; (A-2) the other source / drain region of the first transistor includes a fourth region (A-3) The channel formation region of the first transistor is:
(B-1) the first region includes a surface region including the first main surface of the second region and sandwiched between the surface region including the first main surface of the first region and the fourth region; (B-2) The other source / drain region of the second transistor includes a second main surface of the second region. (B-3) a channel formation region of the second transistor,
And (C-1) the first region includes a surface region including the second main surface of the first region, sandwiched between the third region and the surface region including the second main surface of the second region. The gate region of the junction transistor 1 is
(C-2) a channel region of the first junction type transistor includes a fifth region and a second region. The fourth part sandwiched between
(C-3) one source / source of the first junction type transistor
The drain region extends from one end of the channel region of the first junction type transistor, and includes a portion of a fourth region forming the other source / drain region of the first transistor; (C-4) The other source of one junction transistor /
The drain region includes a portion of a fourth region extending from the other end of the channel region of the first junction transistor. (D-1) The gate region of the second junction transistor includes:
(D-2) The channel region of the second junction type transistor includes the sixth region and the third region. The sixth region includes a third region opposed to the sixth region. And (D-3) one source / source of the second junction transistor.
The drain region extends from one end of the channel region of the second junction transistor, and extends from one source / drain region of the first transistor and a portion of the first region forming a channel forming region of the second transistor. (D-4) the other source / source of the second junction transistor
The drain region is composed of a portion of a first region extending from the other end of the channel region of the second junction transistor. (E-1) One source / drain region of the third transistor is a first transistor (E-2) the other source / drain region of the third transistor is composed of a fifth region, and (E-3) the channel formation region of the third transistor is
(F) a gate portion common to the first transistor and the third transistor and a gate portion of the second transistor are formed by the first source / drain region of the first transistor and the third transistor. (G) the third region is connected to a write information setting line; (H) the other source / drain region of the second junction transistor is connected to a predetermined potential line; ) The other source / drain region of the first junction transistor is connected to a second wiring for selecting a memory cell, and (J) the sixth region is connected to a second predetermined potential line. A semiconductor memory cell characterized by the above-mentioned. 16. The other junction / transistor region of the first junction transistor is connected to a predetermined potential line instead of being connected to a second wiring for selecting a memory cell. 16. The semiconductor memory cell according to claim 15, wherein the other source / drain region is connected to a second wiring for selecting a memory cell, instead of being connected to a predetermined potential line. 17. The semiconductor memory cell according to claim 16, wherein the sixth region is connected to a write information setting line instead of being connected to a second predetermined potential line. 18. The second junction type transistor, wherein the other source / drain region of the first junction type transistor is connected to a predetermined potential line instead of being connected to a second wiring for selecting a memory cell. 18. The semiconductor memory cell according to claim 17, wherein the other source / drain region is connected to a second wiring for selecting a memory cell instead of being connected to a predetermined potential line. 19. A first transistor for reading having a first conductivity type and a second transistor for writing having a second conductivity type, comprising a semiconductor layer having first and second opposed main surfaces. And a junction type transistor for current control having a first conductivity type, and (a) a first conductivity type provided on the semiconductor layer from the first main surface to the second main surface. (B) a semiconductor region having a second conductivity type provided in the semiconductor layer from the first main surface to the second main surface and in contact with the first region; A second region, (c) a semiconductor which is provided on the surface region including the second main surface of the first region so as to be separated from the second region and which is in contact with the first region by forming a rectifying junction. (D) a surface region including the first main surface of the second region, separated from the first region; A semiconductor or conductive fourth region which is provided as a rectifying junction and is in contact with the second region; (e) a second region is provided on the surface region including the first main surface of the first region. A fifth region which is provided apart from the first region and is in contact with the first region by forming a rectifying junction, and (f) a barrier layer formed on the first main surface. A gate portion of the first transistor provided so as to bridge the first region and the fourth region; and (g) a second region on the barrier layer formed on the second main surface. A gate portion of the second transistor provided so as to bridge the third region, and (A-1) one source / source formed from a surface region including the first main surface of the first region. (A-2) the other source / drain region composed of the fourth region; (A-3) the first region A first transistor including a channel forming region including a surface region including the first main surface of the second region, sandwiched between the surface region including the first main surface and a fourth region; (B-1) one source / drain region composed of a third region; (B-2) another source / drain region composed of a surface region including a second main surface of the second region; B-3) Channel formation including a surface region including the second main surface of the first region, sandwiched between the third region and the surface region including the second main surface of the second region. A second transistor having a region, (C-1) a fifth region, and a gate region including a third region facing the fifth region; and (C-2) a fifth region. (C-3) a junction-type channel formed of a portion of the first region sandwiched by the third region; One source / drain region extending from one end of the channel region of the transistor and including a portion of the first region forming one source / drain region of the first transistor and a channel forming region of the second transistor (C-4) a method of manufacturing a semiconductor memory cell comprising: a junction transistor having the other source / drain region formed by a portion of the first region extending from the other end of the channel region of the junction transistor. (A) after forming a barrier layer on the surface of the first main surface, forming a gate portion of the first transistor on the barrier layer, and forming a barrier layer on the surface of the second main surface Forming a gate portion of a second transistor on the barrier layer, and (b) optimizing a distance between opposing gate regions of the junction transistor; and First, the first impurity concentration in the opposing gate region and the impurity concentration in the channel region of the junction transistor are optimized.
Forming the third region, the third region, and the fifth region in an arbitrary order by an ion implantation method. 20. A semiconductor device having a semiconductor layer having first and second opposed two main surfaces, at least a first transistor for reading having a first conductivity type and a writing transistor having a second conductivity type. A second transistor and a junction type transistor for current control having a first conductivity type; and (a) a first transistor provided on the semiconductor layer from the first main surface to the second main surface. (B) a semiconductor having a second conductivity type provided in the semiconductor layer from the first main surface to the second main surface and in contact with the first region; (C) a surface region including the second main surface of the first region, which is provided separately from the second region, and forms a rectifying junction with the first region. (D) a first region in the surface region including the first main surface of the second region; A semiconductor or conductive fourth region that is provided apart from the region and that is in contact with the second region by forming a rectifying junction; (e) provided in the surface region of the fourth region; A semiconductor or conductive fifth region which is in contact with the fourth region by forming a rectifying junction; (f) forming the first region and the fourth region on the barrier layer formed on the first main surface; A gate portion of the first transistor provided so as to bridge, and (g) a second portion provided on the barrier layer formed on the second main surface so as to bridge the second region and the third region. (A-1) one source / drain region composed of a surface region including the first main surface of the first region; and (A-2) a fourth gate portion of the first region. The other source / drain region constituted by the region, (A-3) including the first main surface of the first region A first transistor having a channel formation region including a surface region including the first main surface of the second region, sandwiched between the surface region and the fourth region; (B-1) a third transistor (B-2) the other source / drain region composed of a surface region including the second main surface of the second region; and (B-3) the third source / drain region composed of a surface region including the second main surface of the second region. A second channel formation region including a surface region including the second main surface of the first region, sandwiched between the region and the surface region including the second main surface of the second region; A transistor; (C-1) a fifth region; and a gate region including a portion of a second region opposed to the fifth region. (C-2) a fifth region and a second region. (C-3) a junction region composed of a portion of a fourth region sandwiched by the portion; One source / drain region extending from one end of the channel region of the transistor and comprising a portion of a fourth region constituting the other source / drain region of the first transistor; (C-4) a junction transistor A junction type transistor having the other source / drain region composed of a portion of a fourth region extending from the other end of the channel region, wherein: After a barrier layer is formed on the surface of the first main surface, a gate portion of the first transistor is formed on the barrier layer, and a barrier layer is formed on the surface of the second main surface. (B) forming a gate portion of the second transistor; and (b) optimizing a distance between opposing gate regions of the junction transistor, and The second impurity concentration is optimized so that the impurity concentration in each gate region and the impurity concentration in the channel region are optimized.
Forming each of the region, the fourth region, and the fifth region in an arbitrary order by an ion implantation method.