JPH11203872A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor storage device which reduces a margin when designing a timing of an internal control signal and operates at high speed. SOLUTION: By providing a memory cell selection detecting circuit 14 for detecting that a word line has been driven; providing a sense amplifier final output detecting circuit 15 for detecting that an output of the sense amplifier 10 is fixed, which reads the data of the memory cell; providing a reset circuit 16 for resetting a series of operations; and latching read-out data of the memory cell in an output data latch circuit 12 according to the output of the sense amplifier final output detecting circuit 15, the reset circuit 16 is operated by the output of the memory cell selection detecting circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device capable of high-speed operation.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have become larger and larger due to advances in microfabrication technology, and with the speeding up of systems, semiconductor memory devices have also been required to have higher speeds. In a conventional semiconductor memory device, the timing of an internal control signal such as a pulse width of a word line, a delay time from when a word line is opened to when a sense amplifier operates, and a timing for latching output data are adjusted by an inverter delay. .

Here, the relationship between the pulse width of a word line and the read speed of a memory will be briefly described. In the operation of the memory, a cycle time is defined by a period in which a word line is opened to read data from a memory cell, or a period in which data is written to a memory cell (pulse width of a word line), and a period in which a bit line is precharged. Therefore, by minimizing the pulse width of the word line to a necessary minimum, the memory operation can be performed at high speed.

Hereinafter, a conventional semiconductor memory device will be described.
This will be described with reference to the drawings. FIG. 5 is a block diagram showing a configuration of a conventional semiconductor memory device. In FIG. 5, 1
Is an address input terminal for inputting an external address AD. Reference numeral 2 denotes an address buffer for receiving an external address AD. Reference numeral 3 denotes a clock input terminal for inputting an external clock signal CLK. Reference numeral 4 denotes a pulse generation circuit that generates a pulse in response to the rising of the external clock signal CLK. Reference numeral 5 denotes an inverter delay circuit for setting the pulse width of the pulse generation circuit 4, and the pulse width of the word line is determined by this time.

A row address decoder 6 decodes an address fetched by the address buffer 2 and drives a word line WL for selecting a part of memory cells in a memory cell array 7 in response to an external clock signal CLK. , And operates using the output WLE2 of the pulse generation circuit 4 as a control signal. The row address decoder 6 has a built-in word line driver (not shown) for selecting a part of the memory cell array 7 in response to a logical product of a row address decode output and an external clock signal CLK.

Reference numeral 8 denotes a column address decoder for decoding an address taken into the address buffer 2.
Reference numeral 9 denotes a column selector for selecting data of one more memory cell from a plurality of memory cells selected by the word line WL, and receives an output of the column address decoder 8. Reference numeral 10 denotes a sense amplifier that reads data from a memory cell.

Reference numeral 11 denotes an inverter delay circuit for setting a delay time from when the word line WL is driven to when the sense amplifier 10 is operated, an input of which is an output WLE2 of the pulse generation circuit 4 and an output of which is a sense amplifier. 1
0 is the control signal SAE3. An output data latch circuit 12 latches the output of the sense amplifier 10. Reference numeral 13 denotes a precharge circuit that precharges the bit line pair BL / NBL when the external clock signal CLK is at a low level (hereinafter, referred to as an L level).

The operation of the semiconductor memory device configured as described above will be described with reference to FIG. FIG. 6 is a timing chart showing a relationship among input signals, memory cell data, and internal control signals of the semiconductor memory device of FIG. First, when the external clock signal CLK rises from the L level to the high level (hereinafter, referred to as the H level), the output WLE2 of the pulse generation circuit 4 goes to the H level (timing A). At the same time, the external address signal AD is taken in by the address buffer 2 and input to the row address decoder 6 (timing B). One word line WL is selected by this signal and the output WLE2 of the pulse generation circuit 4 to go to the H level, a memory cell connected to the word line WL in the memory cell array 7 is selected, and the data of the memory cell is converted into a bit. Line pair BL / NBL (bit line pair D
L / NDL) (timing C).

Further, the control signal SAE of the sense amplifier 10
3, the output of the inverter delay circuit 11 becomes H level after the delay time t2 of the inverter delay circuit 11 after the output WLE2 of the pulse generation circuit 4 becomes H level (timing D), and the sense amplifier 10 operates and the bit The data of the bit line pair DL / NDL selected by the column selector 9 from the line pair BL / NBL is amplified to H
Level / L level (timing E). At this time, the output data latch circuit 12 is in the data through state (timing F).

Further, the delay time t of the inverter delay circuit 5
After 1, the output WLE2 of the pulse generation circuit 4 changes to L level (timing G). As a result, the word line WL becomes L level, and after the delay time t2 of the inverter delay circuit 11, the output of the inverter delay circuit 11, which is the control signal SAE3 of the sense amplifier 10, changes to L level.
The operation of the sense amplifier 10 stops (timing H), and the output data latch circuit 12 enters the data latch state (timing I).

On the other hand, when the external clock signal CLK goes high, the precharge circuit 13 turns off the precharge.
(Timing J), and when the external clock signal CLK goes low, precharging of the bit line pair BL / NBL starts (timing K) and the bit line pair B
L / NBL (see bit line pair DL / NDL) is precharged to H level (timing L).

[0012]

In the above-mentioned conventional configuration,
After the word line is opened and the data of the memory cell is read out to the bit line, the sense amplifier 1 is turned on by the inverter delay circuit 11.
0, the output of the sense amplifier 10 is determined, the time until the data of the memory cell reaches the output data latch circuit 12 is set, and the delay time of the inverter delay circuit 5 is set. Close, that is, the word line pulse width is set. When setting the timing,
The pulse width of the word line must be equal to or longer than the time required for the output data latch circuit 12 to take in the data of the memory cell. If this condition cannot be satisfied, the data in the memory cell cannot be read correctly. As a result, in order to reliably perform the read operation, it is necessary to design the delay time of the internal control signal with a margin. for that reason,
Each margin is accumulated and it is very difficult to operate at high speed.

In order to reduce the chip area, it is desired that the memory capacity of the semiconductor memory device required by the system configuration is variable. To achieve the behavior,
Timing design of internal control signal is required for each capacity,
Timing design is complicated. On the other hand, in order to simplify the timing design, it is only necessary to design the timing according to the maximum capacity. However, in this case, the operation speed of the small-capacity semiconductor memory device is equivalent to that of the large-capacity semiconductor memory device, and the higher speed is achieved. I couldn't.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor memory device capable of removing a timing design margin of an internal control signal and enabling high-speed operation according to a memory capacity. .

[0015]

According to a first aspect of the present invention, there is provided a semiconductor memory device, comprising: a memory cell array for storing data; an address buffer for receiving an external address; an address decoder for decoding the received address;
A word line driver for selecting a part of a memory cell array in response to a logical product of an output of an address decoder and an external clock, and a memory selection detecting means for receiving an output of the word line driver as input and detecting that a memory cell is selected A sense amplifier that operates in response to the output of the memory cell selection detecting means and reads data of the selected memory cell;
Sense amplifier output confirmation detecting means for detecting that the output of the sense amplifier has been confirmed, and output data latch means for receiving the output of the sense amplifier in response to the output of the memory cell selection detecting means and the output of the sense amplifier output confirmation detecting means And reset means for resetting the word line driver in response to the output of the memory cell selection detection means.

According to this configuration, the timing of the internal control signal can be designed by detecting the read data from the word line and the memory cell without using the inverter delay circuit having a margin. In other words, by detecting the operation of the word line, confirming that the word line is open, and then closing the word line, the pulse width of the word line is set to avoid malfunction due to insufficient pulse width of the word line. Thus, an unnecessary margin is added to the delay value of the inverter delay circuit to prevent a problem in high-speed operation. Further, the operation of the word line changes depending on the memory capacity, that is, the number of memory cells connected to the word line, but by detecting the actual operation of the word line,
The required minimum word line pulse width can be set according to each memory capacity, and the speed can be increased. Further, by detecting that the output of the sense amplifier for reading the data of the memory cell has been determined, the read data can be immediately latched, the word line is closed, and the next operation is performed after the precharge is applied. It is possible to cope with shortening of the time required for performing. That is,
The margin added to the word line pulse width setting to avoid malfunctions as in the conventional example can be deleted,
It can be operated at high speed.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising:
A memory cell array for storing data, an address buffer for capturing an external address, an address decoder for decoding the captured address, and a word for selecting a part of the memory cell array in response to a logical product of an output of the address decoder and an external clock A line driver, a dummy word line driver that operates in response to an external clock regardless of the output of the address buffer, and a sense amplifier that operates in response to the output of the dummy word line driver and reads data of a selected memory cell. , Sense amplifier output determination detecting means for detecting that the output of the sense amplifier has been determined, and output data latch means for receiving the output of the sense amplifier in response to the output of the dummy word line driver and the output of the sense amplifier output determination detecting means In response to the dummy word line output. And a reset means for resetting the line driver.

According to this configuration, the timing of the internal control signal is detected without using an inverter delay circuit having a margin, and detecting a dummy word line operating in the same manner as a word line, data read from a memory cell, and the like. Can be performed. In other words, by detecting the operation of the dummy word line, confirming that the word line is open, and closing the word line, the pulse width of the word line is reduced to prevent malfunction due to insufficient pulse width of the word line. An unnecessary margin is added to the delay value of the inverter delay circuit to be set, so that high-speed operation is not hindered.
Furthermore, the operation of the word line changes depending on the memory capacity, that is, the number of memory cells connected to the word line. By detecting the operation of the dummy word line that performs the same operation as the word line, the operation of each memory capacity is increased. The required minimum word line pulse width can be set accordingly, and the speed can be increased. Further, by detecting that the output of the sense amplifier for reading the data of the memory cell has been determined, the read data can be immediately latched, the word line is closed, and the next operation is performed after the precharge is applied. It is possible to cope with shortening of the time required for performing. That is, the margin added to the pulse width setting of the word line in order to avoid malfunction as in the conventional example can be deleted, and high-speed operation can be performed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, reference numeral 14 denotes a memory cell selection detection circuit for detecting that a word line WL has been driven and a memory cell has been selected. In this embodiment, all different word lines WL are connected to their respective gates and their drains are shared. Multiple N-channel Ms connected to nodes and sources connected to power
It is composed of OS transistors.

Reference numeral 15 denotes a sense amplifier output decision detection circuit for detecting that the output of the sense amplifier 10 has been decided, and in this embodiment, is constituted by a two-input exclusive OR circuit. Reference numeral 16 denotes a reset circuit which resets the output signal WLE1 in response to the output of the memory cell selection detection circuit 14. In this embodiment, the reset circuit 16 comprises a D flip-flop with reset. Reference numeral 18 denotes a two-input NOR circuit for calculating the NOR of the output EXOR of the sense amplifier output determination detection circuit 15 and the output RESET1 of the memory cell selection detection circuit 14, and 19 denotes the output RES of the memory cell selection detection circuit 14.
ET1 is inverted to control signal SAE1 of sense amplifier 10.
Is an inverter. In addition, components corresponding to those in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted.

The operation of the semiconductor memory device configured as described above will be described with reference to FIG. FIG. 2 is a timing chart showing a relationship among input signals, memory cell data, and internal control signals of the semiconductor memory device of FIG. First, the external clock signal CLK is changed from L level to H level.
When it rises to the level, the output WLE of the reset circuit 16
1 goes to the H level (timing A), and the output WLE1 goes to the H level, whereby the precharge circuit 13 enters the precharge OFF state (timing J). At the same time, the external address signal AD is taken in by the address buffer 2 and input to the row address decoder 6 (timing B). One word line WL is selected by this signal and the output WLE1 of the reset circuit 16 to go to the H level, the memory cell connected to this word line WL in the memory cell array 7 is selected, and the data of the memory cell is stored in the bit line. The data is read out to the pair BL / NBL (see bit line pair DL / NDL) (timing C). When the word line WL goes high, the memory cell selection detection circuit 1
4 goes low (timing M), the output LATE of the NOR circuit 19, that is, the control signal of the output data latch circuit 12, goes high, and the output data latch circuit 12 enters the data through state ( Timing F). Also, the memory cell selection detection circuit 1
4 is at the L level, the inverter 1 which is the control signal SAE1 of the sense amplifier 10
9 becomes H level (timing D), the sense amplifier 10 operates, and the bit line pair DL / NDL selected by the column selector 9 from the bit line pair BL / NBL.
Are amplified to H level / L level (timing E). When the bit line pair DL / NDL is amplified to H level / L level, the output EXOR of the sense amplifier output confirmation detection circuit 15, that is, the output of the two-input exclusive OR circuit becomes H level (timing O),
This signal and the output RESE of the memory cell selection detection circuit 14
The output LAT of the NOR circuit 18 to which T1 is input
E, that is, the control signal of the output data latch circuit 12 is L
Level, and the output data latch circuit 12 enters the data latch state (timing I).

On the other hand, when the output RESET1 of the memory cell selection detection circuit 14 becomes L level, the output WLE1 of the reset circuit 16 becomes L level (timing G), the word line WL becomes L level, and the precharge circuit 13 The charge is turned on (timing K). As a result, both the bit line pair DL / NDL become H level (timing L), the output RESET1 of the memory cell selection detection circuit 14 also becomes H level (timing N), and the control signal SAE1 of the sense amplifier 10 also becomes L level ( Timing H), external clock signal CLK
Returns to the state before it became the H level.

As described above, according to this embodiment,
A memory cell selection detection circuit 14 for detecting that the word line WL has been driven, a sense amplifier output determination detection circuit 15 for detecting that data of the bit line pair DL / NDL has been read out, By providing the reset circuit 16 which starts resetting the internal operation immediately after the operation, the data of the memory cell is read by the sense amplifier 10 when the operation of the word line WL is detected, and the data of the memory cell is read. When it is detected that the output of the sense amplifier 10 to be read is determined, the output of the sense amplifier 10 is fetched by the output data latch circuit 12, and when the operation of the word line WL is detected, the reset circuit 16 resets the word line driver. As a result, the timing of data reading by the sense amplifier 10 and the So that the timing of the data by the force data latch circuit 12 takes in is automatically set to the optimum state in accordance with the operation state of the word line WL and sense amplifier 10. That is, after confirming that the word line WL is open, the user closes himself immediately, so that it is not necessary to adjust the timing of the internal control signal by the inverter delay circuit, and the pulse width of the word line is insufficient. It is possible to eliminate the timing margin of the inverter delay circuit which has been added in order to avoid malfunction. Further, since the read data is immediately taken into the output data latch circuit 12 immediately after the output of the sense amplifier 10 is determined, it is possible to cope with a short word line pulse width and realize a high-speed operation. Further, when the memory capacity changes, the timing of the internal control signal changes in accordance with a change in the operation time of the word line WL and a change in the time until the output of the sense amplifier 10 is determined. It is possible to operate at high speed according to the capacity.

[Second Embodiment] FIG. 3 shows a second embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment. 3, reference numeral 17 denotes a dummy word line driver that operates regardless of the output of the address buffer 2, and reference numeral 20 denotes an inverter that inverts the output of the dummy word line driver 17, which is a memory cell selection detection circuit of FIG. 14 and an inverter 19 are provided. In addition, components corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

The operation of the semiconductor memory device configured as described above will be described with reference to FIG. FIG. 4 is a timing chart showing a relationship among input signals, memory cell data, and internal control signals of the semiconductor memory device of FIG. First, the external clock signal CLK is changed from L level to H level.
When it rises to the level, the output WLE of the reset circuit 16
1 becomes H level (timing A), and the precharge circuit 13 enters a precharge OFF state (timing J). At the same time, the external address signal AD is taken in by the address buffer 2 and input to the row address decoder 6 (timing B). One word line WL is selected by this signal and the output WLE1 of the reset circuit 16 to be at the H level, and this word line WL in the memory cell array 7 is selected.
Is selected, and the data of the memory cell is stored in the bit line pair BL / NBL (bit line pair DL / N
DL (see DL) (timing C).

Further, the output WLE1 of the reset circuit 16
Goes high, the output DWL of the dummy word line driver 17 goes high (timing P).
When the dummy word line DWL goes high, the inverted signal of the output DWL of the dummy word line driver 17, ie, the output RESET2 of the inverter 20, goes low (timing M), and the output LATE of the NOR circuit 18 outputs A control signal of a certain output data latch circuit 12 becomes H level, and the output data latch circuit 12 enters a data through state (timing F). When the output RESET2 of the inverter 20, which is an inverted signal of the output DWL of the dummy word line driver 17, goes low, the control signal SAE2 of the sense amplifier 10 goes high (timing D), and the sense amplifier 10 operates. The data of the bit line pair DL / NDL selected from the bit line pair BL / NBL by the column selector 9 is amplified to H level / L level (timing E). When the bit line pair DL / NDL is amplified to H level / L level, the output of the two-input exclusive OR circuit, which is the output EXOR of the sense amplifier output confirmation detection circuit 15, becomes H level (timing O), and this signal and The control signal LATE of the output data latch circuit 12, which is the output LATE of the NOR circuit 18 to which the inverted signal RESET2 of the output DWL of the dummy word line driver 17 is input, becomes L level, and the output data latch circuit 12 is in the data latch state. (Timing I).

On the other hand, when the inverted signal RESET2 of the output DWL of the dummy word line driver 17 becomes L level, the output WLE1 of the reset circuit 16 becomes L level (timing G), the word line WL becomes L level, and the dummy word The line DWL goes low (timing Q), the control signal SAE2 of the sense amplifier 10 goes low (timing H), and the dummy word line driver 17
Signal RESET2 of the output DWL becomes H level (timing N), and the precharge circuit 13 enters a precharge ON state (timing K). Thereby, both the bit line pair DL / NDL become H level (timing L), and return to the state before the external clock signal CLK became H level.

As described above, according to this embodiment,
A dummy word line driver 17 that operates independently of an address input, and a sense amplifier output determination detection circuit 1 that detects that data of a bit line pair DL / NDL has been read out
5 and a reset circuit 16 which starts resetting the internal operation immediately after the dummy word line DWL is driven. Therefore, when the operation of the dummy word line DWL is detected, the data of the memory cell is read by the sense amplifier 10. Sense amplifier 1 which reads out data from a memory cell
The output of the sense amplifier 10 is fetched by the output data latch circuit 12 when it is detected that the output of 0 has been confirmed, and the word line driver is reset by the reset circuit 16 when the operation of the dummy word line DWL is detected. Therefore, the timing of reading data by the sense amplifier 10 and the timing of fetching data by the output data latch circuit 12 correspond to the dummy word line DW.
The optimum state is automatically set according to L and the operation state of the sense amplifier 10. That is, by confirming that the dummy word line DWL has been opened, it has been confirmed that a word line having the same operation has been opened. There is no need to adjust the timing of the internal control signal by the circuit, and the timing margin of the inverter delay circuit added to avoid malfunction due to insufficient pulse width of the word line can be eliminated. Further, since the read data is immediately taken into the output data latch circuit 12 immediately after the output of the sense amplifier 10 is determined, it is possible to cope with a short word line pulse width and realize a high-speed operation. further,
When the memory capacity changes, the timing of the internal control signal changes with the change in the operation time of the word line WL and the change in the time until the output of the sense amplifier 10 is determined. In addition, it is possible to operate at high speed.

[0029]

According to the semiconductor memory device of the present invention, a memory cell selection detection circuit is provided, or a dummy word line is provided to detect the operation of a word line and output the sense amplifier reading data from the memory cell. Is provided with a sense amplifier output determination detecting means for detecting that the data has been determined, and the output data is latched. Further, a resetting means is provided to reset a series of operations, so that the pulse width of the word line (after the word line is opened, The self-closing itself is set by the load of the memory cell connected to the word line), the operation timing of the sense amplifier, and the operation timing of the output data latch means are set. Therefore, it is possible to operate at high speed without having to provide a margin as in the case of timing setting. Further, when the memory capacity changes, the operation timing of the sense amplifier and the operation timing of the output data latch means change, so that timing design for each capacity is not required, and high-speed operation can be performed in accordance with the memory capacity. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a relationship among input signals, memory cell data, and internal control signals of the semiconductor memory device of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

4 is a timing chart showing a relationship among input signals, memory cell data, and internal control signals of the semiconductor memory device of FIG. 3;

FIG. 5 is a block diagram showing a configuration of a conventional semiconductor memory device.

6 is a timing chart showing a relationship among input signals, memory cell data, and internal control signals of the semiconductor memory device of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address input terminal 2 Address buffer 3 Clock input terminal 4 Pulse generation circuit 5 Inverter delay circuit 6 Row address decoder 7 Memory cell array 8 Column address decoder 9 Column selector 10 Sense amplifier 11 Inverter delay circuit 12 Output data latch circuit 13 Precharge circuit 14 Memory cell selection detection circuit 15 Sense amplifier output confirmation detection circuit 16 Reset circuit 17 Dummy word line driver 18 NAND circuit 19 Inverter 20 Inverter

Claims (2)

[Claims] 1. A memory cell array for storing data,
An address buffer for capturing an external address, an address decoder for decoding the captured address, and a word line driver for selecting a part of the memory cell array in response to a logical product of an output of the address decoder and an external clock signal; A memory selection detection unit that receives the output of the word line driver as an input and detects that the memory cell is selected, and operates in response to an output of the memory cell selection detection unit to read data of the selected memory cell A sense amplifier, a sense amplifier output confirmation detecting means for detecting that the output of the sense amplifier is confirmed, and the sense amplifier in response to an output of the memory cell selection detecting means and an output of the sense amplifier output confirmation detecting means. Output data latch means for capturing the output of The semiconductor memory device including a reset means for resetting the word line driver in response to a force. 2. A memory cell array for storing data,
An address buffer for capturing an external address, an address decoder for decoding the captured address, a word line driver for selecting a part of the memory cell array in response to a logical product of an output of the address decoder and an external clock signal, A dummy word line driver that operates in response to an external clock signal irrespective of an output of an address buffer, a sense amplifier that operates in response to an output of the dummy word line driver, and reads data of the selected memory cell; Sense amplifier output confirmation detecting means for detecting that the output of the sense amplifier has been confirmed, and output data for capturing the output of the sense amplifier in response to the output of the dummy word line driver and the output of the sense amplifier output confirmation detecting means Latch means, responsive to output of the dummy word line The semiconductor memory device including a reset means for resetting the word line driver Te.