JPH11191792A - Method and device for processing signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance for suppressing the waveform interference of a signal stream in the state of maintaining the stability of an AGC loop by comparing a level fluctuation value in the signal cycle of the signal sequence with a reference value, averaging the signal level fluctuation of the signal sequence through the adjustment on the preceding step side of an equalizer based on this result and controlling the reference value based on the signal level fluctuation value of an output signal from the equalizer. SOLUTION: In a signal processing circuit 2 of a digital signal recording and reproducing device, a gain is corrected by a first signal level control loop composed of a signal adjuster 21, first low-pass filter(LPF) 41, comparator 45 and third LPF 47 provided on the preceding step side rather than an equalizer 13 to generate signal delay concerning a signal level fluctuation component having jitter fluctuation in the repetition cycle equal with or faster than a frequency having the same repetition cycle as the basic cycle of a regenerative signal yk} in the fluctuation component of the regenerative signal yk}. Thus, even when quick-response gain correction is performed, this gain correction is not made unstable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal processing method and a signal processing device in a signal transmission system.

[0002]

2. Description of the Related Art As a signal processing circuit in a signal transmission system, a signal processing circuit of a digital signal recording / reproducing apparatus shown in FIG. 2 is conventionally known.

FIG. 2 is a block diagram showing a main part of a digital signal processing circuit constituting a digital signal recording / reproducing apparatus. The circuit block 1 is a digital signal processing unit 3, a modulator 5, a recording circuit unit 7, and a recording medium. 9, reproduction circuit section 11, equalizer 13, noise reduction circuit section 15, decoder 17, demodulator 1
9, a signal adjuster 21, a control signal generator 23, and a synchronization signal generator 25.

The digital signal processing unit 3 converts an analog signal supplied to an input unit (not shown) of the digital signal processing unit 3 into a digital signal code sequence {ak}, and converts the digital signal code sequence {ak} into a modulator. 5 The digital signal processing unit 3 converts the digital signal code sequence {ak} output from the demodulator 19 into an analog signal and outputs the analog signal from an output unit (not shown).

[0005] The modulator 5 converts the code sequence {ak} supplied from the digital signal processing unit 3 into a recording signal sequence {bk}, and supplies the recording signal sequence {bk} to the recording circuit unit 7. The recording circuit unit 7 supplies the recording signal sequence {bk} to a recording head (not shown) and records the recording signal sequence on a recording medium 9.

[0006] The reproduction circuit section 11 has a recording signal sequence {b} reproduced from the recording medium 9 by a reproduction head (not shown).
k}, a reproduction signal {yk} is generated, and the reproduction signal {yk} is generated.
To the signal adjuster 21 to suppress the signal level fluctuation of the signal {yk}, and to supply the reproduced signal with the signal level fluctuation suppressed to the equalizer 13. The equalizer 13 is composed of a multi-stage transversal filter, a signal {zk} in which the waveform interference of the reproduced signal {yk} is suppressed is obtained through the transversal filter, and the signal {zk} is supplied to the noise reduction circuit unit 15. .

[0007] The noise reduction circuit section 15 is provided with the maximum likelihood (ML: maximu
m likelihood or PRML: partial response maximum
likelihood) decoding means. The maximum likelihood decoding means converts the signal {zk} from the signal {zk} based on the property of the recording signal sequence {bk} (for example, the property that the recording signal sequence is NRZI) and the statistical property of noise. To obtain a signal sequence {pk} having the same repetition period as the recording signal sequence {bk} of the above.

[0008] The signal {pk} is supplied to a decoder 17 to obtain binary data {bk}, and the binary data {bk} is supplied to a demodulator 19. Get {ak}.

The control signal generator 23 detects a signal level fluctuation of the signal {zk}, generates a correction signal for suppressing the level fluctuation, controls the signal adjuster 21 with this correction signal, and controls the signal {zk} signal. Suppress level fluctuation.

The synchronization signal generator 25 is provided with a PLL (Phase Lock).
ed Loop) Synchronous signal generator with circuit configuration, signal {p
A synchronization signal synchronized with the basic period of k｝ is generated, and the synchronization signal is used as a detection window signal in the decoder 1.
7, and converts the signal {pk} into a binary signal {bk} based on the detection window signal.

Then, the binary signal {bk} is supplied to the demodulator 19 to be demodulated to the original digital signal code sequence {ak}, and the demodulated digital signal code sequence {ak} is supplied to the digital signal processing unit 3 for conversion. And output from an output unit (not shown) of the digital signal processing unit 3.

[0012]

As the maximum likelihood decoding means, Viterbi decoding with a low bit error rate is used for decoding for each bit. In this Viterbi decoding, amplitude information of a signal processed by this Viterbi decoding is used. For use, there is a property that the bit error rate increases due to the strong influence of the amplitude fluctuation of the signal processed in this Viterbi decoding.
Even in a normal decoding process in which a decoding process is performed for each bit using a threshold value, since the amplitude information of a signal is used, there is a property that the bit error rate increases due to the influence of the amplitude fluctuation. Therefore, the signal {zk} on which the decoding process is performed has an AGC (automatic gain c) from the amplitude variation of the signal {zk} in a range from a high frequency variation component to a DC signal level variation component.
ontroller) must be sufficiently suppressed in advance.

However, the control signal generator 23 detects a signal level fluctuation of the signal {zk}, generates a correction signal for suppressing the level fluctuation, controls the signal adjuster 21 with the correction signal, and controls the signal {zk}. In the conventional AGC shown in FIG. 2 which suppresses the signal level fluctuation of the AGC, there is a problem that this suppressing action is insufficient.

Next, the problem of the AGC characteristic of the AGC loop constituted by the equalizer 13, the signal adjuster 21, and the control signal generator 23 will be described.

FIG. 3A is a diagram of a linear equalization model of the AGC loop shown in FIG. 2, FIG. 3B is a diagram showing a gain characteristic of the diagram of the linear equalization model, and FIG. 3C is a phase characteristic of the diagram of the linear equalization model. FIG. 3 is a diagram showing delay characteristics.

In FIG. 3A, reference numeral 31 denotes a loop gain G (s) of the AGC loop, and reference numeral 32 denotes a loop delay amount D. It should be noted that the loop delay amount D is mostly a delay caused by the multi-stage transversal filters constituting the equalizer 13, and the delay caused by the signal adjuster 21 and the control signal generator 23 may be ignored.

Assuming that the number of taps of the transversal filter is n and the delay amount around one tap is T, the delay amount D is expressed by the following equation (1), and the absolute value of the delay amount D is Expressed as in equation (2), and
The characteristics of the C loop are represented as shown in equation (3).

D = e ^-snT (1) | e ^-snT | = 1 (2) G (s) × e ^-snT (3)

The frequency characteristic of the loop gain G (s) is represented as shown by a line 33 in FIG. 3B, and the frequency characteristic of the loop phase is represented as shown in FIG. 3C. Line 3 in FIG. 3C
5 shows the characteristic when the loop delay D is zero or negligible in FIG. 3A, the line 37 shows the characteristic when the loop delay D is not negligible in FIG. 3A, and the line 39 shows the frequency characteristic of the delay D. The line 36 indicates a decrease in the phase margin when the loop delay amount D cannot be ignored in FIG. 3A.

Therefore, in this AGC loop, a change in the amount of delay due to an increase or decrease in the number of taps of the transversal filter does not affect the gain of the AGC loop. However, if the number of taps of the transversal filter constituting the equalizer 13 is increased to enhance the effect of removing waveform interference, the amount of loop delay D increases.
As shown by the line 36, there is a disadvantage that the stability of the AGC loop is reduced.

In view of the foregoing, the present invention provides a signal processing for suppressing the waveform interference of the signal sequence {yk} while suppressing the waveform interference of the signal sequence {yk} while maintaining the stability of the AGC loop. It is an object of the present invention to improve and eliminate waveform distortion caused by this waveform interference.

[0022]

A signal processing method according to the present invention is directed to a signal processing method in which a waveform distortion of a signal sequence {yk} output from a signal transmission system is suppressed by an equalizer 13. The level fluctuation value of the signal cycle of {yk} is compared with a reference value {eb}, and adjusted at the preceding stage of the equalizer 13 based on the comparison result {ec} to average the signal level fluctuation of this signal sequence. At the same time, the reference value {eb} based on the signal level fluctuation value of the output signal of the equalizer 13
Control.

The signal processing apparatus according to the present invention is a signal processing apparatus in which the waveform distortion of the signal sequence {yk} output from the signal transmission system is suppressed by the equalizer 13. Signal gain adjusting means 21 for averaging the signal level fluctuation of the signal sequence based on the level fluctuation value of the signal period of the signal sequence {yk} and the reference value {eb}, and the signal of the output signal of the equalizer 13 The control unit 45 detects a level variation value and controls a reference value {eb} based on the detected signal level variation value, and the signal sequence {y}
The level fluctuation of k｝ is corrected.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a signal processing device according to the present invention will be described below with reference to FIG.

FIG. 1 shows an embodiment of a signal processing circuit of a digital signal recording / reproducing apparatus according to the present invention. The same components as those shown in FIG. explain.

In FIG. 1, reference numeral 2 denotes a block diagram showing a main part of a signal processing circuit constituting a digital signal recording / reproducing apparatus. The digital signal processing section 3 converts an analog signal supplied to the digital signal processing section 3 into a digital signal. Code sequence ｛a
k} and converts the digital signal code sequence {ak} to the modulator 5
The modulator 5 converts the code sequence {ak} supplied from the digital signal processing unit 3 into a recording signal sequence {bk}, and supplies the recording signal sequence {bk} to the recording circuit unit 7. The recording circuit unit 7 outputs the signal ｛b
k｝ is supplied to a recording head (not shown) and recorded on the recording medium 9.

Reproducing head (not shown) and reproducing circuit section 1
1 to convert the signal sequence recorded on the recording medium 9 into the reproduced signal {y
k}, and reproduces the reproduced signal {yk}
To suppress the envelope level fluctuation of the signal {yk}, supply the signal {yk} with the envelope level fluctuation suppressed to the first low-pass filter 41, and supply the reproduced signal {yk}
Signal ｛yk from which noise components outside the band frequency of
Get '｝.

The reproduction signal {yk ′} is supplied to an equalizer 13 composed of a multi-stage transversal filter, and is generated due to a decrease in the high frequency range of a transmission frequency characteristic of a signal transmission system between the recording circuit 7 and the reproduction circuit 11. A reproduced signal {zk} in which distortion due to the waveform interference is suppressed is obtained.

The reproduced signal {zk} is supplied to a noise reduction circuit section 15 constituted by maximum likelihood decoding means, and the original recorded signal sequence {b
A signal sequence {pk} having the same repetition period as the basic period of k is obtained, and this signal sequence {pk} is supplied to the decoder 17 to obtain binary data {bk}, and the binary data {bk} is obtained. The signal is supplied to the demodulator 19 to obtain the digital signal {ak} of the original code sequence from the demodulator 19.

Further, the signal sequence {zk} is supplied to the control signal generator 23, and compared with a reference envelope level signal supplied from a signal source (not shown) to a reference signal input terminal 23a of the control signal generator 23. An error signal of the envelope level of the signal sequence {zk} with respect to the reference envelope level signal is obtained, and this error signal is supplied to the second low-pass filter 43 and has the same repetition period as the fundamental period of the signal sequence {zk}. A high frequency component such as a frequency component is removed to obtain a first level fluctuation component {eb} composed of a DC level fluctuation component of the signal sequence {zk}.

When the recording medium 9 is a rotary disk, the second low-pass filter 43 is cut off so that the first error signal {eb} is composed of a DC level fluctuation frequency component of the rotation period of the rotary disk. Select a frequency.

The first level variation {eb} is input to one input terminal 45b of the two error signal input terminals 45a and 45b of the comparator 45, and the signal {yk '} is input to the other error signal input terminal 45a. At the comparator 45.
The second level variation {ec} is obtained by comparing this reference value with the level variation of the envelope of the signal {yk '} using the level variation {eb} of the second level as a reference value, and obtaining the second level variation {ec}. ec} is supplied to the signal conditioner 21 through a third low-pass filter 47 for removing noise components outside the band frequency of the reproduced signal {yk}, thereby controlling the gain of the signal conditioner 21 and suppressing the signal level fluctuation of the signal {pk}. I do.

In the embodiment of the signal processing circuit of the digital signal recording / reproducing apparatus shown in FIG. 1, the frequency component having the same repetition cycle as the fundamental cycle of the reproduced signal {yk} among the fluctuation components of the reproduced signal {yk} For a signal level fluctuation component having a jitter fluctuation of the same repetition period or a near period close thereto, a signal adjuster 21 and a first low-pass filter 4 provided in a stage preceding the equalizer 13 causing a signal delay.
1, the gain is corrected in the first signal level adjustment loop constituted by the comparator 45 and the third low-pass filter 47, and even if the gain is corrected quickly with a quick response, the gain described with reference to FIGS. The configuration is such that the correction does not become unstable.

Therefore, the cutoff frequency of the second low-pass filter 43 is selected as a frequency at which a frequency component higher than the DC level fluctuation component is cut off, and the control signal generator 23
And the response speed of the second signal level adjustment loop including the second low-pass filter 43 can be reduced, so that the gain correction by the second signal level adjustment loop does not become unstable.

Therefore, according to the embodiment of the signal processing circuit of the digital signal recording / reproducing apparatus shown in FIG. 1, the gain correction state of the entire signal processing circuit of the digital signal recording / reproducing apparatus is not destabilized. The transversal filter constituting the rectifier 13 is multi-staged to perform sufficient equalization to sufficiently correct the waveform distortion of the reproduced signal {yk} and sufficiently suppress the level fluctuation of the reproduced signal {yk}.

Therefore, the equalizer 13 and the noise reduction circuit 1
5, the reproduction signal {yk} is converted from the original recording signal sequence {b
It is possible to select a signal {pk} having a cycle that matches the repetition cycle of k}.

The fluctuation of the DC level generated when the setting of the equalizer is changed due to the distortion state of the reproduced signal {yk} having undergone the waveform distortion due to the waveform interference is also corrected by the second signal level adjustment loop. Therefore, such a setting change can be performed.

Although the transversal filter is used as the equalizer 13 in the embodiment shown in FIG. 1, a high-order filter may be used as the equalizer 13.
Further, in the embodiment shown in FIG. 1, the maximum likelihood decoding means using Viterbi decoding is used as the noise reduction circuit unit 15, but the signal {zk} is compared with a certain threshold value, and the signal signal {zk} is set as the threshold. Maximum likelihood decoding means for decoding to "0" or "1" depending on the magnitude between the values may be used.

Also, the signal processing circuit of the digital signal recording / reproducing apparatus has been described as an embodiment of the present invention with reference to FIG. 1 as the signal processing section in the signal transmission system. The present invention is not limited to the processing circuit, but may be applied to a signal processing unit of a signal transmission system in various forms of signal communication means.

[0040]

According to the present invention, the operation of the signal gain adjustment loop can be stabilized even when a signal processing unit causing a signal delay is provided in the signal gain adjustment loop of the signal processing device having the signal gain adjustment loop. Can be kept.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration of a signal processing device of the present invention.

FIG. 2 is a circuit block diagram illustrating a configuration of a conventional signal processing device.

FIG. 3A is a linear equalization model diagram of the AGC loop shown in FIG. 2; B is a diagram illustrating gain characteristics of the linear equalization model diagram illustrated in FIG. 2A. C is a diagram illustrating phase characteristics and delay characteristics of the linear equalization model diagram illustrated in FIG. 2A.

[Explanation of symbols]

2 signal processing circuit, 3 digital signal processing unit, 5 signal
{Modulator, 7} Recording circuit section, 9} Recording medium, 11
{Reproduction circuit unit, 13} equalizer, 15} noise reduction circuit unit, 17 ‥‥ decoder, 21 ‥‥ signal conditioner, 23 ‥‥ control signal generator, 43 ‥‥ second low-pass filter, 47
{3rd low-pass filter, 45} comparator

Claims (2)

[Claims] 1. A signal processing method in which a waveform distortion of a signal sequence output from a signal transmission system is suppressed by an equalizer, wherein a level variation value of a signal cycle of the signal sequence is compared with a reference value, and the comparison is performed. Adjusting the signal level fluctuation of the signal sequence by adjusting at the pre-stage side of the equalizer based on the result, and controlling the reference value based on the signal level fluctuation value of the output signal of the equalizer. Characteristic signal processing method. 2. A signal processing apparatus in which a waveform distortion of a signal sequence output from a signal transmission system is suppressed by an equalizer, wherein the level of a signal cycle of the signal sequence is provided before the equalizer. Signal gain adjustment means for averaging the signal level fluctuation of the signal sequence by a fluctuation value and a reference value,
A signal level variation value of the output signal of the equalizer is detected, and the level variation of the signal sequence is corrected by control means for controlling the reference value based on the detected signal level variation value. Signal processing device.