JPH11191778A - Repeating installation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain efficient data communication by realizing priority control in response to kinds of packets at a pre-stage of an asynchronous transfer mode ATM switch so as to send a packet with higher priority with priority. SOLUTION: Priority control sections 121 -12n-1 are provided to a pre-stage of an ATM switch section 13 for each of input channels 111 -11n-1 and process received data in the unit of packets before routing processing and switching processing and send the data to the ATM switch section 13 according to the priority depending o the kinds of the packets. Thus, even in the case of data with a traffic in excess of channel frequency band connecting to the ATM switch section 13 and a packet assembly/disassembly section 16, packets with high importance are transferred to the packet assembly/disassembly section 16, where they are processed, then the possibility of packet abort in the ATM switch section 13 is reduced and data are efficiently communicated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
Nous Transfer Mode: relates to a relay device used in a network, and more particularly to a relay device having a priority control function according to a packet type.

[0002]

2. Description of the Related Art Conventionally, a relay device (ATM switch) used for an ATM network has a routing process of a packet such as an IP (for example, where to send a packet, etc.).
Selecting a communication path) by software. In this case, since the performance of the relay device depends on the processing performance of software, that is, the performance of the processor, it is difficult to transfer packets at high speed.

On the other hand, as a method for greatly improving the performance of a relay device, a routing process in a network layer as in the related art is performed by software or hardware, and a transport layer exchanged between adjacent relay devices is performed. A method of performing a switching process in the data link layer using only hardware without software and using a bypass transfer path (hereinafter, referred to as a cut-through transfer path) established according to a protocol of a higher layer. Proposed.

[0004] Conventional packet transfer by routing processing in the network layer is called hop-by-hop transfer, and packet transfer by switching processing on the cut-through transfer path in the data link layer performed by hardware is called cut-through transfer. Call.

[0005] It is determined whether a packet input to the relay apparatus is to be transferred hop-by-hop or cut-through based on a condition called cut-through trigger for determining whether to establish a cut-through transfer path. You. As the cut-through trigger, the TCP port number of the first packet of each flow (hereinafter referred to as a trigger packet) is referred to. Cut-through transfer is performed by an application (for example, tel) that is determined to have a long session duration.
net, ftp, http).

In the following, a description will be given of a relay apparatus that performs cut-through transfer in addition to hop-by-hop transfer. Here, the methods of the conventional relay device will be described separately for (a) the case where the hop-by-hop transfer processing is performed by software and (b) the case where the hop-by-hop transfer processing is performed by hardware.

(A) When hop-by-hop transfer processing is performed by software FIG. 7 is a block diagram showing a schematic configuration of a conventional relay device when an ATM switch is used as a switch and hop-by-hop transfer processing is performed by software. is there. Figure of 71 ₁ ~
71 _n is an input line, 72 is an ATM switch unit, 73 is a switching table, 74 ₁ to 74 _n are output lines, 75
Denotes a packet assembling / dividing unit, 76 denotes a processor, and 77 denotes a frame memory.

[0008] The first packet of the flow to be routed by the relay device is input to the ATM switch unit 72 from the input lines 71 _{1 to} 71 _n-1 . In fact, ATM
The packet input to the switch unit 72 is converted into an ATM cell. In other words, a plurality of cells are stored in ATM units in packet units.
It is input to the switch unit 72.

The ATM switch 72 refers to the switching table 73 to perform switching processing of the packet (actually, an ATM cell) by hardware. Moreover, the packet of a flow that is not decided whether to hop-by-hop forwarding or cut-through transfer, set to be output to the output line 74 _n in the switching table 73 is performed.

The packet output to the output line 74 _n is
It is input to the packet assembling / dividing unit 75. Since the packet is divided into ATM cells and input, the original packet is assembled on the frame memory 77 so that the processor 76 can process the packet by the packet assembling / dividing unit 75. That is, since it is not possible to determine the type of data used for the application and the data length, etc., by looking at only one cell, the cells can be collected in packet units so that the processor 76 can process the data. I do.

When the assembling of the packet is completed, the packet assembling / dividing unit 75 notifies the processor 76 of the arrival of the packet for making the connection establishment request, together with the address of the frame memory 77 in which the packet is stored, and the like. . The processor 77 that has received the notification refers to the TCP port number of the packet and determines whether the flow through which the packet is to be transferred hop-by-hop or cut-through.

As a result of the determination, when the flow is cut-through transferred, the processor 76 sets the switching table 73 so that the packet flowing through the flow is switched only by the switching process in the ATM switch unit 72. . When the flow is transferred hop-by-hop, the switching table 73 is not changed, and the packets flowing through the flow are processed by the software of the processor 76 thereafter.

Next, how a packet to be cut-through transferred (hereinafter referred to as a cut-through packet) and a packet to be transferred hop-by-hop (hereinafter referred to as a hop-by-hop packet) are processed in the relay device. Will be described.

When a cut-through packet is input to the ATM switch 72, an output line is determined according to the switching table 73, and the determined output line 74 ₁ is determined.
The cut-through packet is output to ~ 74n _-1 .

The hop-by-hop packet is set in the switching table 73 so as to switch to the output line 74 _n . Output line 7 of ATM switch section 72
4 _n are output to the packet assembler / divider 7
5 is transferred.

The packet assembling / dividing unit 75 stores the ATM cells in the frame memory 7 so that the processor 76 can process them.
7 to assemble the original packet. When the packet assembling is completed, the packet assembling / dividing unit 75 outputs
Is notified together with the address of the frame memory 77 in which the packet is stored.

The processor 76 having received the notification performs a routing process based on the header (source address, destination address, etc.) of the packet. When the routing process is completed, the processor 76 notifies the packet assembling / dividing unit 75 that the packet to be transmitted exists in the frame memory 77. The packet assembler / divider 75 extracts a packet to be transmitted from the frame memory 77,
After being divided into cells, the input line 7 of the ATM switch 72
Enter 1 _n . The packet input from the input line 71 _n is output to output lines 74 ₁ to 74 _n−1 determined according to the switching table 73.

Here, in the conventional relay device, the processor 76 includes a hop-by-hop packet, a trigger packet, a packet including routing protocol information, an AT,
Regardless of the type of signaling cell or the like used for establishing the M connection, the packets are processed in the order in which the packet arrival notification is received from the packet assembling / dividing unit 75.

(B) When hop-by-hop transfer processing is performed by hardware FIG. 8 is a block diagram showing a schematic configuration of a conventional relay device when hop-by-hop transfer processing is performed by hardware using an ATM in a switch unit. FIG. In the figure, 81 _{1 to} 81 _n
Is an input line, 82 is an ATM switch unit, 83 is a switching table, 84 _{1 to} 84 _n are output lines, 85 is a packet assembling / dividing unit, 86 is a processor, 87 is a frame memory, and 88 is a routing processing unit.

FIG. 8 differs from FIG. 7 in that the hop-by-hop packet routed from the output line 84 _n to the packet assembling / dividing unit 85 and assembled in the frame memory 87 is routed to the routing processing unit 88.
In hardware.

When the packet assembling / segmenting unit 85 notifies that the packet assembling is completed on the frame memory 87, the routing processing unit 88, based on the header information (source address, destination address, etc.) of the packet, To perform routing processing. After the end of the routing process, the packet assembling / dividing unit 85 is notified that a packet to be transmitted exists in the frame memory 87. The packet assembling / dividing section 85 divides the packet into ATM cells and inputs the ATM cells to the ATM switch section 82 through the input line 81 _n .

As described above, by configuring the routing processing unit 88 by hardware, high-speed routing processing can be realized. In this case, in the configuration of FIG. 8, the packet to be processed by the processor 86 includes a trigger packet for determining whether or not to perform cut-through transfer, a packet including routing protocol information, a signaling cell used for establishing an ATM connection, and the like. Only the packet addressed to the relay device is provided.

Here, in the conventional relay device, the processor 86 and the routing processing unit 88 in FIG.
Processes the packet in the order in which the packet assembling / dividing unit 85 receives the packet arrival notification, regardless of the type of the packet, similarly to the processor 76 in FIG.

[0024]

In the conventional repeater shown in FIG. 7, the ATM switch 72 and the packet assembler / divider 75 are connected via one input / output line of the ATM switch 72. Packets to be processed by the processor 76, such as data packets to be transferred hop-by-hop, trigger packets, packets containing routing protocol information, and signaling cells used in establishing an ATM connection, are converted into ATM cells. Is transferred on the line.

From the ATM switch 72, packet assembly /
The cells are output to the division unit 75 in substantially the same order as the order in which the cells are input to the ATM switch unit 72 from the input line. The ATM switch 72 and the packet assembler / divider 75
Assembling / dividing unit 7 beyond the bandwidth of the line connecting
If the state where the cell addressed to No. 5 is input to the ATM switch unit 72 (congestion) continues, it is conceivable that cell discarding occurs inside the ATM switch unit 72.

In the conventional relay device, the ATM switch 7
Since the input side of No. 2 does not have a function of controlling the output order of cells addressed to the packet assembling / dividing unit 75, the cell discarding occurs regardless of the type of cell. In such a case,
Control and management information between relay devices, such as trigger packets, packets containing routing protocol information, and signaling cells, are also discarded in the same manner as data packets transferred hop-by-hop. For this reason, there is a possibility of affecting the control between the relay devices and the sharing of the management information between the relay devices.

In order to solve such a problem,
The packet assembling / dividing unit 75 has a buffer queue in the frame memory 77 for each cell type or each packet type. For example, the trigger packet is given a higher priority than other packets, and the processor 76 is given priority. Even if the processing is performed, cell discarding occurs in the ATM switch unit 72 regardless of the type of the cell, so that it cannot be said that the trigger packet is always processed preferentially in the entire apparatus. .

Also, in the configuration shown in FIG. 8, a packet of high importance, such as a trigger packet, a packet containing routing protocol information, and a signaling cell, may be discarded according to the input state of the cell.

The present invention has been made in view of the above points, and realizes priority control according to the type of packet at the preceding stage of the ATM switch, and preferentially transmits a high-priority packet to efficiently transmit data. An object is to provide a relay device that enables communication.

[0030]

According to a first aspect of the present invention, there is provided a relay apparatus for performing routing processing in a network layer and switching processing in a data link layer using an ATM switch. Before performing the above, the input data is handled in packet units, the type of the packet is determined, and priority control means for transmitting each packet to the ATM switch according to the priority according to the packet type is provided.

According to a second aspect of the present invention, the priority control means is provided before the ATM switch and has a plurality of queues for storing packets for each packet type. The transmission is performed to the ATM switch in accordance with the priority set for each queue.

[0032] Further, the present invention is characterized in that the priority control means outputs a packet from a queue having the highest priority among the queues. According to a fourth aspect of the present invention, the priority control means outputs packets from the queues in the order of priority.

According to such a configuration, the input data is handled in packet units before the routing processing and the switching processing are performed by the priority control means provided in the preceding stage of the ATM switch, and the input data is handled in accordance with the packet type. It is sent to the ATM switch according to the priority. As a result, even when a large number of traffics are input, the possibility that packets with high priority are transferred and processed preferentially and discarded in the ATM switch is reduced, thereby enabling efficient data communication.

In this case, by giving high priority to control / management information between relay devices such as trigger packets, control cells, and routing information, rapid control and management information can be shared between relay devices. Become.

Further, by making the priority of each packet type variable by setting from the outside, it is possible to give user data transferred hop-by-hop higher priority than control / management information. Can be preferentially processed.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A relay device according to an embodiment of the present invention will be described below with reference to the drawings. The relay device of the present invention is used as an exchange of an ATM network. In addition to performing routing processing in a network layer by software or hardware (hop-by-hop transfer), a layer higher than a transport layer exchanged between adjacent relay devices is provided. By performing switching processing in the data link layer (cut-through transfer) using only hardware without software and using a bypass transfer path (cut-through transfer path) established according to the protocol of It performs high-speed routing.

In the following, the configuration of the relay device is as follows:
The case where the hop-by-hop transfer processing is performed by software and the case where (b) the hop-by-hop transfer processing is performed by hardware will be described separately.

(A) When hop-by-hop transfer processing is performed by software FIG. 1 is a block diagram showing a schematic configuration of a relay apparatus of the present invention when an ATM switch is used as a switch and hop-by-hop transfer processing is performed by software. FIG. 11 _{1 in the} figure
To 11 _n are input lines, 12 _{1 to} 12 _n-1 are priority control units,
13 ATM switch unit, 14 a switching table, 15 ₁ to 15 _n is output lines, 16 a packet assembly and
Reference numeral 17 denotes a processor, and reference numeral 18 denotes a frame memory.

[0039] In FIG. 1, FIG. 7 differs is that the priority control unit 12 ₁ to 12 _n-1 are provided. The priority control unit 12 ₁ ~12 _n-1 is, ATM switch unit 13
The input data is handled in packet units.
Priority control is performed according to the packet type.

[0040] inputted from the input line 11 ₁ to 11 _n-1 packet (actually ATM cells), the priority control unit 12 ₁
At 12 _n−1 , the type of the packet is determined, and the packet is queued for each packet type. Priority control unit 12 ₁
In to 12 _n-1, each packet type buffer queue 23 _1-23 provided for each _m (see FIG. 2), priority is given with respect to the order in which they are output to the ATM switch unit 13, respectively. Priority control unit 12 ₁ ~12 _n-1 is
The buffer queues 23 ₁ to 23 _m having this priority are scheduled, and packets are output to the ATM switch unit 13. Incidentally, with reference to FIG. 2 will be described later detailed operation of the priority control unit 12 ₁ ~12 _n-1.

When a packet is input to the ATM switch unit 13 in the form of an ATM cell, the switching table 14
, The packet (actually, an ATM cell) is subjected to switching processing by hardware. Information such as which packet is output to which line is set in the switching table 14 in advance. Packets flowing in a flow for which hop-by-hop transfer or cut-through transfer is not determined are stored in the switching table 1.
It is set to be output to the output line 15 _n have been made to 4.

The packet output to the output line 15 _n is
It is input to the packet assembling / dividing unit 16. Since the packet is divided into ATM cells and input, the packet is assembled into the original packet on the frame memory 18 so that the processor 17 can process the packet at the packet assembling / dividing unit 16. That is, since it is not possible to determine the type of data used for the application and the data length, etc., by looking at only one cell, the cells are collected in packet units so that the processor 17 can process the data. I do.

When the assembling of the packet is completed, the packet assembling / dividing unit 16 notifies the processor 17 that the trigger packet of the flow has arrived, together with the address of the frame memory 18 where the packet is stored, and the like. The processor 17 compares the trigger condition with the trigger condition to determine whether or not the flow through which the packet flows should be cut-through transferred.

As a result, when the flow is cut-through transferred, the processor 17
The setting is made such that the packet flowing through the flow is routed only by the switching process of the ATM switch unit 13. In the case of hop-by-hop transfer, the switching table is not changed, and thereafter, the packets flowing through the flow are subjected to hop-by-hop transfer processing by software in the processor 17.

Next, processing of cut-through packets (packets transferred through cut-through) and hop-by-hop packets (packets transferred hop-by-hop) will be described.

When a cut-through packet is input to the ATM switch section 13, an output line is determined according to the switching table, and the determined output lines 151 to ₁ are determined.
The cut-through packet is output to 5 _n−1 .

In the hop-by-hop packet, the switching table 14 is set to switch to the output line 15 _n . Output line 1 of ATM switch unit 13
5 _n is output to the packet assembler / divider 16
Is forwarded to

The packet assembler / divider 16 stores the ATM cells in the frame memory 1 so that the processor 17 can process them.
8 to assemble the original packet. When the packet assembling is completed, the packet assembler / divider 16 sets the processor 17
Is notified together with the address of the frame memory 18 in which the packet is stored.

The processor 17 that has received the notification sends the header information of the packet (source address, destination address, etc.).
The routing process is performed based on. When the routing process is completed, the processor 17 notifies the packet assembling / dividing unit 16 that the packet to be transmitted exists in the frame memory 18. The packet assembling / dividing unit 16
The transmission packet is extracted from the frame memory 18 and the AT
After being divided into M cells, it is input to the input line 11 _n of the ATM switch unit 13. Packet input from the input line 11 _n is output to the output line 15 ₁ ~15 _n-1 determined in accordance with the switching table 14.

[0050] Here, a description will be given priority control section 12 ₁ ~12 _n-1. Figure 2 is a block diagram showing a schematic configuration of a priority control section 12 ₁ ~12 _n-1. Priority control unit 12 ₁ to 1
2 _n-1 are provided at the preceding stage of the ATM switch unit 13 for each of the input lines 11 _{1 to} 11 _n-1 , and as shown in FIG. 2, the packet assembling unit 20, the filtering unit 21, the filtering table 22, Buffer queue 23 ₁ to 23
_m , a queue management unit 24, and a selector 25.

The packet assembling section 20 assembles each of the divided cells input in the form of ATM cells into a packet format. In this case, information indicating what type of packet is written in a predetermined cell of each cell, and the packet assembling unit 20 assembles each cell in packet units based on this information.

[0052] Filtering unit 21 determines the type of a packet obtained by the packet assembling unit 20, with reference to the filtering table 22 is assigned to the buffer queue 23 ₁ ~ 23 _m in accordance with the packet to its type. As a method of determining the type of packet, for example, there is a method using VPI / VCI.

That is, in the ATM network,
A number of virtual paths (VPs) are set, and a virtual channel (V
C) are set. Therefore, first, a VPI (Virtual Path Identifier) is provided in the header of the cell in order to identify which VP is used. Further, in order to identify which VC in the VP should be used to send data to the other party, a VCI (Virtual Channel Identifie) is added to the header of the cell.
r: virtual channel identifier). This VPI /
The VCI is a part that determines which VP and which VC to select and communicate with the other party, and is therefore called a routing bit (a bit for selecting a communication path).
The cell is composed of 53 bytes, of which 5 bytes are used as a header and the remaining 48 bytes are used as user information.

Here, for example, UNI (User-Network Int)
erface), 8 bits of VPI and 16 bits of VCI are prepared, but the fields actually used may be limited. Further, the usage of some values is limited in advance, and a signaling VCC (Virtual Channel Control) for setting a connection to one of the values is used.
nection: virtual channel connection). The signaling VCCs are assigned to VCIs 1, 2, and 5, for example, for signaling purposes. Therefore, when the type of the input packet is determined, if a predetermined cell in the packet contains the VCIs of 1, 2, and 5, the packet can be determined as a connection setting packet.

The VCIs 1, 2, and 5 have the following types. VCI = 1: Meta-signaling VCI = 2: Broadcast signaling VCI = 5: Point-to-point signaling In the filtering table 22, the conditions for selecting a buffer queue according to the type of such a packet are set in advance. Buffer queue 23 ₁ ~ 23 _m is a memory for storing the filtered packets by filtering unit 21, for example, buffer queue 2
3 _1, 23 _2, 23 ₃ ... such priority order is assigned.

The queue management unit 24 includes a buffer queue 23
Output control of packets stored in ₁ to 23 _m is performed by a fixed priority method (FIG. 3) or a round robin method (FIG. 4) described later. The selector 25 is operated by the control of the queue management unit 24 selectively outputs the ATM switch unit 13 a packet stored in the buffer queue 23 ₁ ~ 23 _m.

[0057] Hereinafter, the processing operation of the relay apparatus including the priority control unit 12 ₁ ~12 _n-1. Each input line 11
₁ to 11 _n-1 input packet through (actually AT
M cells), since the priority control by the priority controller 12 ₁ ~12 _n-1, is input to the ATM switch unit 13.

[0058] In the priority control section 12 ₁ in to 12 _n-1,
Each cell input in the form of an ATM cell is put together in a packet format by a packet assembling unit 20 and provided to a filtering unit 21. The filtering unit 21 first determines whether the input packet is a normal packet, and when it is determined that the input packet is a normal packet, determines what kind of packet the packet is. The determination of the packet type is performed by reading information written in a predetermined cell among the cells constituting the packet.

The types of packets include trigger packets, packets containing routing protocol information, control / management information between relay devices such as signaling cells, and user data packets.

When the type of the packet is determined, the filtering unit 21 refers to the filtering table 22 to determine which buffer queue 23 ₁ to 23 _m
Decide if it should be stored in At that time, when assigning buffer queue 23 ₁ ~ 23 _m in each simply packet type, the packet type and buffer queue 23 ₁ ~ 23 _m 1
In this case, the buffer queue 23 _{1 is used under the} condition that the packet type and other information (for example, the transmission source of the packet, the transmission destination of the packet, or the flow in which the packet is transferred) are combined. ~ 23
_Since flexibility is taken into consideration, such as assigning _m , the filtering table 22 is arranged.

The filtering table 22 is searched for a buffer queue 23 ₁ in which the packet is to be stored.
When ~ 23 _m is determined, the filtering unit 21 buffer queue 23 that is the determining the packet ₁ ~ 23 _m
To be stored. The buffer queues 23 ₁ to 23 _m are FIFO which is a method of sequentially outputting packets stored first.
(First-in first-out method). So far is the input side of the operation of the priority control section 12 ₁ ~12 _n-1.

_On the output side of the priority control units 12 _{1 to} 12 _n−1 , one or more packets to be output to the ATM switch unit 13 are stored in the buffer management unit 24 from each of the buffer queues 23 ₁ to 23 _m. A signal (queue status signal) indicating whether or not the operation has been performed is input. The queue management unit 24, determines a buffer queue 23 ₁ ~ 23 _m of packets to be output next ATM switch unit 13 on the basis of this queue status signal is stored, corresponding to the buffer queue 23 ₁ ~ 23 _m A signal (output enable signal) for permitting packet output to the ATM switch unit 13 is activated only for this.

[0063] At the same time, the queue management unit 24 switches the secretase 25 so that packets from the corresponding buffer queue 23 ₁ ~ 23 _m is output to the ATM switch unit 13. How to perform the priority control depends on the algorithm implemented in the queue management unit 24. In this embodiment,
Two schemes, a fixed priority scheme (FIG. 3) and a round robin scheme (FIG. 4), are shown.

Here, the queue status (#x) signal indicates whether or not one or more packets are stored in the buffer queue #x. When the signal is at "H" level, it indicates that one or more packets are stored. And The output enable (#x) signal indicates whether or not output of a packet is permitted to the buffer queue (#x). When the signal is at the "H" level, the output enable (#x) signal indicates that the output is permitted. The highest priority is assigned to the buffer queue (# 1), and the lowest priority is assigned to the buffer queue (#m).

In the fixed priority system, the ATM switch unit 1
3 is a method of outputting a packet from a buffer queue having the highest priority among buffer queues storing one or more packets when determining a packet to be output.

Specifically, when the queue management unit 24 has a configuration as shown in FIG. 3 and a packet is stored in the buffer queue (# 1) (queue status (# 1) =
(H level), the output of the packet is always permitted to the buffer queue (# 1) (output enable (# 1) =
"H" level). The output enable (# 2) that permits the output of a packet to the buffer queue (# 2) is performed when no packet is stored in the buffer queue (# 1) having a higher priority than the own buffer queue (queue status (#
1) Only at the “L” level), it becomes the “H” level.

The output enable of the decoder 31 (# 1)
~ Output enable (#m), and generates a signal (selector control signal) for controlling the selector 25 so that a packet output from the buffer queue for which output is permitted is output to the ATM switch unit 13.

As described above, in the fixed priority system, packets are always output from the buffer queue having the highest priority. In the round robin method, when the next packet to be output to the ATM switch unit 13 is determined, the previous ATM
In this method, the right to output a packet is provided to a buffer queue having the next highest priority after the buffer queue that outputs the packet to the switch unit 13. However, since only the right to output is given, if the packet to be output is not stored in the buffer queue to which the right has been given,
Also grants the right to the buffer queue with the next highest priority.

As described above, in the round robin method, the right to output the packet to the ATM switch unit 13 is given, and the packet is output from the buffer queue storing the packet to be output.

Specifically, the queue management section 24 has a configuration as shown in FIG.
When a packet is output from 1), first, it is determined whether a packet to be output is stored in the buffer queue (# 2). If it is stored, the round robin scheduler 41 gives output permission to the buffer queue (# 2), and the output enable
Only 2) is set to “H” level and output.

The decoder 43 has a buffer queue (# 2)
A signal (selector control signal) for controlling the selector 25 is generated so that the packet output from is output to the ATM switch unit 13. Generate a signal that controls

When packets to be output are not stored in the buffer queue (# 2), the round robin scheduler 41 gives the right to output to the buffer queue (# 3), and gives the right to output to the buffer queue (# 3). It is determined whether a packet to be output is stored. The same operation is repeated until a buffer queue storing a packet to be output is found.

When the buffer queue storing the packet to be output is found, the round robin scheduler 41 points to the buffer queue having the next highest priority after the buffer queue and stops, and determines the packet to be output next time. In this case, the right to output from the buffer queue is given, and it is determined whether a packet to be output is stored in the buffer queue.

That is, in the round-robin system, packets are not output from a specific buffer queue to the ATM switch unit 13 preferentially as in the above-mentioned fixed priority system. In this method, packets are output in priority order.

[0075] Thus, provided before the ATM switch 13 to the priority control unit 12 ₁ ~12 _n-1, treats the input data before performing a switching processing and routing processing in packet units, corresponding to the packet type By performing the priority control, even if traffic exceeding the bandwidth of the line connecting the ATM switch unit 13 and the packet assembling / dividing unit 16 is input, packets with higher importance are given priority to the packet assembling / dividing unit 16. , The possibility of being discarded in the ATM switch unit 13 is reduced.

Therefore, by giving high priority to control / management information between relay devices such as cut-through trigger packets, control cells, and routing information,
It is possible to quickly share control and management information between relay devices.

Further, by making the priority of each packet type variable, it is possible to give user data transferred hop-by-hop higher priority than control / management information. It can also be processed preferentially. The priority is set according to the scenario of the user of the relay device (giving high priority to user data transferred hop-by-hop, giving high priority to control information, giving high priority to management information, etc.). It can be done flexibly.

(B) When hop-by-hop transfer processing is performed by hardware FIG. 5 is a block diagram showing a schematic configuration of a relay apparatus when an ATM switch is used as a switch and hop-by-hop packets are processed by hardware. It is. In the figure, 51 _{1 to} 51 _n are input lines and 52 _{1 to} 52 _n-1.
Is a priority control unit, 53 is an ATM switch unit, 54 is a switching table, 55 _{1 to} 55 _n are output lines, 56 is a packet assembling / dividing unit, 57 is a processor, 58 is a frame memory, and 59 is a routing processing unit.

The difference from FIG. 1 is that the frame data is transferred from the output line 55 _n to the packet
That is, the routing processing unit 59 performs a routing process of the hop-by-hop packet assembled on the routing device 8.

When the packet assembling / dividing unit 56 notifies the completion of packet assembly on the frame memory 58, the routing processing unit 59, based on the header information (source address, destination address, etc.) of the packet, To perform routing processing. After the end of the routing process, the packet assembling / dividing unit 56 is notified that a packet to be transmitted exists in the frame memory 58. The packet assembler / divider 56 divides the packet into ATM cells and inputs the ATM cells to the ATM switch 53 via the line 51 _n .

As described above, by configuring the routing processing unit 59 with hardware, high-speed routing processing can be realized. In this case, in the configuration of FIG. 5, the packets to be processed by the processor 57 are only the packets including the trigger packet and the routing protocol information, and the packets addressed to the relay device, such as the signaling cells used for establishing the ATM connection.

FIG. 6 shows a schematic configuration of the routing processing section 59. The routing processing unit 59 includes a frame memory management unit 61, a header analysis unit 62, a table I / F 63, and a forwarding table 64. Inside the routing processing unit 59, a notification of the completion of packet assembly is received from the packet assembling / dividing unit 56, the address of the frame memory 58 in which the packet is stored is received, and the frame memory management unit 61 manages the packet.

The frame memory management unit 61 extracts the header information of the packet based on the notified address of the frame memory 58 in which the packet is stored.
This is transferred to the header analysis unit 62. Header analysis unit 62
Then, the extracted header information is analyzed, a key for searching the forwarding table 64 storing the routing information of the packet is created, and the key is notified to the table I / F 63.

The table I / F 63 uses the notified search key of the forwarding table 64 to search and extract the routing information, which is the output route information of the packet, from the forwarding table 64. The extracted routing information is transferred to the frame memory management unit 61 together with information for identifying which packet the routing information relates to.

The frame memory management unit 61 writes the extracted routing information into the frame memory address where the packet is stored, and the packet assembling / dividing unit 5
6 is notified that the routing process has been completed.

In such a configuration, as in FIG.
Priority control unit 5 provided at the preceding stage of ATM switch unit 53
2 ₁ ~52 _n-1 to handle the input data in units of packets, and performs priority control corresponding to the packet type.

The configuration of the priority control units 52 _{1 to} 52 _n-1 is the same as that of FIG. 2, and the configuration of the queue management unit 24 provided therein (fixed priority system / round robin system). Since this is the same as FIG. 3 and FIG. 4, the description thereof is omitted here.

By the priority control by the priority control units 52 _{1 to} 52 _{n -1} , even if traffic exceeding the bandwidth of the line connecting the ATM switch unit 53 and the packet assembling / dividing unit 56 is input, the priority is controlled. Since a high packet is preferentially transferred to the packet assembling / dividing unit 56 and processed, the possibility of being discarded in the ATM switch unit 53 is reduced.

Therefore, by giving high priority to control / management information between relay devices such as cut-through trigger packets, control cells, and routing information,
It is possible to quickly share control and management information between relay devices.

Further, by making the priority of each packet type variable, it is possible to give user data transferred hop-by-hop a higher priority than control / management information. It can also be processed preferentially. The priority is set according to the scenario of the user of the relay device (giving high priority to user data transferred hop-by-hop, giving high priority to control information, giving high priority to management information, etc.). It can be done flexibly.

[0091]

As described above, according to the present invention, input data is handled in packet units before routing and switching processes are performed, and the input data is transmitted to the ATM switch according to the priority according to the packet type. Thereby, it is possible to transfer and process packets with high priority with priority, and to realize efficient data communication. Also, for example, control / relay between relay devices such as trigger packets, control cells, routing information, etc. By giving high priority to the management information, it becomes possible to quickly control and share the management information between the relay devices.

Also, by making the priority of each packet type variable by setting from the outside, it is possible to give the user data transferred hop-by-hop higher priority than the control / management information. Can be preferentially processed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a relay device of the present invention, and is a block diagram showing a schematic configuration in a case where an ATM switch is used as a switch and a hop-by-hop transfer process is performed by software.

FIG. 2 is a block diagram showing a schematic configuration of a priority control unit used in the relay device.

FIG. 3 is a block diagram showing a schematic configuration when a queue management unit in the priority control unit is realized by a fixed priority system;

FIG. 4 is a block diagram showing a schematic configuration when a queue management unit in the priority control unit is realized by a round robin method.

FIG. 5 is a block diagram showing a schematic configuration of a relay device of the present invention, in which an ATM switch is used as a switch and hop-by-hop transfer processing is performed by hardware.

FIG. 6 is a block diagram showing a schematic configuration of a routing processing unit in the relay device.

FIG. 7 is a diagram showing a schematic configuration of a conventional relay device,
FIG. 2 is a block diagram showing a schematic configuration in a case where an ATM switch is used as a switch and hop-by-hop transfer processing is performed by software.

FIG. 8 is a diagram showing a schematic configuration of a conventional relay device,
FIG. 2 is a block diagram showing a schematic configuration in a case where an ATM switch is used as a switch and hop-by-hop transfer processing is performed by hardware.

[Explanation of symbols]

11 _{1 to} 11 _n input line 12 _{1 to} 12 _n-1 priority control unit 13 ATM switch unit 14 switching table 15 ₁ to 15 _n output line 16 packet assembling / dividing unit 17 processor 18 frame memory 20 ... packet assembling unit 21 ... filtering unit 22 ... filtering table 23 ₁ ~ 23 _m ... buffer queue 24 ... queue managing unit 25 ... selector 31 ... decoder 41 ... round robin scheduler 42 ... output enable generator 43 ... decoder

Claims (4)

[Claims] 1. A relay device for performing routing processing in a network layer and switching processing in a data link layer using an ATM switch, wherein input data is handled in packet units before performing the routing processing and switching processing, and And a priority control means for determining each packet and sending each packet to the ATM switch in accordance with the priority according to the packet type. 2. The priority control means is provided in a stage preceding the ATM switch, has a plurality of queues for storing packets for each packet type, and sets packets stored in these queues for each queue. 2. The transmission to the ATM switch according to the determined priority.
The relay device according to the above. 3. The relay device according to claim 2, wherein said priority control means outputs packets from a queue having the highest priority among said queues. 4. The relay device according to claim 2, wherein said priority control means outputs packets from each of said queues in order of priority.