JPH11191738A - Signal demodulating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent out-of-synchronism in demodulation when superimposing a noise on an input signal by holding the input signal during counting to a prescribed value and demodulating the held signal when counting is reset after one cycle is counted. SOLUTION: Even when the noise is superimposed on an input signal IrRx from a count value '8' of a hexadecimal counter 103 to a count value '15', an edge detecting circuit part 101' detects that edge and sends it to a latch circuit 107 but the latch circuit 107 does not output a reset signal and detected contents before a hexadecimal count signal is next inputted from the hexadecimal counter 103, but outputs the reset signal to the hexadecimal counter 103 and an edge detection control circuit part 104 for the first time when the hexadecimal count signal is next inputted, and outputs the detected contents of the edge detecting circuit part 101' to a filtering circuit 102. The reset signal is not erroneously outputted to the hexadecimal counter 103 and count operation can be continued.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal demodulation circuit suitable for demodulating to bit data, for example, for use on the receiving side of an infrared communication device.

[0002]

2. Description of the Related Art In recent years, infrared signals have been used not only for remote controllers such as television receivers and audio / video equipment, but also for communication between a mouse and a printer of a personal computer and the main body.

The basic format of this kind of infrared signal (hereinafter abbreviated as "Ir signal") is such that a start bit of data "0" is added at the head of a predetermined number of bit data, and data "1" is added at the end. The configuration is such that an end bit is added, and the infrared ray is continuously output for a time corresponding to 3/16 bit only when the bit data is “0”.

Therefore, on the receiving side for receiving the Ir signal, the light receiving level detected by the light receiving section constituted by a photoelectric element such as a phototransistor or a photodiode changes from a normal "L" level to an "H" level, and This "H"
An ideal configuration is to detect the input of the signal “0” when it is determined that the level state is continuous for a time corresponding to 3/16 bits.

However, at the time of actual communication, the signal waveform changes by propagating in the space, and in many cases, the width direction of the pulse is attenuated. Therefore, the light receiving level continues for a time corresponding to the above 3/16 bit. It is rare that the level becomes "H" level, and it is difficult to detect reception accurately.

Therefore, usually, synchronization is achieved by detecting the edge of the rising portion where the light receiving level of the Ir signal is inverted from "L" level to "H" level, and at the same time, whether or not the edge is detected during each bit period. Thus, "0" or "1" of the bit data in the bit period is determined.

FIG. 5 exemplifies a configuration of an Ir signal receiving circuit for receiving and demodulating such an Ir signal. The input signal IrRx whose light receiving level ("H" level or "L" level) has been waveform-shaped. Is the edge detection circuit unit 101
Is input to

The edge detection circuit section 101 detects a rising edge of the edge of the input signal IrRx. When the rising edge of the edge is detected, a hexadecimal counter 103 for counting one bit width of the input signal IrRx is provided. While sending a reset signal to the edge control circuit unit 104,
A signal “0” or “1” according to the presence or absence of the detection is output to the filtering circuit 102.

The filtering circuit 102 shapes the waveform of the detection content of the edge detection circuit 101, that is, whether or not it has risen from the “L” level to the “H” level, to “1” or “0” bit data. To send to.

The hexadecimal counter 103 is reset by a reset signal from the edge detection circuit unit 101,
Thereafter, a count operation corresponding to 16 clocks per bit is repeatedly executed by a clock (not shown). When the count value becomes "8", an 8 count signal is sent to the edge detection control circuit unit 104, Further, when it becomes “16”, that is, “0”, a 16 count signal is sent to the edge detection control circuit unit 104 and the output control unit 105.

When receiving the reset signal or the 16 count signal, the edge detection control circuit 104 outputs a control signal for temporarily stopping the detection operation until receiving the 8 count signal from the hexadecimal counter 103. Send to 101.

The output control unit 105 has a hexadecimal counter 10
3 is reset by the reset signal from the edge detection circuit unit 101, or when the count value becomes “16”, that is, “0” by the counting operation,
The bit data “0” or “1” based on the detection signal that has been waveform-shaped by the filtering circuit 102 and sent to the output unit 106 is sent as an output signal Rx to the next-stage reception processing circuit (not shown).

In the circuit configuration as described above, FIG.
When the input signal IrRx as shown in (2) is applied to the edge detection circuit unit 101, the edge detection circuit unit 101 changes the reception level from the “L” level to the “H” level at the timing indicated by I in the figure. Upon detecting the rise, a reset signal is sent to the hexadecimal counter 103 and the edge detection control circuit unit 104.

The hexadecimal counter 103 is reset by the reset signal in synchronization with the falling edge of the clock shown in FIG. 6A, as shown in FIG. When the count value becomes "8", an 8 count signal is output to the edge detection control circuit 104, and when the count value becomes "16", the count value becomes "8". The count value is automatically returned to "0" and the output control unit 1
At step 05, a 16 count signal is output.

The edge detection control circuit 104 detects the edge until the 8-count signal from the hexadecimal counter 103 is input, that is, while the count value of the hexadecimal counter 103 is "0" to "7". The operation is suppressed by a control signal so that the circuit unit 101 does not detect a noise edge. When the eight count signal is input, the output of the control signal is stopped.

Therefore, the detection result of the edge detection circuit unit 101 when the count value of the hexadecimal counter 103 is between "8" and "16" is sent to the output unit 106 via the filtering circuit 102. In part 106, 1
Under the control of the output control unit 105 having received the 16 count signal from the hexadecimal counter 103, the detection result at that time is converted into bit data Rx and supplied to the next stage.

For example, if the value of the hexadecimal counter 103 is "1"
6 (0) ", there is no change in the light receiving level of IrRx, and no new edge is detected in the edge detection circuit unit 101. Therefore, FIG. 6 (4) assumes that the next bit data is" 1 ". ), The bit data Rx is supplied to the next stage.

[0018]

In the signal demodulation circuit having the above structure, the edge detection circuit 101 inadvertently re-starts the edge only while the count value of the hexadecimal counter 103 is "0" to "7". The edge detection control circuit 04 suppresses the operation by the control signal so as not to detect the signal.

Therefore, as shown in FIG. 7 (2), when noise or the like is superimposed on the input signal IrRx while the count value of the hexadecimal counter 103 is "8" to "15", the edge detection circuit section 101 determines that this is a rise in the light receiving level, and sends a reset signal to the hexadecimal counter 103, and the counting operation of the hexadecimal counter 103 deviates from the actual synchronization. Not only is detected erroneously (see FIG. 7 (5)), but also it becomes impossible to accurately demodulate Ir data received thereafter into bit data.

More specifically, when synchronization is lost due to noise detection, even if an Ir signal of data "0" is received thereafter, the count value of the hexadecimal counter 103 at that time is "0" to "7". Therefore, all input data is demodulated as data "1".

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to surely prevent the synchronization when demodulating a received signal due to the influence of noise or the like from being shifted. It is to provide a possible signal demodulation circuit.

[0022]

According to the first aspect of the present invention,
In a signal demodulation circuit for demodulating an input signal into bit data depending on the presence or absence of detection of an input signal having a predetermined bit length, a counting means reset by the detection of the input signal and starting to count the period of the input signal; Holding means for holding the input signal while counting to a predetermined value; and demodulation means for demodulating the signal held by the holding means when the counting means is reset after counting one cycle. It is characterized by having.

With such a configuration, even when noise or the like is superimposed on the input signal, it is possible to reliably prevent the synchronization at the time of demodulating the received signal from being affected by the influence.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a paging receiver having an electronic organizer function and a dial data transmission function will be described below with reference to the drawings. FIG. 1 shows a circuit configuration of the paging receiver 1, and a radio signal for calling the paging receiver 1 is based on an advanced radio paging system standard (RCR).
STD-43), which is received by the antenna 2 and sent to the receiver 22. The receiving section 3 demodulates the received data received by the antenna 2 into binary or quaternary digital data and sends it to the decoder 4.

When the decoder 4 detects that the power is turned on, the decoder 4 controls the receiving unit 3 until a synchronization signal is received within a predetermined time under the control of the control unit 6 connected via the bus B.
And upon receiving the synchronization signal, intermittently receive the self-frame based on the frame number in the synchronization signal and the control signal from the control unit 6 which has taken in the frame number data set in the ID-ROM 5. Drive.

The signal demodulated by the receiving unit 3 is converted into 8-bit parallel data and transmitted to the buffer memory 11, and this data matches the address data of the ID code set in the ID-ROM 5 by the control unit 6. When a signal for determining that the data has been input is input, the subsequently received vector data and message data are similarly converted into 8-bit parallel data and transmitted to the buffer memory 11.

The control unit 6 includes an Ir transmission / reception unit 7, a key input unit 8, a display unit 9, a deinterleave circuit 10, a buffer memory 11, a ROM 12, a RAM 13 in addition to the decoder 4 and the ID-ROM 5 via the bus B. , A driver 14, a transmission buffer 15, and an interface (I / F) 16, and controls the reception of the decoder 4 and controls the entire circuit according to an operation program fixedly stored in the ROM 12.

Under the control of the control unit 6, the deinterleave circuit 10 cancels the interleave processing applied to the received data stored in the buffer memory 11 and performs processing for returning to the original parallel data arrangement. It is.

The buffer memory 11 is used for buffering received data directly sent from the decoder 4 and supplying the received data to the deinterleave circuit 10, for example, for use in a process of restoring the received data.

The RAM 13 stores data created by the user by operating the key input unit 8 and message data received, specifically address data, schedule data, memo data, ToDo data, incoming data relating to the electronic organizer function. , Transmission data and the like.

The driver 14 includes a small speaker 17,
It is connected to the vibrator 18 and the LED 19 and selectively drives them according to the set contents, thereby informing the incoming call by buzzer sound, vibration, or flashing light.

The transmission buffer 15 sequentially stores a DTMF data signal of a digital value based on transmission data created by a user and sends it to the D / A conversion unit 20. The DTMF data signal is converted into an analog signal, and the speaker 21 provided in the paging receiver 1 is loudspeaked to emit a DTMF data signal composed of a combination of two preset audio frequency signals.

The interface 16 includes a connector 22
Is for directly transmitting and receiving data to and from other line-connected paging receivers and the like. I above
The r transmission / reception unit 7 includes an encoder / decoder 71 and an infrared transducer 72 as shown in FIG.
The encoder / decoder 71 further includes an infrared transmission encoder 73 and an infrared reception decoder 74, and the infrared transducer 72 includes an LED driver 75, an infrared detector and a reception amplifier 76.

The transmission data transmitted via the bus B is coded and modulated by an infrared transmission encoder 73 of an encoder / decoder 71 in accordance with a predetermined format, and thereafter, the LED driver 7 of the infrared transducer 72
5 and the LED driver 75 drives an LED (not shown) to emit light based on the transmission data, so that an infrared ray (Ir signal) is output to the outside.

In addition, infrared rays (I
r signal) is received by the infrared detector of the infrared transducer 72 and the receiving amplifier 76, amplified with a constant amplification factor after waveform shaping, and then amplified by the encoder / decoder 7
The data is sent to one infrared receiving decoder 74, where it is decoded to obtain received data. The obtained received data is sent to the work memory in the control unit 6 via the bus B.

FIG. 3 shows the infrared detector and the receiving amplifier 7.
6 shows the detailed circuit configuration, and the same parts as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The input signal IrRx (the received I
r), and detects the rising edge thereof (the point at which the light receiving level changes from "L" to "H").
2 is output to the latch circuit 107 provided therebetween.

Although the function of the latch circuit 107 will be described in detail later, the latch circuit 107 is configured to be reset by a reset signal output from the control unit 6 when the power is turned on and after a series of reception of the Ir signal is completed. Has become
When an edge detection signal is input from the edge detection circuit unit 101 'in the reset state, that is, when an edge detection signal related to a start bit is input, the reset signal is transmitted to the hexadecimal counter 103 and the edge detection control circuit 104.
Output to

When the reset signal is supplied from the latch circuit 107, the hexadecimal counter 103 returns the count value to "0" and restarts. When the count value becomes "8", the 8 count signal To the edge detection control circuit 10
4 and the latch circuit 107, and when it becomes “16”, that is, “0”, the 16 count signal is output to the edge detection control circuit 104, the output control unit 105 and the latch circuit 107
Respectively.

The latch circuit 107 outputs a reset signal to the hexadecimal counter 103 and the edge detection control circuit 104 when the edge detection signal is input from the edge detection circuit section 101 'in the reset state, as described above. At the same time, the information of data “0” is
Is output to the output unit 106 via the. And then 1
Until the 8-count signal is input from the hexadecimal counter 103, no signal is received from the edge detection circuit unit 101 '. After the input of the 8 count signal, an edge detection signal from the edge detection circuit unit 101 'is received until the input of the 16 count signal. If an edge detection signal is input during that time, data "0" is output. Otherwise, the information is held as data "1", and when a 16 count signal is input, the held content is passed to the filtering circuit 1
02 to the output unit 106. From the time when the 8 count signal is input from the hexadecimal counter 103 to the time when the 16 count signal is input, the edge detection by the edge detection circuit unit 101 'is sent to the hexadecimal counter 103 as a reset signal. And a reset signal by edge detection is sent to the hexadecimal counter 103 when the 16 count signal is input.

Next, the operation of the above embodiment will be described. When an input signal IrRx as shown in FIG. 4 (2) is given to the edge detection circuit section 101 ', first, in FIG.
When the light receiving level rises from the “L” level to the “H” level at the timing shown by, the edge detection circuit unit 101 ′ detects the rising edge and sends a detection signal to the latch circuit 107.

If this detection signal is the first detection signal, that is, if it is a start bit edge detection signal, the latch circuit 107 outputs the reset signal to the hexadecimal counter 10.
3 and the edge detection control circuit 104. The hexadecimal counter 103 receives the reset signal as shown in FIG.
In synchronization with the falling edge of the clock shown in (1), FIG.
The count value is reset to "0" as shown in
Thereafter, it counts up each time the clock falls.

When the count value of the hexadecimal counter 103 becomes "8", the edge detection control circuit 1
When the count value becomes "16", the count value is automatically set to "0" and the edge detection control circuit unit 104, the output control unit 105, and the latch circuit 107. To output a 16 count signal.

In the edge detection control circuit section 104, a period from when the reset signal from the latch circuit 107 or the 16 count signal from the hexadecimal counter 103 is input to when the 8 count signal from the hexadecimal counter 103 is input. That is, while the count value of the hexadecimal counter 103 is "0" to "7", the operation is suppressed by a control signal so that the edge detection circuit unit 101 'does not detect the edge of noise. When the 8 count signal is input, the output of the control signal is stopped.

Therefore, the detection result of the edge detection circuit section 101 ′ when the count value of the hexadecimal counter 103 is between “8” and “15” is output to the latch circuit 107. When the 16 count signal is input from the hexadecimal counter 103, the content detected by the edge detection circuit unit 101 ', which has been held, is output to the output unit 106 via the filtering circuit 102.

Therefore, the timing II in FIG.
When the position indicated by I, that is, when the count value of the hexadecimal counter 103 is between “8” and “15”, the noise is I
Even if it is superimposed on rRx, the edge detection circuit unit 1
01 ′ detects the edge and sends it to the latch circuit 107, but the latch circuit 107
The reset signal and the detected content are not output until the next 16 count signal is input from
Only when the count signal is input, the reset signal, the hexadecimal counter 103 and the edge detection control circuit 104
And outputs the detection content of the edge detection circuit unit 101 ′ to the filtering circuit 102.

In this case, although the detection content of the edge detection circuit unit 101 'is erroneously set to "0" due to the influence of the noise, a reset signal is sent to the hexadecimal counter 103. Nothing happens, and the counting operation can be continued, so that synchronization can be maintained.

Therefore, the transmitted data is BCH
If the bit data output from the output unit 106 is erroneous data as shown in FIG. 4 (6), the data may be correctly encoded by an error correction circuit (not shown) at the subsequent stage. Can be demodulated. In other words, if the error is a single error due to the influence of noise or the like, it is possible to accurately demodulate the received signal by the processing of the error correction circuit.

In the circuit configuration shown in FIG. 3, the 8-count signal and the 16-count signal are transmitted from the hexadecimal counter 103 to the latch circuit 107.
If the last 3 bits of the 4 bits of the hexadecimal counter 103 are "000", that is, if the count signal is sent to the latch circuit 107 every 8 counts, the signal line can be further simplified. Can be.

In the above embodiment, Ir (infrared ray)
The case where the present invention is applied to the infrared detector for receiving a signal and the receiving amplifier 76 has been described. However, the present invention is not limited to this, and any circuit that receives an asynchronous signal can be applied to other various signals. Of course.

In addition, the present invention can be variously modified and implemented without departing from the gist of the present invention. For example, the present invention can be applied to an electronic computer such as a personal computer and other devices which can be built in or connected to electronic equipment. The invention is applicable.

[0052]

According to the first aspect of the present invention, even when noise or the like is superimposed on the input signal, it is possible to reliably prevent the synchronization when demodulating the received signal due to the influence of the noise or the like. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration in an Ir transmission / reception unit of FIG. 1;

FIG. 3 is a block diagram showing a detailed circuit configuration in the infrared detector and the receiving amplifier of FIG. 2;

FIG. 4 is a timing chart showing the operation of each circuit in FIG. 3;

FIG. 5 is a block diagram showing a configuration of a conventional Ir signal receiving circuit.

6 is a timing chart showing the operation of each circuit in FIG.

FIG. 7 is a timing chart showing the operation of each circuit in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Paging receiver 2 ... Antenna 3 ... Receiving part 4 ... Decoder 5 ... ID-ROM 6 ... Control part 7 ... Ir transmitting / receiving part 8 ... Key input part 9 ... Key input part 10 ... Deinterleave circuit 11 ... Buffer memory 12 ... ROM 13 RAM 14 Driver 15 Transmission buffer 16 Interface 17 Small speaker 18 Vibrator 19 LED 20 D / A converter 21 Speaker 22 Connector 71 Encoder / decoder 72 Infrared transducer 73 Infrared Transmission encoder 74 Infrared receiving decoder 75 LED driver 76 Infrared detector and receiving amplifier 101, 101 'Edge detection circuit 102 Filtering circuit 103 Hexadecimal counter 104 Edge detection control circuit 105 Output control 106 … Output unit 107… Latch circuit

Claims (1)

[Claims] 1. A signal demodulation circuit for demodulating an input signal into bit data according to the presence or absence of detection of an input signal having a predetermined bit length, a count means for resetting upon detection of the input signal and starting counting of the cycle of the input signal; Holding means for holding the input signal while the counting means counts to a predetermined value; demodulation of the signal held by the holding means when the counting means is reset after counting one cycle. A signal demodulation circuit comprising: