JPH11191730A - Semiconductor output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of the circuit without neglecting the response. SOLUTION: In the case that an enable signal EN is inactive and no pre- buffer is in operation and a P channel MOS transistor(TR) 1 is nonconductive in an input state, the operation of an output level transfer circuit is halted because the enable signal EN is inactive so that no power is consumed. However, a gate of P channel MOS TR 2 is kept to a low level by a TR 8 before the TR 1 is conductive to turn on the TR 2. Thus, the enable signal EN becomes active, the pre-buffer is operated, 0 level is applied to the gate of the P channel MOS TR 1, and as soon as the TR 1 is conductive, a voltage of 3V from a power supply Vcc is outputted to an input/output pad with a high response. The enable signal EN being active, the output level transfer circuit comes in the operating state and the succeeding operation is conducted with a high response.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor output circuit having an interface function between different voltage levels in an LSI having two or more different signal voltage levels such as a 3V / 5V system.

[0002]

2. Description of the Related Art In recent years, the voltage of LSIs has been reduced, but it is inevitable that different voltage levels coexist in the transitional period of the reduction in voltage. Interface is required.
Recently, especially since the transition from 5V to 3V power supply, 5V
A / 3V interface circuit has been developed.

FIG. 3 shows such an interface 5
It is a figure explaining the operation | movement concept of V tolerant. The 5V tolerant LSI 31 outputs 0 to 3V, and the output pins can be connected to the external 3V bus 32 as well as to the 5V bus 33.

FIG. 4 is a block diagram showing a configuration example of a conventional semiconductor output circuit (see Japanese Patent Application Laid-Open No. 9-246942). This semiconductor output circuit includes a pre-buffer 3 connected to a Vcc (3 V) power supply and outputting a voltage of 0 to 3 V based on an input voltage A and an enable signal EN, and its output side is a P-type for pull-up. It is connected to the gate of the MOS transistor 1. P-type MOS transistor 1
Is connected in series with a P-type MOS transistor 2 for preventing backflow, the drain and substrate of the P-type MOS transistor 1 are connected to a 3V power supply, and the source of the P-type MOS transistor 2 is connected to an input / output pad 6. ing.

The substrate (N-type well) of the P-type MOS transistor 2 is connected to a switched floating N-Well circuit 4, and the switched floating N-Well circuit 4 is connected to a P-type MOS transistor 1 , And to the input / output pad 6. P-type MOS
The output potential transmission circuit 5 is connected between the source and the gate of the transistor 2, and the input / output pad 6 is connected to the bus line 7.

Here, the above-mentioned switched floating N-Well circuit 4 connects the substrate of the P-type MOS transistor 2 with the potential of the input / output pad 6 of 3.
When the voltage falls below V, the bias is biased to a low level of 3V,
This is a circuit for setting a floating state when the voltage becomes higher than V.

The detailed circuit diagram of the output potential transmitting circuit 5 is as shown in FIG. The output potential transmission circuit 5 is a PM connected in series between the input / output pad 6 and the ground.
The P-MOS transistor 2 includes an OS transistor 51 and a resistor 52, and a connection point thereof is connected to the gate of the P-MOS transistor 2 as an output terminal. A voltage lower than 3V by the threshold voltage Vth of the P-MOS is applied to the gate of the P-MOS transistor 51. Therefore, when the potential of the input / output pad 6 exceeds 3V, this potential is transmitted to the gate of the P-type MOS transistor 2 through the P-MOS transistor 51.

Next, the operation of the circuit of FIG. 4 at the time of pull-up will be described. First, it is assumed that the input / output pad 6 is at a low level. When the enable signal EN is active and the input signal A of "1" is input to the pre-buffer 3, the pre-buffer 3
Inverts the input signal and inputs "0" to the gate of the P-type MOS transistor 1. As a result, the transistor 1 is turned on. At this time, the “0” potential is applied to the gate of the P-type MOS transistor 2 from the output potential transmission circuit 5 and the P-type MOS transistor 2 is also turned on. 3V is applied to the input / output pad 6, and the input / output pad 6 is set to the power supply level of 3V. As a result, 3 V is applied to the output potential transmission circuit 5. At this 3 V, the output potential transmission circuit 5 does not transmit this potential to the gate of the P-type MOS transistor 2.
"0" potential is continuously applied to the gates of.

At the time of such pull-up, when 5 V is applied from the bus line 7 to the input / output pad 6, the switched floating N-Well circuit 4
P-type MO in forward bias state of PN diode
Since the substrate of the S transistor 2 is opened,
Backflow of the current to the 3V Vcc power supply through this substrate is prevented. At the same time, since 5 V applied to the input / output pad 6 is applied to the gate of the P-type MOS transistor 2 through the output potential transmission circuit 5, the P-type MOS transistor 2 is turned off. Therefore, current does not flow backward from the input / output pad 6 to the Vcc power supply of 3 V at the time of pull-up. Also, at this time,
No voltage greater than 3 V is applied between the gate and the source or drain or substrate of any transistor.

[0010]

In the conventional semiconductor output circuit as described above, in order to improve the performance of the circuit, the output potential transmission circuit 5 must always be operated. There is a problem that the leakage current flows to the ground side and the power consumption increases. Therefore, on the contrary, if the leakage is to be reduced, 5
When the application of 5 V is stopped after V is applied, if the input / output pad 6 does not drop to 0 V once, the gate of the P-type MOS transistor 2 cannot be set to 0 V by the operation of the output potential transmission circuit 5. The P-type MOS transistor 2 does not turn on immediately, so that the input / output pad 6
, There is a problem that a 3 V output cannot be easily output to the bus line 7.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor output circuit capable of reducing the power consumption of a circuit without deteriorating responsiveness. It is to be.

[0012]

In order to achieve the above object, a first aspect of the present invention is characterized in that the operation is turned on / off by an enable signal, and a prebuffer for inverting and amplifying an input voltage; A first input / output terminal capable of applying a voltage, and a first level connected between the input / output terminal and a low-level power supply having a voltage level lower than the high-level voltage.
A series circuit comprising a second transistor, when the input / output terminal exceeds the low level voltage, transmitting this voltage level to a control terminal of the second transistor to turn the transistor from on to off; An output potential transmission circuit whose operation is turned on / off by a signal, and at least a period in which the operation of the pre-buffer and the output potential transmission circuit is stopped and a period until the output potential transmission circuit starts operating, by the enable signal. An auxiliary circuit for operating a second transistor, wherein the first transistor is turned on / off based on an output voltage of the pre-buffer, thereby outputting the voltage of the low-level power supply to the input / output terminal. It is in.

According to the first aspect, when the enable signal is inactive, the pre-buffer stops operating and its output becomes, for example, a high level, so that the first transistor is set as a P-type MOS transistor. If this transistor is off, the voltage of the low-level power supply is not output to the input / output terminal, and the circuit enters the input state. At this time, since the enable signal is inactive, the output potential transmission circuit stops operating, and the power consumption here becomes almost zero. Thereafter, when the enable signal is activated and the pre-buffer operates and a low-level signal is output from the pre-buffer, the first transistor is turned on, and the voltage of the low-level power supply is changed to the first and second voltages. Is immediately output to the input / output terminal through a series circuit composed of the above transistors. afterwards,
The activation of the enable signal causes the operation of the output potential transmission circuit, whereby the on state of the second transistor is maintained, and the operation of the auxiliary circuit is turned off. Further, the on / off control of the second transistor after the operation of the output potential transmission circuit is performed with good responsiveness, and the responsiveness of the circuit operation is not neglected.

According to a second aspect of the present invention, the auxiliary circuit is constituted by a transistor having a large dimension, and the transistor is controlled by an input signal of the input / output terminal, so that at least the pre-buffer and the output are enabled by the enable signal. The second transistor is turned on during a period in which the operation of the potential transmission circuit is stopped and a period until the operation of the output potential transmission circuit starts.

According to the second aspect, since the transistor has a large dimension, the responsiveness during the output operation is improved.

A third aspect of the present invention is characterized in that the output potential transmission circuit has a series circuit of a plurality of transistors connecting the input / output terminal and a ground, and among these transistors, a transistor connected to the ground In that the gate width is reduced.

According to the third aspect, when the output potential transmission circuit transmits the potential of the input / output terminal to the gate of the first transistor, the output potential transmission circuit flows to the ground side by the narrow gate width transistor. Since the current can be reduced, power consumption is further reduced.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the semiconductor output circuit of the present invention. However, the same reference numerals are used for the portions corresponding to the conventional example. The pre-buffer 3 inverts and amplifies the level of the input signal A and outputs the inverted signal. The pre-buffer 3 operates when the enable signal EN is activated, and stops operating when the enable signal EN is inactive. The output side of the pre-buffer 3 is connected to the gate of a P-type MOS transistor 1 for pull-up. A P-type MOS transistor 1 is connected in series to a P-type MOS transistor 2 for preventing backflow, and its drain and substrate are connected to a 3V power supply Vcc.
It is connected to the. The source of the P-type MOS transistor 2 is connected to an input / output pad 6, and the input / output pad 6 is connected to a bus line 7. The input / output pad 6 is connected to the input side of an input buffer 9, and an input signal is input into the LSI circuit or the like through the input buffer 9.

The substrate of the P-type MOS transistor 2 is a switched floating N-Well circuit 4
Connected to a switched floating N-Well
The circuit 4 is connected to the 3V power supply Vcc and to the input / output pad 6 side. An output potential transmission circuit 1 is connected between the gate and the drain of the P-type MOS transistor 2.
0 is connected. The gate of the P-type MOS transistor 2 is connected to a transistor 8 having a large dimension, and this transistor 8 is connected to the output side of an input buffer 9.

Next, the operation of this embodiment will be described. When the enable signal EN is inactive, the prebuffer 3 stops operating and its output becomes "1", which is input to the gate of the P-type MOS transistor 1, so that the P-type MOS transistor 1 is turned off. become. For this reason, the voltage of the 3V power supply Vcc is not output to the input / output pad 6, and the input state becomes high impedance.

In this state, when a signal is input from the bus line 7 to the input / output pad 6, the input signal is input to the input buffer 9
Is input internally. At this time, the transistor 8 having a large dimension is operating, and before the P-type MOS transistor 1 is turned on, the gate of the P-type MOS transistor 2 is set to “0” level to turn on the transistor 2. When the enable signal EN is inactive,
The output potential transmission circuit 10 is turned off, and the power consumption of this circuit is almost zero.

Thereafter, when the enable signal EN becomes active and the pre-buffer 3 operates and the input signal A of "1" is input, the output of the pre-buffer 3 becomes "0",
Since the voltage is applied to the gate of the P-type MOS transistor 1, the P-type MOS transistor 1 is turned on. At this time,
Since the P-type MOS transistor 2 is already on,
The input / output pad 6 is immediately brought to a power level of 3V,
3 V is output to the bus line 7. At the same time, the enable signal EN is activated as described above, so that the output potential transmission circuit 10 is turned on and the P-type MOS transistor 2 is turned on.
Is held at "0". Input buffer 9
When the input / output pad 6 becomes 3V, the output of the input / output pad 6 becomes a high level.
Is turned off, but at this time, the output potential transmission circuit 10 has started operation.

In this state, when 5 V is applied from the bus line 7 to the input / output pad 6, the switched floating N-Well circuit 4 activates the P-type MOS transistor 2 in the forward bias state of the PN diode. Since the substrate is opened, a current is prevented from flowing back to the 3 V Vcc power supply through the substrate. At the same time, 5 V applied to the input / output pad 6 is applied to the gate of the P-type MOS transistor 2 through the output potential transmission circuit 10 to turn off the P-type MOS transistor 2. Therefore, no current flows back from the input / output pad 6 to the 3V Vcc power supply at the time of pull-up.

Thereafter, 5 V applied to the input / output pad 6
When the input / output pad 6 becomes 3 V or less when the output voltage disappears, the output potential transmitting circuit 10 immediately stops transmitting the output potential and
In order to set the gate of the MOS transistor 2 of the P-type to 0 level and immediately turn on the transistor 2, the P-type
The 3 V voltage of the Vcc power supply is output to the input / output pad 6 with high responsiveness through the S transistors 1 and 2.

FIG. 2 is a circuit diagram showing a detailed configuration example of the output potential transmission circuit 10 described above. The output potential transmitting circuit is a MOS transistor 10 between the input / output pad 6 and the ground.
The series connection circuits 1 to 103 are inserted, and a part of the series connection circuit of the MOS transistors 104 to 106 inserted between the 3V power supply VDD and the ground is connected to a part of the series connection circuit.

When the enable signal EN is at the inactive low level, the transistors 103 and 106 are turned off, and the series connection circuit of the transistors 101 to 103 and 104 to 106 is separated from the ground.
Is turned off, and the power consumption becomes almost zero. When the enable signal EN is at the active high level, the transistor 10
3 and 106 are turned on, and the transistors 101 to 103 are turned on.
And the series-connected circuits 104 to 106 are connected to the ground, and the output potential transmission circuit 10 becomes operable. Thus, when the input / output pad 6 exceeds 3 V, this potential is applied to the gate of the P-type MOS transistor 2 through the transistor 101, and the P-type MOS transistor 2 is immediately turned off.

According to the present embodiment, the enable signal E
When N is inactive and the pre-buffer 3 is in an input state in which the pre-buffer 3 is not operating, the operation of the output potential transmission circuit 10 is stopped and power is not consumed. it can. Moreover, since the P-type MOS transistor 2 is turned on by the transistor 8 before the transistor 1 is turned on, the enable signal EN is activated and the pre-buffer 3 is turned on, so that the P-type MOS transistor 2 is turned on.
When the MOS transistor 1 of the type is turned on, an output of 3 V can be immediately output from the input / output pad 6 to the bus line 7 with good responsiveness. Similarly, when 5 V is applied to the input / output pad 6 when the circuit is in the pull-up state and the P-type MOS transistor 2 is turned off and 5 V is applied, if the input / output pad 6 becomes 3 V or less. P-type MOS
Transistor 2 is immediately turned on, and input / output pad 6
3V voltage is output with good responsiveness.

[0028]

As described in detail above, according to the semiconductor output circuit of the present invention, the power consumption of the circuit can be reduced without deteriorating the response.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor output circuit of the present invention.

FIG. 2 is a circuit diagram showing a detailed example of the output potential transmission circuit shown in FIG.

FIG. 3 is a diagram illustrating the concept of operation of a conventional 5V tolerant.

FIG. 4 is a block diagram showing a configuration example of a conventional semiconductor output circuit.

FIG. 5 is a circuit diagram showing a detailed example of the output potential transmission circuit shown in FIG. 4;

[Explanation of symbols]

 1, 2P type MOS transistor 3 Prebuffer 4 Switched floating N-Well circuit 6 I / O pad 7 Bus line 8, 101-106 MOS transistor 9 Input buffer 10 Output potential transmission circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Toshikazu Kiyo 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba Semiconductor System Technology Center Co., Ltd.

Claims (3)

[Claims] 1. A pre-buffer whose operation is turned on / off by an enable signal and inverts and amplifies an input voltage, an input / output terminal to which a high-level voltage can be applied by an external circuit, A series circuit composed of first and second transistors connected between a low-level power supply having a low voltage level, and a second transistor that, when the input / output terminal exceeds the low-level voltage, raises this voltage level to the second transistor. And an output potential transmission circuit that turns on / off the transistor by transmitting the control signal to the control terminal and turns on / off the operation by the enable signal. At least the operation of the pre-buffer and the output potential transmission circuit is stopped by the enable signal. During which the second transistor is turned on during a period during which the output potential transmission circuit starts operating. A semiconductor output circuit comprising: an auxiliary circuit; and outputting the voltage of the low-level power supply to the input / output terminal by turning on / off the first transistor based on an output voltage of the prebuffer. . 2. The auxiliary circuit includes a transistor having a large dimension, and the transistor is controlled by an input signal of the input / output terminal.
2. The auxiliary circuit according to claim 1, wherein the auxiliary circuit operates at least during a period when the operation of the pre-buffer and the output potential transmission circuit is stopped by the enable signal and until the output potential transmission circuit starts operating. Semiconductor output circuit. 3. The output potential transmission circuit has a series circuit of a plurality of transistors connecting the input / output terminal and ground, and among these transistors, the gate width of a transistor connected to the ground is reduced. 3. The semiconductor output circuit according to claim 1, wherein: