JPH11187014A - Code deciphering device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a key for deciphering a code from being decoded from the appearance of circuit configuration. SOLUTION: Based on the difference of resistance values between resistance control areas 31b and 32b, a memory bit 30 selects the opening/closing state of switching elements 31 and 32 and by turning one of both the switching elements into close contact state and leaving the other element in an opening state, binary data are stored concerning the key for deciphering the code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encryption / decryption device suitable for use in an encrypted data transmission system, and more particularly, to an encryption / decryption device that is difficult to be forged by a third party.

[0002]

2. Description of the Related Art Using an encrypted data transmission system,
There is a system for providing certain information to a predetermined contractor for a fee. In this paid system, a receiving device incorporating an encryption / decryption device for decrypting information sent as encryption is distributed to subscribers. By receiving and decrypting the encryption by the receiving device, each contractor can obtain the pay information, and can also exclude the use of the pay information by a third party.

[0003] An encryption / decryption device used in this pay system is generally constituted by an integrated circuit such as an LSI. In this encryption / decryption device, a key for decryption of encryption is stored as binary data in a memory bit formed as a part of the integrated circuit.

Conventionally, a memory bit for storing binary data is conventionally provided by an inverter composed of a CMOS in which a PMOS and an NMOS are combined, that is, a CMOS.
An inverter is formed, and this inverter is formed by being incorporated in a substrate of an integrated circuit as a circuit component of the integrated circuit, or the memory bit is formed by a flip-flop incorporated in the substrate.

[0005] In a CMOS inverter, this CMO depends on whether the voltage applied to the input contact of the inverter constituted by the gate of each MOS is a power supply voltage or a ground voltage.
The value of the memory bit formed by the S inverter is determined to be "0" or "1". Thus, by connecting the input contact to a power supply line or a ground line, desired binary data is selectively stored.

In a flip-flop, a data setting signal line is selectively connected to a reset contact or a set contact of the flip-flop, so that the flip-flop is formed by the flip-flop in accordance with the connection relationship as described above. The value of the memory bit is determined to be “0” or “1”.

[0007]

In the meantime, in the encryption / decryption device, the substrate of the integrated circuit is generally packaged by covering the entire integrated circuit including the wiring portion with a resin or the like so as not to be seen from the outside. However, this resin can be relatively easily removed using a predetermined chemical.

When the circuit configuration of the memory bit is exposed by removing the resin, the C constituting the memory bit is exposed.
By visually checking the MOS inverter or flop flip and the wiring portion of the memory bit, it is possible to determine the binary data stored in the memory bit.

Therefore, the binary data of the key stored in the memory bit can be easily decrypted by a third party, so that the confidentiality of the information to be decrypted cannot be enhanced.

For this reason, there has been a demand for an encryption / decryption device that prevents a key for decrypting a ciphertext from being decrypted from the external appearance of the memory bit circuit configuration.

Further, when the key is decrypted, there is a problem that the encryption / decryption device incorporating the key is forged.
Therefore, an encryption / decryption device that is difficult to be forged by a third party has been desired.

[0012]

According to the present invention, there is provided a switching device comprising a pair of contacts formed on a semiconductor substrate at a distance from each other, and a resistance adjusting region formed between the contacts on the semiconductor substrate. Based on the basic concept of using elements.

In the switching element according to the present invention,
By adjusting the resistance value of the resistance adjustment region of the switching element, an open state and a closed state of the switching element are selected. Therefore, since the magnitude of the resistance value that substantially determines the open state and the closed state of the switching element cannot be known from the appearance of the switching element, even if the circuit configuration of the switching element is exposed, The open or closed state of the switching element cannot be determined from the appearance of the circuit configuration of the switching element.

The present invention specifically adopts the following configuration. <Structure 1> The present invention is an encryption / decryption device including a semiconductor substrate provided with at least one memory bit for storing binary data of a key for encrypting or decrypting a received signal.

A memory bit of the encryption / decryption device is a switching element row including a pair of switching elements connected in series with each other. A voltage for binary data is applied to both ends of the switching element row. And a switching element array provided with a data output terminal for outputting binary data according to the open state and the closed state of both switching elements.

In the pair of switching elements, an open state and a closed state of both switching elements are selected based on a difference in resistance value of a resistance adjustment region of each switching element, and one of the two switching elements is switched to a closed state. The other is left open.

<Function 1> In the encryption / decryption device according to the present invention, when a voltage is applied to both ends of the switching element row, the switching element on the high potential side is opened and the switching element on the low potential side is opened. When a certain switching element is in a closed state, the memory bit stores one value of the binary data, for example, “0”.

When the switching element on the high potential side is in a closed state and the switching element on the low potential side is in an open state, the memory bit stores the other value of the binary data. For example, “1” is stored.

Therefore, as described above for the switching element, even if the circuit configuration of the memory bit is exposed, whether the switching element forming the memory bit is in the open state or the closed state is determined. It cannot be known from the appearance of the memory bit circuit configuration. Thus, it is possible to prevent the binary data of the key stored in the memory bit from being determined from the appearance of the circuit configuration of the memory bit.

<Structure 2> The present invention is connected to a genuine decryption circuit for encrypting or decrypting a received signal, at least one pseudo circuit for the decryption circuit, and each of the encryption circuit and the pseudo circuit. An encryption / decryption device including a semiconductor substrate provided with the above-described switching element for selecting a circuit, wherein an open state and a closed state of the switching element are selected based on a resistance value of a resistance adjustment region, The switching element connected to the decoding circuit is in a closed state, and the switching element connected to the pseudo circuit is in an open state.

<Function 2> In the encryption / decryption device according to the present invention, the switching element connected to the decryption circuit is in a closed state, and preferably a plurality of pseudo circuits are provided.
Since the switching element connected to each of the pseudo circuits is in the open state, decoded data of a genuine decoding circuit among a plurality of circuits including the pseudo circuit is output.

In the same manner as in the operation 1 described above, it is impossible to know which switching element is in the closed state from the appearance of the circuit configuration of the encryption / decryption device. Whether the circuit is a circuit cannot be known from the appearance of the circuit configuration of the encryption / decryption device.

<Structure 3> Also, one decoding circuit and one pseudo circuit are provided, and a pair of the switching elements are connected in series between output terminals provided in both circuits. May be provided with a data output terminal.

<Function 3> In the encryption / decryption device according to the present invention, the switching element connected to the decryption circuit is in the closed state, and the switching element connected to the pseudo circuit is in the open state. Thus, the decoded data of the authentic decoding circuit of the two circuits is output from the data output terminal.

Further, in order to adjust the resistance value of the resistance adjustment region of the switching element, an ion implantation method can be used. By implanting impurities into the resistance adjustment region by an ion implantation method, the resistance value of the resistance adjustment region can be adjusted relatively easily.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below using specific examples. << Specific Example 1 >> FIG. 1 shows a memory bit composed of a row of switching elements according to the present invention. Prior to describing a memory bit composed of a switching element row according to the present invention with reference to FIG. 1, a configuration of an encrypted data transmission system including an encryption / decryption device incorporating the memory bit will be described with reference to FIG.

FIG. 2 shows the configuration of the encrypted data transmission system. Encrypted data transmission system 110 according to the present invention
Is a cryptographic device 10 for encrypting information to be transmitted and transmitting ciphertext to a receiving side, as is well known in the art.
And an encryption / decryption device 20 for receiving the encrypted text transmitted from the encryption device 10 and decrypting the encrypted text to obtain information as plain text.

In the illustrated example, a work key used for encrypting and decrypting plaintext and a master key used for encrypting and decrypting the work key as a key higher than the work key are shown. Hierarchical key systems are employed.

The encryption device 10 transmits plaintext transmission data a
Plaintext encryption circuit 11 for encrypting data using work key b
And a master key d used for encrypting the work key b
A master key storage unit 12 for storing
And a work key encryption circuit 13 for encrypting the work key b using the master key d stored in the work key b.

The encryption device 10 is provided with a transmission unit (not shown) which is well known in the art.
The encrypted transmission data c and the encryption key data e encrypted by the work key encryption circuit 13 are transmitted to the encryption / decryption device 20 by the transmission unit.

The encryption / decryption device 20 is provided with a well-known receiving unit (not shown). The encrypted transmission data c and the encryption key data e transmitted by the transmission unit of the encryption device 10 are: Received by the receiving unit.

The decryption device 20 includes a master key storage unit 21 for storing a master key f used for decrypting the encryption key data e received by the receiving unit into a work key, and an encryption key A work key decryption circuit 22 for decrypting the data e into a work key g using the master key f, and the encrypted transmission data c received by the receiving section into the plaintext received data h using the work key g. A plaintext decoding circuit 23 for decoding is provided.

The encryption / decryption device 20 is composed of an integrated circuit such as an LSI incorporated on a semiconductor substrate described later. FIG. 3 is an explanatory diagram of the master key storage unit 21 incorporated in the encryption / decryption device 20.

Master key storage unit 21 of encryption / decryption device 20
Is composed of, for example, eight memory bits 30, each of which stores binary data of the master key f, as shown in FIG.
A semiconductor substrate 34 (see FIG. 1) as a part of the integrated circuit
Built on top. Each memory bit 30 corresponds to the above 2
For example, “0” or “1” is stored as the value data.

As shown in FIG. 3B, each memory bit 30 is represented as an equivalent circuit including a switching element row (31, 32) in which both switching elements 31 and 32 are connected in series. Therefore, the master key storage unit 21
Is composed of eight switching element rows (31, 32).

Each switching element row is inserted in parallel between a power supply line (not shown) to which a power supply voltage is applied and a ground line (not shown) to which a ground voltage is applied. A data output terminal 33 is provided between the switching elements 31 and 32 in each switching element row.

One of the two switching elements 31 and 32 of each switching element row is in a closed state, and the other is in an open state. Therefore, each switching element row outputs the power supply voltage or the ground voltage to the data output terminal 33.

Each switching element array is formed on a semiconductor substrate 34 as shown in FIG. In the illustrated example, the semiconductor substrate 34 has an impurity concentration of, for example, 10 ¹³ to 10.
A P-type semiconductor exhibiting ¹⁴ / cm ³ is used, and the semiconductor substrate 34 has a high resistance value of 1 MΩ / □.

The switching element 31 includes a semiconductor substrate 34
A pair of contact points 31a formed on the top at a distance from each other
And 31a, and both contacts 31a, 3 on the semiconductor substrate 34
1a, and a resistance adjusting region 31b formed between them. Similarly to the switching element 31, the switching element 32 includes a pair of contacts 32a and 32a,
2c.

In the example shown in the figure, both contacts 31a, 31a and both contacts 32a, 32a of each switching element row are arranged on a straight line, and are close to each other between both switching elements 31 and 32 of each switching element row. One contact 31a and one contact 32a are connected by a wiring part 37.

The other contact 31a of the switching element 31
Is connected to the power supply line via a wiring section 35, and the other contact 32a of the switching element 32 is connected to the ground line. Thus, both switching elements 31 and 32 of each switching element row are inserted in series between the power supply line and the ground line.

As described above, the semiconductor substrate 34 has a resistance of 1 MΩ.
/ □ indicates a high resistance value. Therefore, in the illustrated example, between the pair of contacts 32a and 32a of the switching element 32,
That is, since the resistance adjustment region 32b has a high resistance value, the resistance adjustment region 32b of the switching element 32 is maintained in a substantially open state. Further, before the ion implantation described later, the switching element 31
As in 2, it is open.

In order to selectively close both switching elements 31 and 32 for each switching element row, the impurity concentration of resistance adjustment region 31b or resistance adjustment region 32b is adjusted. The resistance value of the region 31b or the resistance adjustment region 32b is adjusted.

In the example of FIG. 1, an impurity such as boron is implanted into the internal region of the semiconductor substrate 34 between the two contacts 31a and 31a of the switching element 31 by, for example, an ion implantation method. Almost 10 ¹⁹ -1
It has been increased to 0 ²⁰ pieces / cm ³ .

The switching element 31 in which the ions are implanted into the resistance adjusting region 31b has a low resistance value of 100 Ω / □. For this reason, the resistance adjustment region 31b of the switching element 31 into which the ions have been implanted is maintained in a substantially closed state.

On the other hand, since the switching element 32 in which ions are not implanted into the resistance adjusting region 32b has a high resistance value of 1 MΩ / □, the resistance adjusting region 32b of the switching element 32 in which ions are not implanted has a substantially open state. Is held.

Since the switching element 31 is in the closed state and the switching element 32 is in the open state, the memory bit 30 shown in FIG. 1 is, for example, "1" which is one of binary data. , And outputs the power supply voltage Vdd to the data output terminal 33.

FIG. 4 illustrates the operation of the memory bit 30. As described with reference to FIG. 1, ions are implanted only into the resistance adjustment region 31b of one of the switching elements 31 in the switching element row, and thereby, only one of the switching elements 31 is closed, whereby the memory bit 30 is closed.
The power supply voltage Vdd can be output to the data output terminal 33 of. Therefore, as shown in FIG. 4A, for example, “1” can be set as one of the binary data of the master key f stored in the memory bit 30.

On the other hand, ions are implanted only into the resistance adjusting region 32b of the other switching element 32 of the switching element row, thereby closing the other switching element 32, thereby connecting the data output terminal 33 of the memory bit 30 to the data output terminal 33. The ground voltage VGND can be output. Therefore, as shown in FIG. 4B, for example, “0” can be set as the other of the binary data stored in the memory bit 30.

As described above, for each memory bit 30 forming the master key storage unit 21, the switching element 31
Alternatively, by selectively injecting ions into the 32 resistance adjustment regions 31b or 32b, it is possible to store the master key f composed of 8-bit binary data in the master key storage unit 21 composed of switching element arrays. it can.

In the encryption / decryption device 20 according to the present invention, even if the circuit configuration of each memory bit 30 constituting the master key storage unit 21 is exposed,
Is controlled by impurity implantation into the resistance adjusting region 31b or 32c by ion implantation, so that the switching elements 3 constituting each memory bit 30 are controlled.
The open / closed state of 1 and 32 cannot be known from the appearance,
Therefore, the binary data of the master key f stored in each memory bit 30 cannot be determined from the appearance. This prevents the master key f from being decrypted from the external appearance of the circuit configuration of the encryption / decryption device 20.

In order to selectively close both switching elements of each switching element row, the resistance adjusting region 31b of the switching element 31 or the switching element 32
Instead of implanting ions into the resistance adjustment region 32b, the resistance value of the resistance adjustment region 31b or the resistance adjustment region 32b of the selected switching element can be reduced by using a thermal diffusion method. However, the ion implantation method is more preferable than the thermal diffusion method from the viewpoint of easy control of the impurity concentration.

Further, in the above-described example, by setting the electric resistance of one of the resistance adjusting regions 31b and 32b of the two switching elements exhibiting high electric resistance to be lower than that of the semiconductor substrate 34, Was selectively converted to a closed state, but instead of this example, a semiconductor substrate having a low electric resistance was used, and one of the resistance adjustment regions 31b and 32b of the two switching elements was changed to the electric resistance of the semiconductor substrate 34. By setting it higher than that, both the switching elements can be selectively converted to the open state.

Both switching elements can be constituted by MOS transistors or bipolar transistors instead of the above-mentioned example. In a switching element composed of a MOS transistor, the impurity concentration is controlled by, for example, injection of ions for adjusting the threshold value, so that the open / close state of the switching element, that is, “0”
Alternatively, “1” can be selected. In a bipolar transistor, by controlling the impurity concentration in the same way,
"0" or "1" can be selected.

FIG. 5 illustrates a modification of the memory bit. As shown in FIG. 5, a dummy switching element row including a switching element 31D and a switching element 32D connected in series to each other is connected in parallel to a switching element row (31, 32) including both switching elements 31 and 32. can do.

A data output terminal 33D provided between both switching elements 31D and 32D of the dummy switching element row is connected to a data output terminal 33 provided between both switching elements 31 and 32 of the switching element row. I have. Both switching elements 31D and 32D of the dummy switching element row are left open, or switching elements 32D and 32D
Are the corresponding switching elements 31 and 3
It is in the same open / close state as 2.

By providing the dummy switching element row in this manner, binary data corresponding to the genuine switching element row can be output from the data output terminal 33D, and which switching element row is genuine in appearance. Cannot be determined, it is possible to increase the load required for a third party to decode the binary data stored in the authentic memory bit 30.

<< Specific Example 2 >> In the specific example 1, an example is shown in which memory bits for key storage which make it difficult to discriminate binary data are constituted by the switching element rows shown in FIG. By using the above-described switching element to connect a dummy circuit for a decryption circuit such as the work key decryption circuit 22 or the plaintext decryption circuit 23 to a genuine decryption circuit, the genuine decryption circuit can be determined. Can be difficult.

FIG. 6 shows an encryption / decryption device according to the second embodiment.
The encryption / decryption device 20 according to the second embodiment of the present invention includes a decryption circuit 41 such as a work key decryption circuit 22 or a plaintext decryption circuit 23, and a dummy circuit 4 for the decryption circuit 41.
2 is provided. The dummy circuit 42 desirably has a circuit scale substantially equal to that of the decoding circuit 41, and may have any circuit function.

The encrypted data to be decrypted is supplied to the decryption circuit 41.
Input terminal 41a and the input terminal 42 of the dummy circuit 42
a is input in parallel. Between the decoding circuit 41 and the dummy circuit 42, a switching element array (43, 4) composed of a switching element 43 and a switching element 44 connected in series, similar to those shown in FIGS.
4) is inserted. A data output terminal 45 is provided between the two switching elements 43 and 44.

Of the two switching elements, the switching element 43 directly connected to the authentic decoding circuit 41
The resistance adjustment region on the semiconductor substrate 34 having the same high resistance value as described above has been subjected to, for example, ion implantation, and the resistance of the resistance adjustment region has been reduced. Has been.

On the other hand, in the switching element 44 connected to the dummy circuit 42, no impurity is implanted into the resistance adjusting region on the semiconductor substrate 34 exhibiting a high resistance value. Since it is held at a similar high resistance value, it is in an open state.

The output terminal 41b of the decoding circuit 41 and the data output terminal 45 are electrically connected to each other.
2 is not connected between the output terminal 42b and the data output terminal 45, the encrypted data, that is, the encrypted transmission data c or the encryption key data e is input to the decryption circuit 41 and the dummy circuit 42. Then, the decrypted data which is the output value of the decrypting circuit 41, that is, the work key g
Alternatively, the reception data h is output from the data output terminal 45.

As a method of knowing which of the decoding circuit 41 and the dummy circuit 42 is a genuine decoding circuit, there is a method of determining which of the switching element 43 and the switching element 44 is in a closed state. By this determination, a genuine decoding circuit can be known.

However, in the encryption / decryption device 20 according to the second embodiment of the present invention, the open / close state of the switching elements 43 and 44 cannot be determined from the appearance of the circuit configuration of the decryption device 20. And 42
Which is a genuine decoding circuit cannot be known from the appearance. Therefore, since the decryption circuit 41 is difficult to be identified, the decryption device 20 can be made difficult to be forged by a third party.

FIG. 7 illustrates a modification of the encryption / decryption device. In the specific example shown in FIG. 6, an example in which one dummy circuit is provided for one decoding circuit has been described. Instead of this example, a plurality of dummy circuits are connected in parallel as shown in FIG. Can be provided.

The encrypted data is input in parallel to the input terminal 51a of the single decryption circuit 51 and the input terminals 52a to 54a of the plurality of dummy circuits 52 to 54, respectively. Output terminals 52b to 54 of dummy circuits 52 to 54
A single switching element (56 to 58) similar to the switching element 44 set to the open state is provided between b and the data output terminal 59, respectively.

On the other hand, a switching element 55 similar to the switching element 43 set in a closed state is provided between the output terminal 51b of the decoding circuit 51 and the data output terminal 59. Thereby, the plurality of dummy circuits 52 to
54 and the decryption circuit 51, the authentic decryption circuit 5
Only 1 is selectively connected to the data output terminal 59.

According to the encryption / decryption device shown in FIG. 7, a plurality of dummy circuits are provided for one decryption circuit. The connection between the output terminals 51b to 54b of each circuit and the data output terminal 59 is determined in accordance with the open / close state of each of the switching elements 55 to 58 that cannot be distinguished from the outside. This makes it more difficult for a third party to identify a genuine decoding circuit. In this specific example, the encryption / decryption device has been described, but such a configuration of the encryption / decryption device can be applied to the encryption device.

[0070]

As described above, in the encryption / decryption device according to the present invention, the open state and the closed state of the two switching elements are selected based on the difference in the resistance values of the resistance adjustment regions of the pair of switching elements. Since the magnitude of the resistance value that substantially determines the open state and closed state of the switching element cannot be known from the appearance, the open state or closed state of each switching element cannot be known from the appearance, Therefore, the binary data is not determined from the appearance.

Therefore, it is possible to prevent the decryption key from being decrypted from the appearance of the circuit configuration of the memory bit, thereby improving the confidentiality of the decrypted information.

Further, in the encryption / decryption device according to the present invention, the open / closed state of the switching element connected to each of the decryption circuit and the pseudo circuit cannot be known from the external appearance. It will not be identified.

Therefore, even if the decryption key is decrypted, the decryption circuit is difficult to identify, so that the encryption / decryption device incorporating the decryption key can be hardly forged.

[Brief description of the drawings]

FIG. 1 is a diagram showing a memory bit including a switching element row according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of an encrypted data transmission system.

FIG. 3 is an explanatory diagram illustrating a master key storage unit of the encryption / decryption device.

FIG. 4 is an explanatory diagram illustrating an operation of a memory bit.

FIG. 5 is an explanatory diagram illustrating a modified example of a memory bit.

FIG. 6 is an explanatory diagram illustrating an encryption / decryption device of a specific example 2.

FIG. 7 is an explanatory diagram illustrating a modification of the encryption / decryption device.

[Explanation of symbols]

 Reference Signs List 10 encryption device 11 plaintext encryption circuit 12, 21 master key storage unit 13 work key encryption circuit 20 encryption / decryption device 22 work key decryption circuit 23 plaintext decryption circuit 30 memory bit 31, 32 switching element 31a, 32a contact point 31b, 32b Resistance adjustment area 33 Data output terminal 34 Semiconductor substrate 35, 36, 37, 38 Wiring unit 110 Encrypted data transmission system

Claims (5)

[Claims] 1. An encryption / decryption apparatus including a semiconductor substrate provided with at least one memory bit for storing binary data of a key for encrypting or decrypting a received signal, wherein the memory bit is A switching element array including a pair of switching elements connected in series, a voltage for the binary data being applied to both ends thereof, and an open state and a closed state of the two switching elements between the two switching elements; A switching element array provided with a data output terminal that outputs the binary data according to a state, wherein each of the switching elements has a pair of contacts formed at intervals on the semiconductor substrate; A resistance adjustment region formed between the two contacts on the semiconductor substrate, wherein each of the switches in the pair of switching elements An open state and a closed state of the two switching elements are selected based on a difference in the resistance value of the resistance adjustment region of the switching element, and one of the two switching elements is in a closed state and the other is in an open state. An encryption / decryption device characterized by being placed. 2. The resistance adjustment region of the one switching element in the semiconductor substrate has a resistance value higher than the resistance value of the semiconductor substrate including the resistance adjustment region of the other switching element by implantation of an impurity by an ion implantation method. 2. The encryption / decryption device according to claim 1, wherein the resistance value is set to a small value. 3. A genuine decryption circuit for encrypting or decrypting a received signal, at least one pseudo circuit for the decryption circuit, and a circuit connected to each of the encryption circuit and the pseudo circuit to select a circuit. A decryption device including a semiconductor substrate provided with a switching element for performing the switching operation, wherein the switching element includes a pair of contacts formed at intervals on the semiconductor substrate, and the switching element on the semiconductor substrate. And a resistance adjustment region formed between both contacts, wherein an open state and a closed state of the switching element are selected based on a resistance value of the resistance adjustment area, and the switching element connected to the decoding circuit is provided. An encryption / decryption device, wherein the switching element is in a closed state and the switching element connected to the pseudo circuit is in an open state. 4. A genuine decryption circuit having an output terminal for decrypting a received cipher, a pseudo circuit having an output terminal, and a pseudo circuit for the decryption circuit; and both outputs of the pseudo circuit and the decryption circuit. An encryption / decryption device including a semiconductor substrate having a pair of selection switching elements connected in series with each other between terminals, and a switching element row provided with a data output terminal between the two switching elements, Each switching element includes a pair of contacts formed at intervals on the semiconductor substrate, and a resistance adjustment region formed between the two contacts on the semiconductor substrate. An open state and a closed state of both the switching elements are selected based on a difference between the resistance values of the resistance adjustment regions of the switching elements, and the decoding circuit of the decoding circuit is selected. Serial decryption apparatus characterized by connected the switching element to the output end is placed in the closed state and the other of the switching elements are placed in an open state. 5. The resistance adjustment region of the switching element connected to the output terminal of the decoding circuit in the semiconductor substrate, wherein the resistance adjustment region of the other switching element is implanted by ion implantation. The encryption / decryption device according to claim 4, wherein the resistance value is set to a resistance value smaller than the resistance value of the semiconductor substrate.