JPH11187000A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable discrimination as to whether or not calibration is required from the outside by detecting a phase deviation between clock signals supplied from outside and synchronously supplied pulse signals even during a normal operation and reporting to the outside to that effect, when a skew is detected. SOLUTION: A skew detection circuit 101 compares the phases of a command flag F with that of a clock signal CLK, while taking the flag F as a representative of address signals and other command signals. When a phase difference is within a prescribed range, it is considered that no skew is present and a signal CB is turned to 'L'. When the phase difference is on the outside of the prescribed range, it is considered that skew is present, the signal CB is turned to 'H' and is reported to an external controller that phase adjustment for skew reduction is required. Also, a command address control circuit 103 shifts a storage device 100 to a calibration made and makes a skew reduction circuit 102 execute a calibration operation when it receives the signal CB 'H'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device having a circuit for reducing skew of input data.

[0002]

2. Description of the Related Art In a semiconductor device, it is desired to realize a high-speed operation by inputting and outputting data using a high-frequency signal. However, if the frequency of the data input / output signal is increased to achieve higher-speed operation, factors that control the signal frequency become apparent, and it is necessary to eliminate these factors.

A major factor that determines the frequency of a data input / output signal is a signal skew, that is, a shift in signal timing. For example, if there is a skew between the input clock signal for synchronization and another signal, when capturing another signal using the timing of the clock signal, there is a possibility that the capture of an erroneous signal may be performed due to a timing difference. is there. Since the possibility increases as the signal frequency increases, it becomes difficult to increase the operation speed by increasing the frequency of the data input / output signal when skew exists between the signals.

The skew between such signals is a conventional D skew.
At the signal frequency used in the RAM, there is a sufficient margin for the timing of taking in the input data, so that the problem was not so serious. However, the skew between signals cannot be ignored as compared with the timing at which input data is fetched from around 200 MHz when the signal frequency increases and it becomes difficult to increase the operation speed.

In order to reduce such a skew, a semiconductor memory device such as a SyncLink-DRAM is provided with a skew reduction circuit for controlling a latch timing of input data. The skew reduction circuit operates when the semiconductor memory device is set to the calibration mode immediately after power-on or immediately after returning from the power-down mode.

FIG. 8 is a block diagram showing an example of a skew reduction circuit. 8 includes a clock switching unit 11 and a skew reduction unit 12.
including. The skew reduction circuit 10 of FIG. 8 is used for an input section of a semiconductor device. In FIG. 8, the skew reduction unit 12 is shown only for one pin for inputting the data signal DQ, but a plurality of skew reduction units 12 may be provided for a plurality of signal input pins. .

The clock switching unit 11 includes a buffer 13 and a delay switching unit 14, and the delay switching unit 14 includes switches 18 and 19 and a delay unit 20. In the calibration mode for skew reduction, the clock signal DCLK for data signal synchronization input to the buffer 13 is supplied to the skew reduction unit 12 via the switch 18. In the normal operation mode, the clock signal DCLK input to the buffer 13 is delayed by the delay unit 20 for a predetermined time and supplied to the skew reduction unit 12 via the switch 19. The mode switching between the calibration mode and the normal operation mode is performed by the switches 18 and 19 by the control signal CT supplied to the delay switching unit 14.
This is done by controlling the opening and closing of That is, the switches 18 and 19 are turned on and off in the calibration mode, and the switches 18 and 19 are turned off and on in the normal operation mode.

The skew reduction unit 12 includes a buffer 1
5, including a phase adjustment unit 16 and a latch 17. The phase adjustment unit 16 includes a shift register 21, a phase comparator 22, and a delay line 23. In the calibration mode, the skew reduction unit 12
The clock signal DCL from the clock switching unit 11
K, and further receives a data signal DQ from outside. Phase adjustment unit 16 of skew reduction unit 12
Compares the phases of the clock signal DCLK and the data signal DQ, and adjusts the phase of the data signal DQ so that the phases of the two signals become equal. The phase adjustment of the data signal DQ is performed by controlling the delay amount of the delay line 23.

FIG. 9 is a circuit diagram showing an example of a circuit configuration of the shift register 21 of FIG. The shift register 21 in FIG. 9 includes NOR circuits 31-0 to 31-n, inverters 32-1 to 32-n, and NAND circuits 33-1 to 33.
−n, NMOS transistors 34-1 to 34-n, N
It includes MOS transistors 35-1 to 35-n, NMOS transistors 36-1 to 36-n, and NMOS transistors 37-1 to 37-n. Reset signal RT
Is set to LOW, the shift register 21 is reset. That is, when the reset signal RT becomes LOW, NA
The outputs of the ND circuits 33-1 to 33-n become HIGH, and the outputs of the inverters 32-1 to 32-n become LOW. Each pair of the NAND circuits 33-1 to 33-n and the inverters 32-1 to 32-n forms a latch by using each output as an input to each other. Therefore, the initial state set by the reset signal RT is maintained even when the reset signal RT returns to HIGH.

In this initial state, the output Qn of the NOR circuit 31-n is HIGH, as shown in FIG.
Outputs Q0 to Q of NOR circuits 31-0 to 31-n-1
n-1 is LOW. That is, only the output Qn is HIGH. When it is necessary to reduce the amount of delay, HIGH pulses are alternately supplied to the signal lines A and B. First, when a HIGH pulse is supplied to the signal line B, the NMOS transistor 35-n turns on. At this time, since the NMOS transistor 37-n is on, the NAND circuit 33-n
The output of n is connected to ground and forced to change from HIGH to LOW. Therefore, the inverter 32-n
Becomes HIGH, and this state changes to the NAND circuit 33.
-N and an inverter 32-n. At this time, the output Qn changes from HIGH to LOW, and the output Qn-1 changes from LOW to HIGH. Therefore, in this state, only the output Qn-1 becomes HIGH.

Next, when a HIGH pulse is supplied to the signal line A, the NMOS transistor 35-n-1 is turned on. At this time, since the NMOS transistor 37-n-1 is on, the output of the NAND circuit 33-n-1 is connected to the ground, and the output is forcibly changed from HIGH to LOW. Accordingly, the output of the inverter 32-n-1 becomes HIGH, and this state indicates that the NAND circuit 33-n-
1 and an inverter 32-n-1. At this time, the output Qn-1 changes from HIGH to LOW, and the output Qn-2 changes from LOW to HIGH.
Therefore, in this state, only the output Qn-2 becomes HIGH.

As described above, the signal lines A and B are alternately set to the high level.
By supplying the H pulse, only one of the outputs Q0 to Qn, which is HIGH, can be shifted to the left one by one. When it is necessary to increase the amount of delay, HIGH pulses are alternately supplied to the signal lines C and D. Since the operation in this case is the reverse of the above operation,
Detailed description is omitted.

It is the phase comparator 22 that supplies HIGH pulses to the signal lines A to D. The phase comparator 22
When the clock signal DCLK is compared with the output of the delay line 23 to determine that the phase of the clock signal DCLK is advanced, the signal lines A and B are set so as to reduce the amount of delay in the delay line 23. Are supplied alternately. Conversely, when it is determined that the phase of the clock signal DCLK is delayed, pulses are alternately supplied to the signal lines C and D so as to increase the amount of delay in the delay line 23. Hereinafter, the configuration of the phase comparator 22 will be described.

FIG. 10 is a circuit diagram showing an example of a circuit configuration of the phase comparator 22 of the phase adjustment unit 16 in FIG.
The phase comparator 22 includes NAND circuits 41 to 45, inverters 46 to 49, NAND circuits 50 and 51, inverters 52 and 53, a binary counter 54, an inverter 55, NAND circuits 56 and 57, and an inverter 58
And 59.

The NAND circuits 44 and 45 constitute a latch, and as shown in FIG. 10, two inputs are LOW and two outputs are HIGH in an initial state. The rising edge of the clock signal DCLK is the delay line 2
If the output is earlier than the rising edge of the data signal DQ from No. 3, the output of the NAND circuit 43 becomes HIGH earlier than the output of the NAND circuit 42. Therefore, the output of the NAND circuit 45 becomes LOW, and the output of the NAND circuit 44 remains HIGH. This state is latched,
After that, NA is raised by the rising edge of the data signal DQ.
Even if the output of the ND circuit 42 becomes HIGH, the state does not change.

Therefore, when the phase of the clock signal DCLK is advanced, the output of the inverter 49 becomes high.
H. Conversely, when the phase of the data signal DQ is advanced, the output of the inverter 55 becomes HIGH. Here, the signal from the inverter 48 plays a role of returning the state of the latch to the initial state by simultaneously making the outputs of the NAND circuits 42 and 43 LOW at an appropriate timing.
Without such a configuration, when the data signal DQ leads the phase, the output of the NAND circuit 42 becomes HIGH.
Then, after the output of the NAND circuit 43 becomes HIGH, the data signal DQ returns to LOW before the clock signal DCLK.
The output of the D circuit 45 becomes LOW. To avoid this, the outputs of NAND circuits 42 and 43 are simultaneously set to L level.
OWing is performed.

The output signal of the inverter 48 is supplied to a binary counter 54. The two outputs of the binary counter 54 are signals that alternately become HIGH every cycle of the clock signal DCLK. Binary counter 54
Includes NAND circuits 61 to 68 and inverters 69 to 71. Since its operation is within the prior art,
Description is omitted.

The two outputs of the binary counter 54 are N
It is supplied to one input of AND circuits 50 and 51. N
The outputs from the inverter 49 are supplied to the other inputs of the AND circuits 50 and 51. The two outputs of the binary counter 54 are further provided to NAND circuits 56 and 57.
Is supplied to one of the inputs. NAND circuits 56 and 57
The other input is supplied with the output from the inverter 55.

Therefore, when the clock signal DCLK is ahead of the data signal DQ in phase, the inverters 52 and 5 invert the outputs of the NAND circuits 50 and 51.
From 3, the HIGH pulse is output alternately. Conversely, when the phase of the data signal DQ is advanced, HIGH pulses are alternately output from the inverters 58 and 59 that invert the outputs of the NAND circuits 56 and 57.

The outputs from the inverters 52 and 53 are supplied to the signal lines A and B of the shift register 21 shown in FIG. 9, and one of the outputs Q1 to Qn, which is HIGH, is shifted one by one to the left. I will shift it. Also, the outputs from the inverters 58 and 59 are supplied to the signal lines C and D, and the output Qx, which is only HIGH among the outputs Q1 to Qn, is shifted to the right one by one. By supplying these output signals Q1 to Qn to the delay line 23, the amount of signal delay is adjusted.

FIG. 11 is a circuit diagram showing an example of the circuit configuration of the delay line 23. The delay line 23 includes an inverter 80, NAND circuits 81-1 to 81-n, N
AND circuits 82-1 to 82-n and inverter 83
-1 to 83-n. Here, the NAND circuit 82-1
To 82-n and the inverters 83-1 to 83-n,
A delay element array is formed.

An inverted signal of the data signal DQ is supplied to one input of the NAND circuits 81-1 to 81-n.
0 and signals Q1 through Qn at the other input.
Is supplied. Only one of the signals Q1 to Qn is H
A signal that is IGH is defined as Qx. NAND circuit 81-1
Of the circuits 81-n other than the NAND circuit 81-x, since one of the inputs is LOW, the output becomes HIGH. Among the NAND circuits 82-1 to 82-n receiving this HIGH level at one input, the NAND circuits 82-1 to 82-n
Anything other than the circuit 82-x functions as an inverter for the other input.

Therefore, the delay element array from the NAND circuit 82-n to the inverter 83-x + 1 is formed by the NAND circuit 8
2-n transmits a fixed HIGH level applied to one input. Therefore, one input of the NAND circuit 82-x is HIGH. The other input of the NAND circuit 82-x is connected to the inverter 80 and the NAND circuit 81-x.
, The data signal DQ is supplied. Therefore, NA
The delay element array from the ND circuit 82-x to the inverter 83-1 propagates the data signal DQ while delaying it, and a delayed signal is obtained as an output signal. In this case, the output signal is delayed from the input signal by a delay time of x delay elements.

As described in the description of the shift register 21 in FIG. 9, the signal Qx which is only HIGH among the signals Q1 to Qn can shift its position between 1 ≦ x ≦ n. Therefore, the delay time of the data signal DQ can be adjusted by using the delay line 23 of FIG. Shift register 21 and phase comparator 2 described above
2 and the delay line 23, when a calibration pattern is input as the data signal DQ in the skew reduction circuit 10 of FIG. 8, the calibration pattern can be adjusted to the phase of the clock signal DCLK. . Thus, in the calibration mode, the phases of the clock signal DCLK and the data signal DQ are matched, and in the normal mode, the data signal DQ is latched by the delay unit 20 using the clock signal DCLK appropriately delayed by the delay unit 20.
Latch.

[0025]

SUMMARY OF THE INVENTION A skew reduction circuit includes:
As described above, the drive is performed immediately after turning on the power or immediately after returning from the power down mode. However, even after the skew is reduced in the calibration mode, a new signal is not applied to the input signal due to the influence of the voltage and temperature fluctuation of the memory controller and the external bus wiring during the operation of the semiconductor memory device in the normal operation mode. A timing shift or skew will appear.

Therefore, even during the normal operation of the semiconductor memory device, it is necessary to appropriately set the semiconductor memory device to the calibration mode and operate the skew reduction circuit to adjust the timing (phase adjustment) of the input signal. However, the memory controller on the control side does not know whether there is a skew in the signal at the input to each semiconductor memory device. Therefore, the memory controller cannot determine whether calibration is necessary.

Accordingly, the present invention provides a semiconductor device having a skew reduction circuit capable of determining whether calibration is required from the outside in response to a skew occurring during operation. Aim.

[0028]

According to the first aspect of the present invention, a semiconductor device comprises a phase shifter between a clock signal supplied from the outside and a pulse signal supplied from the outside in synchronization with the clock signal. And a skew detection circuit for detecting a phase shift between the clock signal and the pulse signal, and an output terminal for outputting a signal indicating whether there is a phase shift to the outside. Features.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a skew for reducing a skew of the input signal by adjusting a phase of the input signal including the pulse signal in a calibration mode. When the skew detection circuit detects a phase shift in the normal operation mode, the phase shifts to the calibration mode to readjust the phase of the input signal.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the skew detection circuit is configured to determine, as the pulse signal, one of a rising edge and a falling edge of the clock signal. It is characterized by receiving a pulse signal supplied from outside in synchronization with the edge. According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the skew detection circuit is configured such that the input timing of the pulse signal is a predetermined period extending before and after the input timing of the predetermined one edge. It is characterized by including a circuit for determining whether or not it is within.

According to a fifth aspect of the present invention, in the semiconductor device according to the third aspect, the skew detection circuit includes a plurality of clock signals having a predetermined timing relationship with the clock signal based on the clock signal. And a plurality of latch circuits for latching the plurality of clock signals at a timing based on the input timing of the pulse signal,
A determination circuit configured to detect a phase shift between the clock signal and the pulse signal based on a combination of signal levels held by the plurality of latch circuits.

In the sixth aspect of the present invention, the semiconductor device comprises:
A skew detecting a phase shift between the clock signal and the pulse signal by comparing phases between a clock signal supplied from the outside and a pulse signal supplied from the outside in synchronization with the clock signal. A detection circuit and a skew reduction circuit that adjusts the phase of the input signal including the pulse signal in the calibration mode to reduce the skew of the input signal, and the skew detection circuit detects a phase shift in the normal operation mode. In some cases, the phase of the input signal is readjusted by shifting to the calibration mode.

According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the skew detection circuit includes, as the pulse signal, a predetermined one of a rising edge and a falling edge of the clock signal. It is characterized by receiving a pulse signal supplied from outside in synchronization with the edge. In the semiconductor device according to the present invention, the skew detection circuit may be configured such that the input timing of the pulse signal is a predetermined period extending before and after the input timing of the predetermined one edge. It is characterized by including a circuit for determining whether or not it is within.

According to a ninth aspect of the present invention, in the semiconductor device according to the seventh aspect, the skew detection circuit includes a plurality of clock signals having a predetermined timing relationship with the clock signal based on the clock signal. And a plurality of latch circuits for latching the plurality of clock signals at a timing based on the input timing of the pulse signal,
A determination circuit configured to detect a phase shift between the clock signal and the pulse signal based on a combination of signal levels held by the plurality of latch circuits.

In the above invention, the skew detection circuit compares the phase of the clock signal with the phase of the pulse signal input in synchronization with the clock signal, so that when a skew occurs in the input signal including the pulse signal, Can detect that even during normal operation. When a skew is detected during the normal operation as described above, the fact is notified to the outside, so that an external controller or the like can be notified that the phase adjustment for skew reduction is necessary. Also, in response to skew detection, shift from the normal mode to the calibration mode and allow the skew reduction circuit to readjust the phase of the input signal, so that signal timing deviation due to power supply voltage, temperature fluctuation, etc. during the normal operation mode Can be dealt with.

[0036]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention. 1 includes a skew detection circuit 101, a skew reduction circuit 102, a command / address control circuit 103,
Row decoder 104, column decoder 105, cell array circuit 106, sense amplifier 107, input / output control circuit 1
08, and the input / output buffer 109.

The skew detection circuit 101 is a component according to the present invention, and the other components are a conventional DRAM.
Alternatively, it is the same as that used in the SyncLink-DRAM. The semiconductor memory device 100 shown in FIG.
First, a general operation will be described. The clock signal CLK, the command signal, and the address signal input to the semiconductor memory device 100 are supplied to the skew reduction circuit 102. The skew reduction circuit 102 has the same configuration as that of the skew reduction circuit 10 shown in FIG. Latch the reduced command and address signals. The skew reduction circuit 102 supplies the command / address signal with reduced skew to the command / address control circuit 103.

Command / address control circuit 103 decodes the received command signal and controls the operation of each component in semiconductor memory device 100 according to the result of the decoding. For example, immediately after turning on the power or immediately after returning from the power down mode, this is determined by a command input or the like, and the semiconductor memory device 100 is set to the calibration mode. Thereby, the skew reduction circuit 102
Can execute the calibration operation.
The command / address control circuit 103 converts the row address of the received address signal into a row decoder 10.
4 and the column address to the column decoder 105.

The row decoder 104 decodes the received row address and accesses the corresponding row address of the cell array circuit 106. In the case of data reading, data of the selected row address is read out to the sense amplifier circuit 107 including a plurality of sense amplifiers. The column decoder 105 decodes the received column address and accesses a sense amplifier corresponding to the selected column address among the plurality of sense amplifiers of the sense amplifier circuit 107. When reading data,
Data is supplied to the input / output control circuit 108 from the sense amplifier accessed by the sense amplifier circuit 107. Further, this data is output to the outside of the semiconductor device 100 via the input / output buffer 109.

In the case of data writing, data supplied to the input / output buffer 109 is transmitted to the input / output control circuit 108.
The signal is supplied to the cell array circuit 106 via the selected sense amplifier of the sense amplifier circuit 107. By performing row access by the row decoder 104, data is stored in the selected row address of the cell array circuit 106.

Here, the command flag signal F is synchronized with Sync.
This signal is used for a Link-DRAM, and is input in synchronization with a clock signal CLK. The command flag signal F is a command / signal for the SyncLink-DRAM.
This is provided to indicate the timing of address input, and the command / address input is taken into the DRAM with the rising edge as the start timing. Although omitted in the above description, the command flag signal F is also similar to the address signal and the command signal in the skew reduction circuit 10.
2, the phase is adjusted and supplied to the command / address control circuit 103.

The skew detection circuit 101 according to the present invention comprises:
It receives the command flag signal F and the clock signal CLK, and compares the phases of both signals. If the phase difference between the two signals is within a predetermined range, it is determined that there is no skew, and LOW is output as the output signal CB. If the phase difference between the two signals is outside the predetermined range, it is determined that skew exists, and HIGH is output as the output signal CB. Output signal CB is output outside semiconductor memory device 100. Therefore, by detecting this output signal CB, an external device such as a memory controller
At 0, it can be determined whether or not input signal skew exists.

The output signal CB from the skew detection circuit 101 may be supplied to the command / address control circuit 103. In this example, the command / address control circuit 103 controls the mode of the semiconductor memory device 100. Therefore, when receiving the signal CB indicating that skew exists from the skew detection circuit 101, the command / address control circuit 103 shifts the mode of the semiconductor memory device 100 to the calibration mode, and causes the skew reduction circuit 102 to perform calibration. Execute the operation.

As described above, the semiconductor memory device 10 of FIG.
In the normal operation mode, which is not the calibration mode for skew reduction, 0 indicates that skew exists in the input signal, and this can be notified to the outside as the output signal CB. Further, the semiconductor memory device 100 can be shifted to the calibration mode by the signal CB indicating that the skew exists, and the calibration operation by the skew reduction circuit can be executed. Even during the calibration operation, the skew detection circuit 101 may be operated, and the presence or absence of the skew may be continuously notified to the outside.

In the example of FIG. 1, the phase of the command flag signal F and the phase of the clock signal CLK are compared to determine whether or not skew exists. That is, the command flag signal F is used as a representative of another address signal or command signal. When the command flag signal F has skew, the address signal and the command signal also have skew. It is assumed that the converse is also true. Also, when the semiconductor memory device 100 is Sync
Even if it is not a Link-DRAM, if there is a pulse signal input in synchronization with a predetermined one of rising edges or falling edges of the clock signal, this pulse signal is sent to the command It can be used instead of the flag signal F.

FIG. 2 is a block diagram showing an example of the configuration of the skew detection circuit 101. Skew detection circuit 101
Are input buffers 121 and 122, delay circuits 123 and 124, latches 125 and 126, a determination circuit 127,
And an output buffer 128. Clock input terminal 13
The clock signal CLK supplied to 0 is buffered in the normal input buffer 121. The input buffer 121 outputs a clock signal CLK0 whose timing is slightly delayed due to buffering. Clock signal CL
K0 is input to the latch 125 and also to the normal delay circuit 123. The delay circuit 123 delays the clock signal CLK0 by the delay time T and outputs the same as the clock signal CLK1. The clock signal CLK1 is
It is supplied to a latch 126 similar to the latch 125.

The command flag signal F input to the command flag signal input terminal 131 is buffered in an input buffer 122 similar to the input buffer 121. From the input buffer 122, a command flag signal F0 whose timing is slightly delayed due to buffering is output.
Here, the delay in the timing of the command flag signal F0 due to buffering in the input buffer 122 is caused by the clock signal CL due to buffering in the input buffer 121.
This is the same as the timing delay of K0. The command flag signal F0 is input to the ordinary delay circuit 124. The delay circuit 124 delays the command flag signal F0 by a delay time t1 (t1 <T), and
Output as Command flag signal F1 is latch 1
25 and the latch 126 are supplied as a synchronization signal for taking in data.

The latch 125 outputs the command flag signal F1
Is used as a synchronization signal, and the clock signal CLK0 is latched at the rising edge. Latch 126 uses command flag signal F1 as a synchronization signal, and latches clock signal CLK1 at its rising edge. Latch 12
5 and 126 output the latched signal levels as signals S0 and S1.

The determination circuit 127 receives the signals S0 and S1, and determines the relative phase relationship between the clock signal CLK and the command flag signal F based on the signal levels of both signals. Clock signal CLK and command flag signal F
When it is determined that there is a phase shift between the two signals, that is, when it is determined that there is a skew between the signals, the signal CB0
Is output, for example. In this example, when it is determined that there is no skew between the signals, the signal C
B0 is LOW. The signal CB0 is output from the skew determination signal output terminal 132 to the outside of the semiconductor device 100 as a signal CB via a normal output buffer 128.

FIG. 3 is a timing chart showing the skew determination operation by the skew detection circuit 101. FIG.
Shows a case where there is no timing shift, that is, no skew between the clock signal CLK and the command flag signal F. In this case, the rising edge of the command flag signal F coincides with the rising edge of the clock signal CLK.

As shown in FIG. 3, the clock signal CL
K is slightly delayed in timing due to buffering, and becomes a clock signal CLK0. Clock signal CLK
0 is further delayed by the delay time T by the delay circuit 123 to become the clock signal CLK1. Similarly, the command flag signal F is slightly delayed in timing due to buffering, and becomes the command flag signal F0. At this time, the clock signal CLK0 and the command flag signal F0 have timing. Command flag signal F0
Is further delayed by a delay time t1 by the delay circuit 124 to become a command flag signal F1.

In this case, the rising edge of the command flag signal F1 is delayed by the delay time t1 from the rising edge of the clock signal CLK0. Also, the clock signal CL
The rising edge of K1 is delayed from the rising edge of clock signal CLK0 by delay time T. In the skew detection circuit 101 shown in FIG.
Is within the period T between the rising edge of the clock signal CLK0 and the rising edge of the clock signal CLK1. Delay time t
1 is smaller than the delay time T, and naturally, in the case of FIG.
Exists within.

If the command signal F1 is earlier than the timing shown in FIG.
The rising edge of 1 exists outside the period T. Also, when the command signal F1 is later than the timing shown in FIG. 3 by the time t2 (= T−t1), the rising edge of the command signal F1 exists outside the period T.

The latches 125 and 126 latch the clock signal CLK0 and the clock signal CLK1, respectively, at the rising edge of the command flag signal F1. Therefore, in the example of FIG. 3, the signal S0 that is the data latched by the latch 125 (the output signal of the latch 125) is HI.
GH, and the signal S1, which is data latched by the latch 126 (output signal of the latch 126), becomes LOW.

The determination circuit 127 of the skew detection circuit 101 in FIG. 2 determines that the signals S0 and S1 are HIGH and L, respectively.
In the case of OW, LOW is output as the signal CB (signal CB0). When the signals S0 and S1 are in other combinations, HIGH is output as the signal CB. In the example of FIG. 3, the signal CB is LOW. Therefore the signal C
When B is LOW, it indicates that the rising edge of the command flag signal F1 exists within the period T.
That is, it indicates that the rising edge of the command flag signal F which is the original input signal exists within the range of t1 + t2 before and after the corresponding rising edge of the clock signal CLK. Thus, it can be determined that the command flag signal F and the clock signal CLK are in phase within a predetermined allowable range.

FIG. 4 is a timing chart showing a skew determination operation by the skew detection circuit 101, and shows a case where a skew exceeding an allowable level exists. In FIG. 4, the rising edge of the command flag signal F is delayed from the rising edge of the clock signal CLK by a time t2 or more. Therefore, the rising edge of the command signal F1 is later than the rising edge of the clock signal CLK1, and exists outside the period T between the rising edge of the clock signal CLK0 and the rising edge of the clock signal CLK1. In this case, the signals S0 and S1 are both HIGH. Therefore, the determination circuit 127 outputs HIGH as the signal CB (signal CB0).

As described above, it can be seen that the rising edge of the command flag signal F which is the original input signal exists outside the range of t1 + t2 before and after the corresponding rising edge of the clock signal CLK. That is, it can be determined that the command flag signal F and the clock signal CLK are out of phase beyond a predetermined allowable range. FIG. 5 is a timing chart showing a skew determination operation performed by the skew detection circuit 101, and shows another case in which a skew exceeding an allowable level exists.

In FIG. 5, the rising edge of the command flag signal F leads the rising edge of the clock signal CLK by more than the time t1. Therefore, the rising edge of the command signal F1 corresponds to the clock signal CL.
The clock signal CL advances from the rising edge of K0.
It will be outside the period T between the rising edge of K0 and the rising edge of the clock signal CLK1. In this case, the signals S0 and S1 are both LOW.
Therefore, the determination circuit 127 outputs HIGH as the signal CB (signal CB0).

In this manner, it can be seen that the rising edge of the command flag signal F, which is the original input signal, exists outside the range of t1 + t2 before and after the corresponding rising edge of the clock signal CLK. That is, it can be determined that the command flag signal F and the clock signal CLK are out of phase beyond a predetermined allowable range. FIG. 6 is a circuit diagram illustrating an example of a circuit configuration of the determination circuit 127 of the skew detection circuit 101.

As shown in FIG. 6, the decision circuit 127
It includes an inverter 141 and a NAND circuit 142. NA
The signal S0 is supplied to one input of the ND circuit 142. The other input of the NAND circuit 142 receives the signal S
The inverted signal of 1 is input from the inverter 141. Therefore, the output CB0 of the NAND circuit 142 becomes low only when the signals S0 and S1 are HIGH and LOW, respectively.
W. That is, when there is no skew (within a predetermined allowable range), it becomes LOW, and when there is skew (exceeds a predetermined allowable range), it becomes HIGH.

FIG. 7 shows the latch 125 or 126 shown in FIG.
FIG. 2 is a circuit diagram showing an example of the circuit configuration of FIG. Latch 1 of FIG.
25 and 126 may have the same circuit configuration. FIG.
Are gates 151 and 152 composed of a PMOS transistor and an NMOS transistor, and the inverter 1
53 to 159, PMOS transistor 160, NMO
S transistor 161, PMOS transistor 162,
And an NMOS transistor 163.

Inverters 153 and 154 constitute a first latch, and inverters 155 and 156 constitute a second latch. When the command flag signal F1 is LOW,
The gate 151 is open and the gate 152 is closed. At this time, both the PMOS transistor 160 and the NMOS transistor 161 are OFF, and the inverter 154 does not operate. Therefore, the first latch is not operating. The supplied clock signal CLK0 (or CLK1) propagates through the inverter 157, the gate 151, and the inverter 153, and is blocked by the gate 152.

When the command flag signal F1 becomes HIGH, the gate 151 closes and the gate 152 opens. At this time, both the PMOS transistor 160 and the NMOS transistor 161 are ON, the inverter 154 operates, and the first latch operates the clock signal CLK0 (CLK
Latch 1). The clock signal CLK0 (CLK1) held by the first latch is output to the output signal S0 via the gate 152, the inverter 155, and the inverter 159.
(Or S1). At this time, the inverter 156 is off, and the second latch is not operating.

When the command flag signal F1 returns to LOW again, the gate 151 opens and the gate 152 closes.
At this time, since the inverter 156 operates, the clock signal CLK0 (CLK1) latched by the first latch when the command flag signal F1 becomes HIGH earlier becomes
It is held in the second latch. Since the gate 152 is closed, even if the current clock signal CLK0 (CLK1) changes, the content held by the second latch does not change.

As described above, the latch of FIG. 7 operates at the rising edge of the command flag signal F1 at the rising edge of the clock signal C.
LK0 or CLK1 can be latched, and the latched content can be retained thereafter. In the above embodiment,
The configuration has been described in which it is determined whether or not skew exists using the command flag signal F1 input externally in synchronization with the rising edge of the clock signal CLK. This is merely an example, and the present invention is not limited to this. Needless to say, the same skew determination can be performed by using a signal input externally in synchronization with the falling edge of the clock signal CLK. In this case, the signals S0 and S1 are LO
At the time of W and HIGH, it may be determined that there is no skew (within a predetermined allowable range).
In the determination circuit 127 shown in FIG.
This can be realized only by changing the positions of

As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be freely modified and changed within the scope of the claims. is there.

[0067]

According to the present invention, the skew is generated in the input signal including the pulse signal by comparing the phase of the clock signal with the phase of the pulse signal input in synchronization with the clock signal. In such a case, the fact can be detected even during the normal operation. When a skew is detected during the normal operation as described above, the fact is notified to the outside, so that an external controller or the like can be notified that the phase adjustment for skew reduction is necessary. Also, in response to skew detection, shift from the normal mode to the calibration mode and allow the skew reduction circuit to readjust the phase of the input signal, so that signal timing deviation due to power supply voltage, temperature fluctuation, etc. during the normal operation mode Can be dealt with.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration of a skew detection circuit.

FIG. 3 is a timing chart showing a skew determination operation by a skew detection circuit.

FIG. 4 shows a case where a skew exceeding an allowable level exists.
5 is a timing chart illustrating a skew determination operation by a skew detection circuit.

FIG. 5 shows a case where a skew exceeding an allowable level exists.
5 is a timing chart illustrating a skew determination operation by a skew detection circuit.

FIG. 6 is a circuit diagram illustrating an example of a circuit configuration of a determination circuit of the skew detection circuit.

FIG. 7 is a circuit diagram illustrating an example of a circuit configuration of a latch.

FIG. 8 is a block diagram illustrating an example of a skew reduction circuit.

9 is a circuit diagram illustrating an example of a circuit configuration of the shift register in FIG.

FIG. 10 is a circuit diagram showing an example of a circuit configuration of the phase comparator of FIG.

FIG. 11 is a circuit diagram illustrating an example of a circuit configuration of the delay line in FIG. 8;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor memory device 101 skew detection circuit 102 skew reduction circuit 103 command / address control circuit 104 row decoder 105 column decoder 106 cell array circuit 107 sense amplifier 108 input / output control circuit 109 input / output buffers 121, 122 input buffers 123, 124 delay circuit 125 , 126 Latch 127 Judgment circuit 128 Output buffer

Claims (9)

[Claims] A phase comparison is made between a clock signal supplied from the outside and a pulse signal supplied from the outside in synchronization with the clock signal to determine a phase between the clock signal and the pulse signal. A semiconductor device comprising: a skew detection circuit for detecting a shift; and an output terminal for outputting a signal indicating whether or not the phase is shifted to the outside. And a skew reducing circuit for adjusting a phase of the input signal including the pulse signal in a calibration mode to reduce a skew of the input signal. In the normal operation mode, the skew detecting circuit detects a phase shift. 2. The semiconductor device according to claim 1, wherein upon detection, the phase of the input signal is readjusted by shifting to the calibration mode. 3. The skew detection circuit according to claim 1, wherein the skew detection circuit receives a pulse signal supplied from the outside in synchronization with a predetermined one of a rising edge and a falling edge of the clock signal. The semiconductor device according to claim 1. 4. The skew detection circuit includes a circuit for determining whether or not the input timing of the pulse signal is within a predetermined period before and after the input timing of the predetermined one edge. 4. The semiconductor device according to claim 3, wherein: 5. A circuit for generating a plurality of clock signals having a predetermined timing relationship with the clock signal based on the clock signal, the skew detection circuit comprising: a plurality of clock signals; A plurality of latch circuits for latching the clock signal of, and a determination circuit for detecting a phase shift between the clock signal and the pulse signal based on a combination of signal levels held by the plurality of latch circuits. 4. The semiconductor device according to claim 3, wherein: 6. A phase comparison between a clock signal supplied from the outside and a pulse signal supplied from the outside in synchronization with the clock signal, and the phase between the clock signal and the pulse signal is compared. A skew detection circuit for detecting a shift; and a skew reduction circuit for adjusting a phase of the input signal including the pulse signal in a calibration mode to reduce a skew of the input signal. A semiconductor device that shifts to the calibration mode to readjust the phase of the input signal when the shift is detected. 7. The skew detection circuit receives a pulse signal supplied from the outside in synchronization with one of a rising edge and a falling edge of the clock signal as the pulse signal. The semiconductor device according to claim 6. 8. The skew detecting circuit includes a circuit for determining whether or not the input timing of the pulse signal is within a predetermined period before and after the input timing of the predetermined one edge. The semiconductor device according to claim 7, wherein: 9. A circuit for generating a plurality of clock signals having a predetermined timing relationship with the clock signal based on the clock signal, the skew detection circuit; A plurality of latch circuits for latching the clock signal of, and a determination circuit for detecting a phase shift between the clock signal and the pulse signal based on a combination of signal levels held by the plurality of latch circuits. The semiconductor device according to claim 7, wherein: