JPH11186420A - Method for writing non-volatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve writing characteristics at the time of writing a charge (electron) in a floating gate. SOLUTION: This is a non-voltage semiconductor storage device provided with a memory cell array in which plural flash memory cell transistors constituted of a floating gate 4, control gate 6, drain area 7, source area 8, an channel area are arranged, and a method for writing the non-volatile semiconductor storage device for writing a charge (electron) in the floating gate 4 by hot electrons. At the time of allowing writing currents to flow to the selected flash memory cell transistor, the writing currents are allowed to flow through a non-selected flash memory cell transistor adjacent to the flash memory cell transistor 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a writing method for a nonvolatile semiconductor memory device, and more particularly, to a floating gate and a control gate formed so as to extend from an upper portion to a side portion of the floating gate. Data writing is performed by having a source / drain region on the surface of the substrate so as to be adjacent and storing hot electrons generated between the source / drain regions in the floating gate.
The present invention relates to a writing method of a nonvolatile semiconductor memory device called a so-called split gate type flash memory cell transistor.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory device in which a memory cell comprises a single transistor, in particular, a programmable ROM (EEPROM: Electronically Erasable an).
d Programmable ROM, also called flash memory. 3), each flash memory cell transistor is formed by a transistor having a double gate structure having a floating gate and a control gate. In the case of such a double-gate flash memory cell transistor, data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. Then, FN conduction (Fowle conduction) is performed via a tunnel oxide film (oxide film 3) between the floating gate and the control gate.
Data is erased by extracting charges (electrons) from the floating gate to the control gate by r-Nordheim tunneling.

FIG. 3 is a plan view of a flash memory cell transistor having a floating gate, and FIG. 4 is a sectional view taken along line XX of FIG. This figure shows a split gate structure in which the control gate 6 extends from the upper portion to the side portion of the floating gate 4 via the insulating film (the oxide film 3 and the selective oxide film 5). A plurality of isolation regions 2 made of a selectively thick oxide film (LOCOS) are formed in a strip shape in a surface region of a P-type silicon substrate 1 to partition an element region. On the silicon substrate 1,
Floating gate 4 is arranged so as to straddle between adjacent isolation regions 2 via oxide film 3. This floating gate 4 is arranged independently for each flash memory cell transistor. Further, the selective oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 by a selective oxidation method, and the end of the floating gate 4 is formed at an acute angle. This allows
At the time of data erasing operation, electric field concentration is easily caused at the end of the floating gate 4.

On the silicon substrate 1 on which a plurality of floating gates 4 are arranged, control gates 6 are arranged corresponding to each column of the floating gates 4. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3. The floating gate 4 and the control gate 6 are arranged such that adjacent rows are plane-symmetric with each other.

An N-type drain region 7 and a source region 8 are formed in the substrate region on the control gate 6 side and the substrate region on the floating gate 4 side. The drain region 7 is surrounded by the isolation region 2 between the control gates 6 and is independent, and the source region 8 is continuous in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a flash memory cell transistor composed of a floating gate transistor and a control gate transistor.

Then, on the control gate 6,
Aluminum wiring 10 is arranged via oxide film 9 in a direction crossing control gate 6. This aluminum wiring 10 is connected to drain region 7 through contact hole 11. Then, as shown in FIG. 5, each control gate 6 becomes a word line WL, and a source region 8 extending in parallel with the control gate 6 becomes a source line SL. The aluminum wiring 10 connected to the drain region 7 becomes the bit line BL, and the bit line B
L is connected to ground via a sense amplifier (not shown) and a MOS transistor 13 used when reading data. The MOS transistor 13 serves to set the write current of each flash memory cell transistor to a certain value.
It is set to 50 nA.

In the case of such a double gate flash memory cell transistor, the floating gate 4
The on-resistance value between the source and the drain fluctuates depending on the amount of charge injected into the device. Therefore, floating gate 4
The on-resistance value of a specific flash memory cell transistor is varied by selectively injecting electric charges into the memory cells, and a difference in operating characteristics of each flash memory cell transistor caused by the change is associated with data to be stored.

The above-described data write, erase, and read operations in the flash memory cell transistor are performed, for example, as follows. First, in the write operation, approximately 2 V is applied to WL2 to which the selected control gate 6 is connected, and the potential of the drain region 7 is changed to approximately 150 n by the write current (see the arrow in FIG. 6).
A value (for example, 0.8 V to 1.2 V), and the potential of the source region 8 is about 9 V. Further, 0 V is applied to WL1 to which the unselected control gate is connected. Thus, hot electrons generated near the gap between the floating gate 4 and the control gate 6 are accelerated toward the floating gate 4 and injected into the floating gate 4 through the oxide film 3 to write data.

Further, other bit lines, for example, BL1,
Since a potential of about 2.2 V, which is higher than about 2 V, is applied to the word line WL2 described above, no write current flows to other unselected flash memory cell transistors connected to the word line WL2. On the other hand, in the erasing operation, the potential of the drain region 7 and the source region 8 is set to 0V, and the control gate 6 is set to approximately 14V. As a result, charges (electrons) accumulated in the floating gate 4 penetrate through the tunnel oxide film from the acute corner of the floating gate 4 through FN conduction to the control gate 6, and data is erased. Is done.

In a read operation, the potential of the control gate 6 is set to about 4V, the drain area 7 is set to about 2V, and the source area 8 is set to 0V. At this time, if charges (electrons) are injected into the floating gate 4, the potential of the floating gate 4 becomes low, so that no channel is formed below the floating gate 4 and no drain current flows. Conversely, if charges (electrons) are not injected into the floating gate 4, the potential of the floating gate 4 increases, so that a channel is formed below the floating gate 4 and a drain current flows. Therefore, by detecting the current flowing from the drain region 7 by the sense amplifier, it is possible to determine whether the flash memory cell transistor is on or off, that is, determine the written data.

[0011]

In the above-mentioned flash memory cell transistor, the control gate 6 formed so as to extend from the upper portion to the side portion of the floating gate 4 has a conductive film formed so as to cover the floating gate 4. Then, the conductive film is formed by patterning using a dedicated mask, that is, since the floating gate 4 and the control gate 6 are not formed in a self-aligned manner, they are used as a mask in the process of processing the floating gate 4. On the other hand, if the mask in the process of processing the control gate 6 is misaligned, the gate length of the control gate transistor (see L1 and L2 in FIG. 7) between the adjacent flash memory cell transistors with the source region 8 interposed therebetween is reduced. Change, emit hot electrons when writing Electric field may change to, also,
When the degree of overlap between the floating gate 4 and the control gate 6 changes, the capacitance ratio between the capacitance between the floating gate 4 and the control gate 6 and the capacitance between the floating gate 4 and the source region 8 changes.

As a result, the write characteristics of each flash memory cell transistor become asymmetric. That is, FIGS. 8 and 9 are characteristic diagrams showing the write characteristics of the respective flash memory cell transistors. In the above-described write operation, the potential of the selected control gate 6 is set to 2 V and the potential of the drain region 7 is set to Various values (8 V, 9 V, 10 V, 11 V) of the source region 8 are set to a value at which the write current (Icell) becomes 150 nA, and hot electrons generated near the gap between the floating gate 4 and the control gate 6 generate floating electrons. 4 shows a write time (Program Time) until a predetermined amount of charge (electrons) is written into the floating gate 4 through the oxide film 3 after being accelerated to the side 4. For example, as described above, when writing is performed by setting the potential of the source region 8 to 9 V, the first flash memory cell transistor (hereinafter, word line W shown in FIG.
This refers to a flash memory cell transistor to which L1 is connected. ) Read current (Cell Current) I
The write time when r is 0.1 μA is about 18 μsec.
At c (point A shown by a two-dot chain line in FIG. 9), a second flash memory cell transistor (hereinafter referred to as a word line W shown in FIG. 7).
This refers to a flash memory cell transistor to which L2 is connected. ) Takes about 30 μsec (point B indicated by a two-dot chain line in FIG. 9) when the read current Ir becomes 0.1 μA.

That is, in order for both the flash memory cell transistors to have a read current Ir of 0.1 μA, the flash memory cell transistor having a lower write characteristic (here, the second flash memory cell transistor) must be used. Since a corresponding writing time (for example, about 30 μsec) was required, there was a problem that the writing time was long. In addition, excessive writing is performed on the flash memory cell transistor having good writing characteristics, and charge (electrons) extracted during the erasing operation of the flash memory cell transistor is concerned.
, The stress degradation of the tunnel oxide film is accelerated and the life of the flash memory cell transistor is shortened. Therefore, there has been a demand to improve the variation in the write characteristics between the two flash memory cell transistors.

Accordingly, the present invention provides a flash memory cell transistor adjacent to a source region, which is caused by misalignment of a mask in a process of processing a control gate with respect to a mask in a process of processing a floating gate. It is an object of the present invention to provide a nonvolatile semiconductor memory device having improved write characteristics by suppressing variations in the write time when writing charges (electrons) to each floating gate.

[0015]

According to the present invention, there is provided a writing method for a nonvolatile semiconductor memory device, comprising: a floating gate, a control gate, a drain region, and a source region;
A flash memory cell transistor including a plurality of flash memory cell transistors, each of which includes a plurality of flash memory cell transistors and a channel region, wherein charge (electrons) is written to the floating gate 4 by hot electrons. Word lines WL2, WL1 'connected to the respective control gates 6, 6 of the unselected flash memory cell transistors adjacent to the drain region 7 of the transistor
Is turned on by applying a predetermined potential (for example, 2 V) to the source region 8 of the selected flash memory cell transistor.
By applying a potential (for example, 9 V) sufficient to generate the hot electrons to the selected flash memory cell transistor, a write current generated when writing electric charges (electrons) to the selected flash memory cell transistor is applied to the selected flash memory cell transistor. From the source region 8 to the drain region 7 through the channel region, and further via the drain region 7, the channel region of the adjacent unselected flash memory cell transistor, and the source region 8 of the unselected flash memory cell transistor. It is characterized by flowing to

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The planar and cross-sectional structures of the nonvolatile semiconductor memory device of the present invention are the same as the structures shown in FIGS. The features of the present invention are:
As shown in FIG. 1 and FIG. 2, an unselected flash memory cell transistor adjacent to the drain region 7 side of the flash memory cell transistor selected during the write operation (flash memory cell transistor surrounded by a dotted circle in FIG. 2) This means that a write current (see an arrow in FIG. 1) flows through the memory. This is because when the selection gate length of the flash memory cell transistor selected due to the mask shift becomes long, the selection gate length of the flash memory cell transistor adjacent to the drain region 7 side becomes short, and conversely, the selection is made. When the select gate length of the flash memory cell transistor becomes short, the fact that the select gate length of the flash memory cell transistor adjacent to the drain region 7 side is long is utilized. That is, when writing to a flash memory cell transistor with a short select gate length that is easy to write, a write current is passed through a flash memory cell transistor with a short select gate length and a small current driving capability. When writing data to a flash memory cell transistor having a long select gate length, which is difficult to write, a write current is passed through a flash memory cell transistor having a short select gate length having a large current driving capability.

The operations of writing, erasing, and reading data in the flash memory cell transistor described above are performed, for example, as follows. First, a description will be given of a control method of writing data into the flash memory cell transistors surrounded by the dotted circle shown in FIG. The word lines WL2 and WL1 'to which the selected flash memory cell transistor and the unselected flash memory cell transistor adjacent to the drain region 7 of the flash memory cell transistor are connected are turned on by applying, for example, 2V to the other word lines. 0 V is applied to the lines (the word lines WL1 and WL2 'are illustrated in FIG. 2). The source line SL connected to the source region 8 of the selected flash memory cell transistor has a sufficient potential for generating hot electrons, for example, 9V.
And 1.2 V is applied to other source lines (the source line SL ′ is illustrated in FIG. 2). Further, the bit line BL0 is opened, and 2.2V is applied to other bit lines (the bit line BL1 is illustrated in FIG. 2).

In the flash memory cell transistor connected to the selected word line WL2, the threshold voltage is about 0.5V. Therefore, in the flash memory cell transistor, the electrons in the source region 8 move into the channel region in the inverted state. Therefore, the write current (Ice
ll) flows, and the write current further flows to the source line SL 'via the channel region of the non-selected flash memory cell transistor connected to the adjacent word line WL1' via the drain region 7.

On the other hand, the potential of the source region 8 adjacent to the selected flash memory cell transistor is about 9 V
Therefore, the potential of the floating gate is raised to about 7 V by the coupling between the source region 8 and the floating gate 4 via the capacitance. Therefore, electrons in the channel region are accelerated to become hot electrons, and are injected into the floating gate 4. As a result, charges (electrons) are accumulated in the floating gate 4 of the flash memory cell transistor,
One-bit data is written and stored.

Further, another bit line (bit line BL in FIG. 2)
1 is exemplified. ) Is applied with the potential of the word line WL2, that is, about 2.2 V, which is higher than about 2 V, so that no write current flows to other unselected flash memory cell transistors connected to the word line WL2. The write current also flows through the unselected flash memory cell transistor connected to the word line WL1 ', but the potential of the floating gate 4 strongly capacitively coupled to the source SL' is set to the potential of the selected flash memory cell transistor. Charge (electrons) is not injected into the floating gate 4.

On the other hand, in the erase operation, the potential of the drain region 7 and the source region 8 of the selected flash memory cell transistor is set to 0 V, and the control gate 6 is set to 14 V, as in the conventional case. As a result, charges (electrons) accumulated in the floating gate 6 penetrate through the tunnel oxide film from the acute corner of the floating gate 4 by FN conduction to the control gate 6, and data is erased. Is done.

The read operation is the same as in the prior art. The potential of the control gate 6 is 4 V, the drain region 7 is 2 V, and the source region 8 is 0 V. At this time, if charges (electrons) are injected into the floating gate 4, the potential of the floating gate 4 becomes low, so that no channel is formed below the floating gate 4 and no drain current flows. Conversely, if charges (electrons) are not injected into the floating gate 4, the potential of the floating gate 4 increases, so that a channel is formed below the floating gate 4 and a drain current flows. Therefore, by detecting the current flowing from the drain region 7 by the sense amplifier, it is possible to determine whether the flash memory cell transistor is on or off, that is, determine the written data.

As described above, in the present invention, when the mask in the step of processing the control gate 6 is misaligned with the mask in the step of processing the floating gate 4, the flash memory adjacent to the source region 8 is sandwiched. The gate length of the control gate / transistor between cell transistors (see L1 and L2 in FIG. 7) changes, the electric field generating hot electrons at the time of writing changes, and the degree of overlap between the floating gate 4 and the control gate 6 decreases. By changing
In order to suppress variations in write characteristics due to a change in the capacitance ratio between the capacitance between the floating gate 4 and the control gate 6 and the capacitance between the floating gate 4 and the source region 8, adjacent flash memory cell transistors having different gate lengths are used. Utilization of each other suppresses variation in writing characteristics. That is, when writing to a flash memory cell transistor with a long select gate length that is difficult to write, a write current is passed through a flash memory cell transistor with a short select gate length that has a large current driving capability, and the select gate length that is easy to write is short. When writing to a flash memory cell transistor, a write current is passed through a flash memory cell transistor having a small current driving capability and a long select gate length,
Variation in writing characteristics can be suppressed.

Further, according to the present invention, unnecessary writing to a flash memory cell transistor having good write characteristics can be prevented under the write conditions corresponding to the conventional flash memory cell transistor having poor write characteristics. Can be solved. Therefore, the number of charges (electrons) extracted from the floating gate during the erasing operation can be reduced, so that a reduction in lifetime due to stress deterioration of the tunnel oxide film can be suppressed. Therefore, the life of the flash memory cell transistor can be improved.

[0025]

According to the nonvolatile semiconductor memory device of the present invention, when writing to a flash memory cell transistor having a long select gate length which is difficult to write, a flash memory cell transistor having a large current drive capability and a short select gate length is used. When writing into a flash memory cell transistor with a short select gate length, which is easy to write, a write current is passed through a flash memory cell transistor with a long select gate length, which has a small current driving capability, and the The mask in the process of processing the control gate is misaligned with the mask in the process of processing the floating gate, as shown in the figure. When writing charge It is possible to improve the writing characteristic by suppressing variation in writing characteristics.

In addition, the problem of excessively writing to a flash memory cell transistor having good write characteristics caused by setting the write condition corresponding to a flash memory cell transistor having poor write characteristics unlike the prior art is eliminated. In some cases, the number of electrons withdrawn from the floating gate can be reduced, so that a reduction in life due to stress deterioration of the tunnel oxide film can be suppressed, and thus the life of the flash memory cell transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a writing method of the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a plan view for explaining a conventional nonvolatile semiconductor memory device.

FIG. 4 is a sectional view taken along line XX of FIG. 3;

FIG. 5 is a cross-sectional view for explaining a conventional nonvolatile semiconductor memory device.

FIG. 6 is a circuit diagram for explaining a writing method of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a circuit diagram for explaining a problem of a conventional nonvolatile semiconductor memory device.

FIG. 8 is a characteristic diagram for describing write characteristics of a first memory cell transistor.

FIG. 9 is a characteristic diagram for explaining write characteristics of a second memory cell transistor;

Claims (2)

[Claims] A memory cell array in which a plurality of flash memory cell transistors each including a floating gate, a control gate, first and second impurity diffusion regions and a channel region are arranged, and the floating gate is charged by hot electrons. A writing method of a nonvolatile semiconductor memory device for writing electrons), wherein a non-selected flash memory cell transistor adjacent to a first impurity diffusion region of the selected flash memory cell transistor when a write current is applied to the selected flash memory cell transistor A write current flowing through the memory device. 2. A memory cell array in which a plurality of flash memory cell transistors each including a floating gate, a control gate, first and second impurity diffusion regions, and a channel region are arranged. A writing method of the nonvolatile semiconductor memory device for writing electrons), wherein a selected flash memory cell transistor and each control gate of an unselected flash memory cell transistor adjacent to the first impurity diffusion region of the flash memory cell transistor are respectively provided. The word line to be connected is turned on by applying a predetermined potential, and a potential sufficient to generate the hot electrons is applied to the second impurity diffusion region of the selected flash memory cell transistor, so that the selected flash memory cell transistor is turned on. Charge Shrewsbury memory cell transistor second flash memory cell transistor a write current for generating the said selected when writing (electronic)
From the impurity diffusion region through the channel region to the first impurity diffusion region, and further via the first impurity diffusion region, the channel region of an unselected flash memory cell transistor, and the unselected flash memory A writing method for a non-volatile semiconductor storage device, characterized by flowing a current to a second impurity diffusion region of a cell transistor.