JPH11184763A - Logging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a logging device for surely obtaining an event being the cause of abnormality. SOLUTION: When a CPU 12 commands data transmission to an outside device to an input and output device 16, the input and output device 16 outputs a start signal to a buffer controller 20 prior to the transmission of an REQ (transmission request) signal to the outside device. The buffer controller 20 which inputs the start signal starts the output of a write signal to a ring buffer 18, and then the REQ signal, ACK (acknowledge) signal, and data are stored (overwrite) as log information in the ring buffer 18. At that time, a sub-timer 22 outputs a stop signal to the buffer controller 20 when an ACK signal response time is over the previous ACK signal response time based on an enable signal or the like inputted from the buffer controller 20. The buffer controller 20 which inputs the stop signal falls the write signal, and stops the storage of the log information in the ring buffer 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a logging device, and more particularly, to a logging device for collecting log information of an input / output device that communicates with an external device.

[0002]

2. Description of the Related Art Conventionally, when a failure or other failure occurs in an input / output device such as a hard disk device or a printer that communicates with another device, a communication signal or hardware status is logged in order to investigate the cause. Things to do are being done. Among them, a technique of detecting an abnormality by a timeout detection mechanism and logging the state of the apparatus at the time of occurrence of the timeout by hardware or software is disclosed in Japanese Patent Application Laid-Open Nos. 5-53881 and 5-53881.
No. 46497.

[0003] JP-A-5-53881 and JP-A-5-53881
The technology described in Japanese Patent No. 46497 discloses a technology in which a time-out occurs in a predetermined time for each technology to obtain information at the time of occurrence of the time-out.

However, Japanese Patent Application Laid-Open No. 5-53881 describes
However, the technology described in Japanese Patent Application Laid-Open No. 5-46497 and Japanese Patent Application Laid-Open No. 5-46497 have a problem that an event causing an abnormality may not be captured. A specific example is shown below.

FIG. 7 shows a time chart when a timeout occurs due to an abnormality of the REQ signal (transmission request signal) during data transfer. In the system of interest here, the slave device issues a transfer request with the REQ signal, and the master device responds to the REQ signal with an ACK signal (acknowledge signal). The figure shows a case where the device on the side transmits data to the bus together with the REQ signal, and the device on the master side performs data transfer for receiving the data.

As shown in FIG. 7, the ACK signal is distorted due to noise or the like at the time point A, so that the slave device cannot recognize the ACK signal and continues to transmit the REQ signal, resulting in timeout. In this case, even if the REQ signal and the ACK signal are sampled when the timeout occurs, it is only known that the REQ signal is enabled and the ACK signal is disabled. For this reason, there is a possibility that the cause of the abnormality is erroneously recognized as an abnormality of the master device that does not transmit the ACK signal in response to the REQ signal.

FIG. 8 shows a time chart when a timeout occurs due to an abnormality in the communication control signal.
The target system here is a host computer and an input / output device (device) through a channel interface which is a kind of communication bus of the host computer.
In this system, the orbiter gives the bus user permission by the HOLDO signal during communication and the bus user indicates to the other device by the OPIN signal that the bus is being used. . On the other hand, when the HOLDO signal drops, the bus user needs to immediately drop the OPIN signal to release the bus.

[0008] As shown in FIG. 8, at the time A during which the device is returning the status to the host computer by the STAI signal, the HOLDO signal is momentarily interrupted due to a malfunction of another device, and the device releases the bus. On the other hand, the host computer does not recognize the instantaneous interruption, and continues to wait for the status from the device without transmitting the SRVO signal that must be transmitted in response to the STAI signal. Timed out. Also in this case, when the timeout occurs, there is a possibility that the device may mistakenly release the bus without returning the status.

As a technique for solving the above problems, there is a technique for constantly logging a communication signal to a buffer memory by hardware. Hereinafter, an outline of this technique will be described.

[0010] Logging system 10A according to this technique
As shown in FIG. 9, a CPU 12A for controlling the entire logging system 10A, a timeout detection unit 14 for detecting a timeout, and communication of an REQ signal, an ACK signal, and the like with an external device (not shown) under the control of the CPU 12. An input / output device 16 for transmitting and receiving an input / output signal 30 including a control signal and data;
A buffer unit 18A that stores the input / output signal 30 as log information based on a write signal 32 input from a buffer control unit 20A, which will be described later.
It is configured to include a buffer control unit 20A that generates a write signal 32 to 8A, and the components are interconnected via a bus 24.

The logging system 1 configured as described above
At 0A, as shown in the time chart of FIG. 10, when communication starts between the input / output device 16 and an external device (not shown), the buffer control unit 20A sends the write signal 32 of a predetermined cycle to the buffer unit 18A. By starting the output, the storage of the input / output signal 30 in the buffer unit 18A is started, and when the input / output signal 30 is stored in the entire use area of the buffer unit 18A, the storage is started again from the head address of the buffer unit 18A. By performing (overwriting), storage of the input / output signal 30 is continuously performed. “N-th round” in FIG. 10 indicates that the n-th overwrite is being performed.

Thereafter, when the timeout occurs, the storage of the input / output signal 30 is stopped.
The cause of the abnormality is searched for by referring to the input / output signal 30 (log information) stored in 8A.

[0013]

However, in the technique of constantly logging the communication signal to the buffer memory by the above-described hardware, the overwriting is performed when the input / output signal 30 is stored in the entire use area of the buffer unit 18A. Is performed, the input / output signal 30 previously stored in the buffer unit 18A disappears. In FIG.
The abnormal input / output signal 30 stored in the buffer unit 18A in the n-th overwrite is further overwritten (two overwrites in FIG. 10) until the time-out occurs, and has disappeared. .

Normally, the system timeout value (a value corresponding to the time until a timeout occurs) is set to a relatively large value which can be said to have clearly caused some abnormality. On the other hand, the sampling period of the input / output signal 30 needs to be a relatively small value in order to reliably detect an abnormality. In FIG. 10, for example, the ACK signal response time (the time from the rise of the REQ signal to the rise of the ACK signal corresponding to the REQ signal) is 100 n.
Assuming that the sampling period of the input / output signal 30 is 50 ns and the timeout value is 5 ms, a buffer unit 18A having a storage capacity of 100,000 entries is required to capture the event of the occurrence of the abnormality.

There is also a method in which sampling of the input / output signal 30 is not periodically performed, but sampling is performed at a change point of the input / output signal 30. This method is used after the occurrence of an abnormality. Is effective when the value does not change. However, the reset or timeout caused as a result of the external device communicating with another device after the occurrence of the error or continuing the wrong sequence due to the error of the input / output signal 30 is not effective. As described above, the problem of the storage capacity of the buffer unit 18A occurs. An example of this case will be described with reference to FIG. The target system is a system in which a host computer and input / output devices (devices) are connected by the same channel interface as the system described with reference to FIG.

As shown in FIG. 11, in this example, at the point A in the process of returning data or status from the device to the host computer, an abnormality occurs in the SRVO signal when only the CMDO signal is originally returned. Has caused a sequence error, and has subsequently been reset from the host computer. In this case, the host computer is communicating with other devices after the occurrence of the error,
There is a danger of losing data in the event of an error.

As described above, in the conventional logging device in which the trigger of logging depends only on a predetermined timeout value, it may not be possible to catch a true cause event in the analysis of the cause at the time of abnormality. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a logging device that can reliably capture an event that causes an abnormality.

[0019]

According to another aspect of the present invention, there is provided a logging device, comprising: a history of signals on a bus to which an input / output device for communicating with an external device is connected; And storage means for storing at least one history of the history of signals transmitted and received between the external device,
From the time when the call signal is transmitted from the input / output device to the external device, the history is stored in the entire use area of the storage means for a time or more in which a response signal corresponding to the call signal can be received in a normal state. Timing generation means for generating a stop signal indicating a timing at which the storage of the history is stopped when a predetermined time equal to or less than a predetermined time elapses, and from a time when communication between the input / output device and the external device is started. The storage unit is configured to sequentially store the history, and when the history is stored in the entire use area of the storage unit, is controlled to continue storing the history by overwriting,
Control means for controlling the storage of the history in the storage means to be stopped based on the stop signal generated by the timing generation means.

In the logging device according to the first aspect, the history of signals on a bus to which an input / output device for communicating with an external device is connected and the history of signals transmitted / received between the input / output device and the external device are recorded. A storage unit capable of storing at least one history is provided.

[0021] Further, after the time when the calling signal is transmitted from the input / output device to the external device by the timing generating means, it is longer than a time during which a response signal corresponding to the calling signal can be received in a normal state, and the use of the storage means is performed. When a predetermined time equal to or less than the time for storing the history in the entire area has elapsed, a stop signal indicating the timing to stop storing the history is generated. The call signal at this time corresponds to the REQ signal in the system described with reference to FIGS. 7 and 10, and the STAI signal in the systems described with reference to FIGS. The response signal is
The ACK signal is output in the system described with reference to FIGS. 7 and 10, and the SRV signal is output in the system described with reference to FIGS.
The O signal corresponds.

Further, the history is sequentially stored in the storage means from the time when the communication between the input / output device and the external device is started by the control means, and when the history is stored in the entire use area of the storage means, it is superimposed. Control is performed so that the storage of the history is continued by writing (overwriting), and the storage of the history in the storage unit is controlled based on the stop signal generated by the timing generation unit.

As described above, according to the logging device of the first aspect, the collection of the signal history (log information) to the storage means is stopped when a predetermined time has elapsed from the time when the call signal was transmitted. , The signal history at the time of occurrence of the abnormality is not lost, and the event causing the abnormality can be reliably captured.

According to a second aspect of the present invention, there is provided a logging device, wherein a history of signals on a bus to which an input / output device for communicating with an external device is connected, and transmission / reception between the input / output device and the external device. Storage means for storing at least one of the signal histories; and timing generation for generating a start signal indicating a timing to start storing the history each time a call signal is transmitted from the input / output device to the external device. Means for storing the history at the time when the history is stored in the entire use area of the storage means after the storage of the history in the storage means is started every time the start signal is generated by the timing generation means. And control means for controlling to stop.

In the logging device according to the second aspect, the history of signals on the bus to which the input / output device that performs communication with the external device is connected and the history of signals transmitted and received between the input / output device and the external device are recorded. A storage unit capable of storing at least one history is provided.

The timing generating means generates a start signal indicating the timing of starting the storage of the history every time a call signal is transmitted from the input / output device to the external device. The call signal at this time corresponds to the REQ signal in the system described with reference to FIGS. 7 and 10, and the STAI signal in the systems described with reference to FIGS.

Further, the control means starts storing the history in the storage means every time the start signal is generated by the timing generation means, and then stops storing the history when the history is stored in the entire use area of the storage means. Is controlled.

Thus, according to the logging device of the second aspect, every time a call signal is transmitted, the collection of the signal history (log information) to the storage means is started and then the history is stored in the entire use area of the storage means. Since the storage of the history is stopped at the point in time, the signal history at the time of occurrence of the abnormality due to overwriting is not lost, and the event causing the abnormality can be reliably captured.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings. Hereinafter, a case where the logging device of the present invention is applied as a logging system including an input / output device will be described.

[First Embodiment] As shown in FIG. 1, a logging system 10 according to the first embodiment comprises a CPU 1
2. It includes a system memory 15, an input / output device 16, a ring buffer 18, a buffer controller 20, and a sub-timer 22. The components are interconnected by a bus 24.

The input / output device 16 is connected to an external device (not shown).
A communication control signal such as a CK signal and data are transmitted and received.
The input / output device 16 is also connected to the buffer controller 20 and outputs a start signal indicating the start of communication with an external device to the buffer controller 20.

The ring buffer 18 is used for the input / output device 1.
6, a terminal for transmitting a REQ signal to an external device, a terminal for receiving an ACK signal from the external device, and a terminal for transmitting and receiving data to and from the external device. Can be entered.

The buffer controller 20 is connected to a terminal for transmitting an REQ signal to an external device of the input / output device 16 and a terminal for receiving an ACK signal from the external device, and is also connected to the ring buffer 18 and the sub-timer 22. , REQ signal and ACK signal input, sub-timer 2 for enable signal, clear signal and load signal generated based on the input REQ signal and ACK signal
2, an input of a stop signal generated by the sub-timer 22 based on the enable signal, the clear signal, and the load signal, and a start signal input from the input / output device 16 and a stop signal input from the sub-timer 22. The generated write signal is output to the ring buffer 18.

The write signal generated by the buffer controller 20 is enabled by a start signal input from the input / output device 16 and disabled by a stop signal input from the sub-timer 22.
In the first embodiment, the occurrence of the timeout is determined by the CP
Detected by U12.

The ring buffer 18 serves as the storage means of the present invention, and the buffer controller 20 serves as the control means of the present invention.
The sub-timer 22 provides the timing generation means of the present invention with RE
The Q signal corresponds to the calling signal of the present invention, the ACK signal corresponds to the response signal of the present invention, and the stop signal corresponds to the stop signal of the present invention.

FIG. 2 shows a detailed configuration of the sub-timer 22 in FIG. As shown in the figure, the sub-timer 22 has an offset register 4 for temporarily storing an offset value input from the CPU 12 via the bus 24.
0 is provided.

The sub-timer 22 receives the enable signal and the clear signal 1 output from the buffer controller 20 and a predetermined clock signal from an enable terminal (Enab).
The counter 42 is input to a le terminal), a clear terminal (Clear terminal), and a clock terminal (CLK terminal). The counter 42 is constituted by an up counter, and an enable signal generated by the buffer controller 20 to start counting when the REQ signal rises and to stop counting when the ACK signal corresponding to the REQ signal rises. Is started and stopped on the basis of. That is, in the counter 42, the time from the rising edge of the REQ signal to the rising edge of the ACK signal corresponding to the REQ signal (hereinafter referred to as A)
CK signal response time).

The Q terminal for outputting the count value of the counter 42 is connected to one input terminal of the adder 44, and the other input terminal of the adder 44 is connected to the terminal for outputting the offset value of the offset register 40. The output terminal of the adder 44, which outputs the added value, receives an enable signal, a load signal and a clear signal 2 output from the buffer controller 20, and a predetermined clock signal, respectively, an enable terminal (Enable terminal) and a load terminal ( Load terminal), Clear terminal (Clear terminal), and Clock terminal (CLK terminal)
Is connected to the D terminal (terminal for inputting the load data) of the counter 46 input to the counter 46. Accordingly, the adder 44 adds the count value of the counter 42 to the offset value stored in the offset register 40, and outputs the addition result to the D terminal of the counter 46.

The terminal C for outputting the stop signal of the counter 46 is connected to the buffer controller 20 as described above.
And outputs the stop signal generated by the counter 46 to the buffer controller 20. The counter 46 is constituted by a down counter, and clearing of the count value and loading of the initial value from the D terminal are executed by the clear signal 2 and the load signal input from the buffer controller 20. The counter 46 counts down after loading an initial value from the D terminal, and outputs a stop signal to the buffer controller 20 when the count value becomes 0.

Next, the operation of the logging system 10 configured as described above will be described with reference to the time charts of FIGS.

When the CPU 12 instructs the input / output device 16 to transmit data, as shown in FIG.
Reference numeral 6 outputs a start signal to the buffer controller 20 before transmitting the REQ signal. The buffer controller 20 to which the start signal has been input is the ring buffer 1
The output of the write signal to 8 starts. As a result, the input / output device 16
The REQ signal, the ACK signal, and the data transmitted and received between and the external device (not shown) are stored (collected) as log information.

Thereafter, the buffer controller 20 clears the counters 42 and 46 of the sub-timer 22 by generating the clear signals 1 and 2 and
At the same time as transmitting the REQ signal, it outputs an enable signal to the counter 42 and the counter 46. Therefore, at this time, the counter 42 starts counting up from 0, and the counter 46 starts counting down from 0.

When an ACK signal is received from an external device (not shown), the buffer controller 20 lowers the enable signal output to the counter 42 and the counter 46, and then outputs a load signal to the counter 46. . As a result, the counter 46 stores the count value of the counter 42 at this time, that is, the count value corresponding to the first ACK signal response time, in the offset register 4.
A value obtained by adding a preset offset value to 0 is loaded.

Thereafter, the buffer controller 20 inputs the clear signal 1 to the counter 42 to clear the count value of the counter 42, and then, when the next REQ signal is input, the counter 42 and the counter 4 of the enable signal again.
6. Output to 6 starts.

Therefore, the counter 42 starts counting up from 0 from the rise of the REQ signal, and the counter 46 starts counting down from the count value obtained by adding the offset value to the count value corresponding to the previous ACK signal response time. I do.

Thereafter, the buffer controller 20
The operation after the above-mentioned ACK signal is received, that is, A
After the enable signal falls when the CK signal is input, the clear signal 1 is input to the counter 42 after the load signal is output to the counter 46, and the next RE is output.
The operation of outputting the enable signal again when the Q signal is input is repeatedly performed.

At some point, as shown in FIG. 4, when the ACK signal becomes slower than usual due to the external device, the ACK signal response time is offset by the count value of the counter 42 corresponding to the previous ACK signal response time. When the time becomes longer than the time corresponding to the added value, the count value of the counter 46 becomes 0 and a stop signal is output to the buffer controller 20.

The buffer controller 20 to which the stop signal has been input stops the collection of the log information in the ring buffer 18 by causing the write signal output to the ring buffer 18 to fall.

Thereafter, if an ACK signal is received before the CPU 12 times out,
The counter 46 counts down again after the initial value is loaded by the K signal as a trigger, so that the output of the stop signal to the buffer controller 20 is stopped, and the buffer controller 20 sends the write signal to the ring buffer 18 again. Start output and ring buffer 18
Collection of log information to the server is restarted.

On the other hand, as shown in FIG. 5, when the ACK signal is distorted due to noise or the like and the input / output device 16 cannot recognize the ACK signal (at time A in FIG. 5), the counter is operated in the same manner as described above. 46 outputs a stop signal to the buffer controller 20 when a time corresponding to a value obtained by adding the offset value to the count value of the counter 42 corresponding to the previous ACK signal response time has elapsed.

The buffer controller 20 to which the stop signal has been input stops the collection of log information to the ring buffer 18 by causing the write signal output to the ring buffer 18 to fall.

If a timeout is detected by the CPU 12 in this state, C is set when the timeout occurs.
The PU 12 reads out the log information from the ring buffer 18 and stores it in the system memory 15. Therefore, the log information finally stored in the system memory 15 includes the REQ signal and the ACK signal at the time when the ACK signal is distorted.

As described above in detail, in the logging system according to the first embodiment, when the time based on the previous ACK signal response time has elapsed since the transmission of the REQ signal, the log to the ring buffer 18 is transmitted. Since the collection of the information is stopped, the log information at the time of occurrence of the abnormality due to the overwriting is not lost, and the event causing the abnormality can be reliably captured.

In the first embodiment, the previous ACK
The case where the collection of log information in the ring buffer 18 is stopped based on the signal response time has been described. However, the present invention is not limited to this. For example, the use of the ring buffer 18 may be started from the rising of the REQ signal. The collection may be stopped when the time for collecting the log information has elapsed in the entire area.

[Second Embodiment] In the second embodiment, a mode in which the stop signal output from the sub-timer 22 in the first embodiment is used as a logging start signal will be described. The configuration of the logging system according to the second embodiment is the same as that of the logging system 10 according to the first embodiment, and a description thereof will not be repeated.

The logging system 1 according to the second embodiment
In the case of 0, a two's complement of a desired offset value is set in advance in the offset register 40 in FIG. 2 as an offset value. Thus, the adder 44 causes the counter 4
A value obtained by subtracting the offset value from the count value of 2 is loaded into the counter 46.

In the logging system 10 according to the second embodiment, the stop signal output from the sub-timer 22 to the buffer controller 20 is transmitted to the ring buffer 1.
8 is used as a signal instructing the start of log information collection, that is, a signal corresponding to the start signal of the present invention.

In the buffer controller 20 according to the second embodiment, the output of the write signal to the ring buffer 18 does not start even if the start signal is input from the input / output device 16, and the stop signal is input from the counter 46. At this time, the output of the write signal to the ring buffer 18 is started, and thereafter, when the collection of the log information for the entire storage capacity of the ring buffer 18 is completed, the write signal falls.

Therefore, as shown in FIG. 6, the ring buffer 18 stores the signal A from the time when the REQ signal rises.
The log information corresponding to the storage capacity of the ring buffer 18 is collected from a point in time when a time SC corresponding to a value obtained by subtracting the offset value OS from the count value BC corresponding to the CK signal response time has elapsed. However, during the collection of this log information, the next RE
If the time SC has elapsed from the transmission of the Q signal, the collection of log information into the ring buffer 18 is restarted from the head address of the ring buffer 18 and overwritten.

Therefore, in this case, the log information is overwritten in the ring buffer 18 while the transmission and reception of the REQ signal and the ACK signal between the input / output device 16 and the external device (not shown) are normally performed. ACK
When the signal is distorted due to noise or the like, and the input / output device 16 cannot recognize the ACK signal (at the time point A in FIG. 6).
In this case, the REQ signal thereafter rises, and the collecting operation ends after collecting the log information that can be stored in the entire storage capacity of the ring buffer 18. Therefore, the time period including the time point A Log information remains in the ring buffer 18, and the event causing the abnormality can be reliably captured.

As described in detail above, in the logging system according to the second embodiment, every time the REQ signal is transmitted, the log information is collected into the ring buffer 18 and then the amount of the used area of the ring buffer 18 is reduced. Since the collection of the log information is stopped when the log information is collected, the log information at the time of occurrence of the abnormality due to overwriting is not lost, and the event that causes the abnormality can be reliably captured.

In the second embodiment, a case has been described in which the collection of log information into the ring buffer 18 is started from the time when the time based on the previous ACK response time has elapsed since the transmission of the REQ signal. However, the present invention is not limited to this. For example, a mode may be adopted in which sampling is started at the same time as transmitting a REQ signal.

In each of the above embodiments, the input / output device 1
Although a case has been described in which a signal transmitted and received between the device 6 and an external device (not shown) is collected as log information in the ring buffer 18, the present invention is not limited to this. The log information may be collected in the input / output device 16.
A configuration may be adopted in which both the signal transmitted and received between the external device (not shown) and the signal on the bus 24 are collected in the ring buffer 18 as log information.

Further, in each of the above-described embodiments, the REQ transmitted from the input / output device 16 to the external device (not shown) is used.
The case where the present invention is applied to a system that returns an ACK signal from an external device according to a signal has been described. However, the present invention is not limited to this, and can be applied to any other system that performs handshake control.

[0065]

As described above, according to the logging device of the first aspect, the collection of the signal history (log information) to the storage means is stopped when a predetermined time has elapsed from the time when the calling signal was transmitted. Therefore, there is an effect that an event causing an abnormality can be reliably captured without losing a signal history at the time of occurrence of an abnormality due to subsequent overwriting.

Further, according to the logging device of the present invention, each time a call signal is transmitted, the collection of the signal history (log information) to the storage means is started and then the history is stored in the entire use area of the storage means. Since the storage of the history is stopped in the step (1), the signal history at the time of occurrence of the abnormality due to the overwriting is not lost, and the effect of causing the abnormality can be reliably captured.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a logging system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a sub timer in the logging system shown in FIG.

FIG. 3 is a time chart showing an operation at the start of communication in the logging system according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a logging system according to the first embodiment of the present invention, in which an REQ signal and an ACK signal are normally transmitted and received between an input / output device and an external device;
FIG. 9 is a time chart of a Q signal and an ACK signal, and a diagram showing a state of collecting log information at this time.

FIG. 5 is a diagram illustrating a REQ signal and an ACK signal transmitted and received between the input / output device and the external device in the logging system according to the first embodiment of the present invention;
FIG. 9 is a time chart of a signal and an ACK signal, and a state of collecting log information at this time.

FIG. 6 is a diagram illustrating a REQ when an REQ signal and an ACK signal are not normally transmitted and received between an input / output device and an external device in the logging system according to the second embodiment of the present invention;
FIG. 9 is a time chart of a signal and an ACK signal, and a state of collecting log information at this time.

FIG. 7 is a time chart showing an example of a case where an event causing an abnormality cannot be caught in the related art.

FIG. 8 is a time chart showing another example in the case where the event causing the abnormality cannot be caught in the related art.

FIG. 9 is a block diagram showing a configuration of a conventional logging system.

FIG. 10 is a time chart used to explain a problem in the logging system shown in FIG. 9;

FIG. 11 is a time chart used to explain another problem in the logging system shown in FIG. 9;

[Explanation of symbols]

 Reference Signs List 10 logging system 12 CPU 16 input / output device 18 ring buffer (storage means) 20 buffer controller (control means) 22 sub timer (timing generation means) 24 bus

Claims (2)

[Claims] 1. A history of a signal on a bus to which an input / output device performing communication with an external device is connected and a history of a signal transmitted / received between the input / output device and the external device. Storage means for storing, from a point in time when a call signal is transmitted from the input / output device to the external device, at least a time during which a response signal corresponding to the call signal can be received in a normal state, and a use area of the storage means Timing generation means for generating a stop signal indicating a timing at which the storage of the history is stopped when a predetermined time equal to or less than the time for storing the history has elapsed, and communication between the input / output device and the external device The history is sequentially stored in the storage means from the point in time when the storage is started, and when the history is stored in the entire use area of the storage means, the storage of the history is continued by overwriting. With Gosuru logging apparatus and a control means for controlling to stop the storing of the history to the storage unit based on the generated the stop signal by the timing generating means. 2. A history of a signal on a bus to which an input / output device for performing communication with an external device is connected, and a history of a signal transmitted / received between the input / output device and the external device. Storage means for storing; a timing generating means for generating a start signal indicating a timing to start storing the history each time a call signal is transmitted from the input / output device to the external device; Control means for controlling the storage of the history to be stopped when the history is stored in the entire use area of the storage means after the storage of the history in the storage means is started each time a start signal is generated; and A logging device with,.