JPH11184754A - Address translation processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the address translation of plural elements through one time of address translation by detecting a page attribute designated by the logical address of a list vector instruction and simultaneously performing the address translating processing of plural logical addresses. SOLUTION: A simultaneous processing element detecting means 30 inputs page address X bits of the logical addresses of list address holding means 10-13 for holding the plural logical addresses of the list vector instruction and the page attribute detected by a page attribute detecting means 20 and outputs the high-order M bits of representative page address X bits of simultaneous address processible element information and simultaneous processible elements to an address translation buffer index address generating means 40. The address translation buffer index address generating means 40 indexes an address translation buffer 45. An effective address generating means 50 inputs that output, intra-page address Y bits and the high-order M bit information of representative page address of simultaneous processible elements, outputs an effective bit and accesses a main storage device 60.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a list vector instruction control, and more particularly to an address conversion processing device for simultaneously performing address conversion processing of a plurality of elements.

[0002]

2. Description of the Related Art Conventionally, in an apparatus that supports a plurality of page frames (a frame in which a plurality of pages having the same page attribute are combined into one by a certain rule), data stored in a vector register in a vector processing unit is stored. The address conversion process in the list vector instruction accessing the main memory as an address is determined to operate on the smallest page frame among a plurality of supported page frames, and its page attribute is determined and the number of simultaneous address conversion processes is performed. And a simultaneous address conversion process is performed to access the main storage device (see Japanese Patent Application Laid-Open No. 61-180349).

[0003]

However, the above-mentioned prior art uses an address translation process for a list vector instruction.
Since the page attributes are determined to always operate with the smallest page frame among multiple supported page frames, and the number of simultaneous conversion processes is determined, the minimum for list vector instructions that can operate on large page frames Since the number of simultaneous conversion processes is determined as the page attribute of, there is a disadvantage that the processing performance is poor and the address conversion process cannot be performed at high speed.

[0004] The reason is that when determining the number of simultaneous translation processes in the address translation process in the list vector instruction,
Since it is unknown which of the page frames having the logical address of the instruction has a plurality of pages,
This is because the page attribute is determined to always operate in the minimum page frame.

The present invention has been made in view of the above-mentioned problems of the prior art,
When determining the number of simultaneous conversions that can be performed in the address conversion process in the list vector instruction, it is determined in which page frame the list vector instruction operates, and the page attribute is determined in advance, so that one address conversion process can be performed. Provided is an address conversion processing device capable of processing a larger number of elements than the number of simultaneous conversions determined to operate in the conventional minimum page frame, and performing high-speed address conversion processing of a list vector instruction. It is intended to be.

[0006]

In order to solve the above problems, an address translation processing device of the present invention translates a plurality of elements simultaneously by a single address translation process for a plurality of logical addresses in a list vector instruction. And a list address holding means for receiving a plurality of logical addresses, a page attribute detecting means for detecting a page attribute from an element (logical address) held in the list address holding means, and A simultaneous processing element detecting means for detecting an element which can be simultaneously converted by one address conversion, an address conversion buffer having a configuration capable of simultaneously obtaining continuous N-number of page conversion data, and an index for the address conversion buffer Address conversion buffer index address generation means for generating an address to be converted; And an effective address generating means for inputting an output of the buffer and an address in the page of the list address holding means and outputting an effective address.

According to the configuration of the present invention, when the logical address is divided into a page address of upper X bits and a page address of lower Y bits, and the page address of upper X bits is divided into upper M bits and lower N bits In an apparatus having an address conversion buffer configured to simultaneously obtain consecutive 2 N powers of page conversion data, the address conversion processing of the list vector instruction is performed after the page attribute is detected by the page attribute detection means, The detecting means detects which of the processing elements of the list vector instruction is capable of simultaneous address translation processing,
By one address conversion process, more elements can be subjected to the address conversion process than in the prior art.

[0008]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the address conversion processing of the present invention. In the figure,
The address conversion processing device according to the present embodiment includes list address holding means 10, 11, 12, and 13, page attribute detection means 20, simultaneous processing element detection means 30, address conversion buffer index address generation means 40, address conversion It comprises a buffer 45 and an effective address generating means 50.

List address holding means (register) 10
13 holds a plurality of logical addresses of the list vector instruction.

The page attribute detecting means 20 receives the representative page address X bits of the logical address held by the list address holding means, detects the page attribute on which the instruction operates, and sends the detection result to the simultaneous processing element detecting means 30. I do.

The simultaneous processing element detecting means 30 receives the page address X bits of the plurality of logical addresses held by the list address holding means 10 to 13 and the page attribute detected by the page attribute detecting means 20 as inputs, and The processable element information and the upper M bits of the representative page address X bits of the simultaneously processable element are output to the address conversion buffer index address generation means 40.

The address conversion buffer index address generation means 40 receives the representative page address M bits of the simultaneously processable element, generates an index address of the address conversion buffer 45, and indexes the address conversion buffer 45.

The effective address generation means 50 outputs the output of the address translation buffer 45 and the list address holding means 10
The Y address of the thirteenth page and the upper M-bit information of the representative page address of the simultaneously processable element of the simultaneous processing element detecting means 30 are input and an effective address is output to access the main storage device 60.

Next, a specific description will be given of a case where the first four elements (elements 0 to 3) of all the processing elements of the list vector instruction in this embodiment are processed. FIG. 2 is a diagram showing a configuration example of a logical address.

The usable page frame is operable in two types of page frames of 1 MB and 32 KB, and the logical address (list vector address) is, as shown in FIG. , The lower 2 bits are 7 bits, the address in the page is 20 bits,
At the time of the 32 KB page frame operation, the page address is set to the upper 10 bits, the lower 2 bits to 12 bits, and the address in the page to 15 bits. Further, the maximum number of simultaneous processing elements is set to four. In the present embodiment, the upper 12 logical addresses of the four elements
The bits have the following values.

Element 0 = 00001 00 01010 Element 1 = 000000 01 010101 Element 2 = 00001 10 01010 Element 3 = 000000 01 010101 In order to generate an effective address for accessing the main storage device from the logical address, the effective address is calculated from the logical address. As shown in FIG. 3 showing generation of addresses, address conversion processing is performed on page addresses of logical addresses to obtain conversion data (hereinafter referred to as page base addresses), and the obtained page base addresses and An effective address is generated by joining the logical address with the address in the page.

FIG. 4 is a diagram showing a configuration of an address conversion buffer for holding a page address.

The address conversion buffer 45 stores the value of the lower two bits of the logical page address as 00, 01, 10, 1
The address conversion data of 1 is pre-loaded,
Logical address upper 5 bits or 4 by 10 bits
By indexing one address translation buffer, a four-way interleave configuration is obtained in which four page base addresses can be obtained.

In FIG. 4, the address generated by the address conversion buffer index address generation means 40 is 0, the page base address indexed by the value of the lower 2 bits of the logical page address being 00 is PB (00), and the index address is 0. The page base address whose lower 2 bits of the logical page address is indexed by 01 is PB (01), and so on.
.. Is described as PB (31).

In this embodiment, it is assumed that a page base address that can be indexed by the upper 5 bits 00001 (1 MB page frame) of the logical page address is registered.

Since the maximum number of simultaneous processing elements is four, the list address holding means 10 to 13 receive a logical address for each of the four elements, and each time the processing of the four elements is completed, the list address holding means 10 to 13 starts with the lowest number of unprocessed elements Address registers 10, 11,
This circuit receives four element logical addresses in the order of 12, 13. That is, the list address holding units 10 to 13
Receives the elements 0, 1, 2, and 3, respectively, and when the processing of the four elements ends, further receives the elements 4, 5, 6, and 7.

The page attribute detecting means 20 holds the page base address information registered in the address conversion buffer 45, and detects the page attribute (size) at which the instruction operates based on the representative logical page address of the received instruction. It is. The page attribute detecting means 20 stores the upper 5 bits of the logical page address in the address conversion buffer 45 as 0.
0001 holds information in which the page address of the 1 MB page frame is registered. The upper 10 bits of the logical page address of the list address holding means 10 (000
0100010) is received, and from the information that the page base address of the 1 MB page frame is registered, the upper 5 bits (00001) of the received logical page address
And checks whether the registered information in the address translation buffer 45 matches the 5-bit 00001 of the registered address. When the check results match, a page attribute of 1 MB page frame is detected and reported to the simultaneous processing element detecting means 30.

The simultaneous processing element detection means 30 is a circuit which receives a plurality of logical addresses for performing address conversion processing and page attributes, and controls elements which can be converted at the same time so as to be processed by one address conversion. The simultaneous processing element detection means 30 sends the list address holding means 10 to 13
The upper 5 bits of the logical address are received, and information of 1 MB page is received from the page attribute detecting means 20. From the information of the 1 MB page, it is found that the logical page address is 7 bits, and a match detection of the upper 5 bits of 4 elements is performed. When it is detected that all four elements match, the element number (0, 1, 2, 3) to be processed in one address conversion process and the lower two bits of the logical page address of each element are sent to the effective address generation means 50. Report.

In the prior art, since a match is detected in a uniform 32 KB page, the received four 12-bit elements perform a match detection of the upper 10 bits, and a 4-element address conversion is performed based on the result that the elements 1 and 3 match. The processing is performed three times: elements 1 and 3, element 2 and element 4.

The address conversion buffer index address generation means 40 is a circuit for receiving the upper 5 bits of the logical page base address to be converted from the simultaneous processing element detection means 30, and generating an index address.

The address conversion buffer 45 has a configuration as shown in FIG. 4, and uses the index address of the output of the address conversion buffer index address generation means 40 to calculate a square of 2 (four) page conversion data (pages). This is a circuit that simultaneously reads the base address) and outputs it to the effective address generating means 50.

The address conversion buffer index address generation means 40 receives the five bits of 00001 from the simultaneous processing element detection means 30, and generates an index address. In this embodiment, an index address 0001 is generated, the address translation buffer 45 is indexed, and four page base addresses P
B (04) to PB (07) are converted to effective address generating means 50
Output to

The effective address generating means 50 calculates the effective address based on the four indexed page base addresses, the conversion element number from the simultaneous processing element detecting means 30, and the lower two bits of the logical page address. Is generated and output to the main storage device 60.

The four page base addresses PB (04) -PB indexed by the effective address generation means 50
(07) is selected by the value of the lower two bits of the logical page address of each element.

Since the lower 2 bits of the logical page address of the effective address of element 0 are 00, the page base address PB (04) is selected. The selected page base address PB (04) and the address in the page of the list address resist 10 are joined to generate an effective address of element 0,
The data is sent to the main storage device 60.

Similarly, the effective addresses of elements 1, 2, 3 are as follows:
The lower two bits of the logical page address are 01 and 1, respectively.
0, 01, the page base address PB (0
5), PB (06) and PB (05) are selected. The selected page base addresses PB (05), PB (06),
PB (05) and list address holding means (register) 1
The addresses in the pages 1, 12, and 13 are joined, and the elements 1, 1,
A few effective addresses are generated and sent to the main storage device 60.

[0033]

According to the present invention, since address conversion of a plurality of elements can be performed by one address conversion by controlling the address conversion buffer with a small amount of hardware, the address conversion processing time at the time of a list vector instruction is shortened. The effect of being performed can be produced.

The reason is that when the simultaneous conversion processing element is detected, since the page attribute is known, the bit width for detecting the logical page address match of each element can be detected by the bit width specified by the page attribute. Because.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an address conversion process according to the present invention.

FIG. 2 is a diagram showing a configuration example of a logical address;

FIG. 3 is a diagram showing generation of an effective address from a logical address;

FIG. 4 is a diagram showing a configuration of an address translation buffer;

[Explanation of symbols]

 10-13 List address holding means 20 Page attribute detection means 30 Simultaneous processing element detection means 40 Address conversion buffer index address generation means 45 Address conversion buffer 50 Effective address generation means 60 Main storage device

Claims (6)

[Claims] 1. An address translation processing device which supports a plurality of pages of different sizes and is capable of simultaneously translating a plurality of logical addresses for memory access to an effective address on a real address. Means for detecting the page attribute to which the address is assigned from the logical address of the list vector instruction that operates with the page attribute (page size type), and the page address of the logical address that can be simultaneously converted according to the detected page attribute And a means for converting the page address specified by the logical address of the list vector instruction to the effective address by means of a page address and a logical address within the page, and simultaneously converting a plurality of logical addresses. An address translation processing device for processing. 2. A list address holding means for receiving a plurality of logical addresses of a list vector instruction, and a page attribute detecting means for detecting a page attribute on which the instruction operates from an element (logical address) held in the list address holding means. A simultaneous processing element detecting means for detecting an element which can be simultaneously converted by one address conversion; an address conversion buffer configured to simultaneously obtain two N-th powers of page conversion data; Address translation buffer index address generation means for generating an address for indexing the buffer; and effective address generation means for receiving an output of the address translation buffer and an in-page address of the list address holding means and outputting an effective address. , Once for multiple logical addresses in a list vector instruction An address conversion processing device for simultaneously converting a plurality of elements by the address conversion processing and accessing a main storage device. 3. The page attribute detection means receives the upper M bits of the page address of the logical address held by the list address holding means, detects the page attribute on which the instruction operates, and outputs the page attribute to the simultaneous processing element detection means. The address translation processing device according to claim 1 or 2, wherein 4. The simultaneous processing element detecting means includes a page address X of a logical address held by the list address holding means.
It is assumed that the bit and the page attribute detected by the page attribute detecting means are input and the element information which can be processed simultaneously and the upper M bits of the representative page address X bits of the simultaneously processable element are output to the address conversion buffer index address generating means. The address translation processing device according to claim 1, wherein: 5. The effective address generation means inputs the output of the address conversion buffer, the Y bits in the page address of the list address holding means, and the upper M bits information of the representative page address of the simultaneously processable element of the simultaneous processing element detection means. 5. The address conversion processing device according to claim 1, wherein an effective address is output to access the main storage device. 6. The address conversion process according to claim 1, wherein the address conversion buffer is loaded with address conversion data of lower N bits of the logical page address in advance. apparatus.