JPH11184748A - Information processor and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the ratio of a long word access to a whole memory access. SOLUTION: At the time of transferring data between arbitrary two points in an address space, a data latch 107 latches transfer data, and a subtracter 105 calculates shit amounts from the lower 2 bits of the read and write address of the transfer data segmented into byte units. A barrier shifter 106 shifts the transfer data by the byte units based on the shift amounts, and a data latch 109 latches the shifted transfer data. A state controlling part 102 controls the width of the data-transferred data to the data bus width or byte width based on the shift amounts and the write address of the transfer data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and a control method therefor, and more particularly to an information processing apparatus for transferring data between any two points in an address space and a control method therefor.

[0002]

2. Description of the Related Art In general, an information processing apparatus including an MPU, a ROM, a RAM, and a peripheral device has a common bus for transferring data stored in the ROM, the RAM, and the like. These memories, registers in the ASIC, and peripheral device ports are addressed (addressed) from the viewpoint of the MPU. However, in local data processing of the peripheral device, a bus may be separately configured.

[0005] The information processing apparatus is configured so that data exchange with each peripheral device is established based on the operation of the MPU. In such a configuration, as a method of exchanging data between devices at high speed, there is a DMA in which devices exchange data directly without using an MPU. At this time, the MPU relinquishes the right to use the bus and does not exchange data with the outside.

In recent years, in information processing apparatuses, the system clock and the bus width have been continuously increased in order to process an enormous amount of data quickly. However, not all operations are performed with the fastest specifications. For example, DMA requires 32-bit or 64-bit data transfer, but data itself is often handled in byte units or word units. To give a concrete example, in a 32-bit bus,
In some cases, the bit width is used by dividing it into four (one byte each), and in this case, address control is performed to divide the 32-bit width into four by the lower two bits of the address. The storage order of the data is within a 32-bit width that combines 4 bytes into one.
It can be big-endian or little-endian in bytes.

[0005]

The process of moving data in a certain storage area to another storage area is frequently used and frequently used in places important for improving the throughput. As mentioned above, the specifications of information processing equipment have been improving year by year due to the improvement of semiconductor technology. However, in order to improve the throughput of the whole system, in data access without MPU (hereinafter referred to as DMA), I want to use the full width of the data bus. In the following description, the bus width of the data bus will be described as a 32-bit long word (Long Word: LW), but the present invention is not limited to this.

[0006] Data transfer tends to rely on DMA, regardless of whether the data is processed or not, in order to improve the throughput of the entire apparatus. Therefore, the circuit configuration linked to the bus arbiter becomes complicated. 2. Description of the Related Art In recent circuit design, a method of implementing a circuit expressed by a logic description language such as VHDL or Verilog HDL in a device using logic synthesis is used. The merits of this design method include that the design period can be shortened and the degree of freedom in selecting devices can be improved. on the other hand,
In this design method, the circuit delay, the circuit area, and the like must be considered in the language description. As described above, byte access and LW access are described in a unified manner.For example, if a state machine is described as it is, the content of conditional branches in the operation state increases,
This causes a problem that it is not suitable for later logic synthesis.

In order to solve such a problem and improve the throughput of the entire apparatus, it is desired to clearly separate byte access and LW access, and particularly to improve the ratio of LW access to the entire memory access.

An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide an information processing apparatus capable of controlling the width of data to be transferred and a method thereof.

[0009]

The present invention has the following configuration as one means for achieving the above object.

[0010] An information processing apparatus according to the present invention stores holding means for setting data transfer control information, control means for controlling data transfer based on the held control information, and stores read and write addresses of transfer data. An information processing device for performing data transfer between any two points in an address space, the storage device comprising: a storage unit for performing data transfer; and an address calculation unit for calculating a next address for continuously transferring data. The smallest unit associated with the width of
Shift means for shifting data to be transferred, latch means for latching data input / output to / from the shift means, and shift means for determining read and write addresses of transfer data divided into the minimum units from predetermined lower bits. Calculating means for calculating the shift amount of the data, wherein the control means controls data transfer via the latch means and the shift means, and writes the shift amount calculated by the calculating means and the transfer data. The width of data to be transferred is controlled based on the address.

According to the control method of the present invention, a holding unit in which control information for data transfer is set, a control unit for controlling data transfer based on the held control information, and a read and write address of transfer data are stored. Storage means;
Address operation means for calculating a next address for continuously transferring data, a method for controlling an information processing apparatus for performing data transfer between any two points in an address space, wherein the transfer data is latched, The shift amount is calculated from predetermined lower bits of read and write addresses of transfer data divided into minimum units related to the width of the data transfer bus, and the latched transfer is performed in the minimum unit based on the calculated shift amount. The data is shifted, the shifted transfer data is latched, and the width of the data to be transferred is controlled based on the calculated shift amount and the write address of the transfer data.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an example of data transfer in a storage area for the purpose of converting an array of data, there is the development of print data from a reception buffer of a printer to a print buffer. FIG. 1 is a block diagram showing a configuration example of a printer controller showing such an example.

The printer controller shown in FIG. 1 prints print information received from an external device, mainly a host computer, through an interface 505 to a print head mechanism 51 for printing. Interface
A signal received via the 505 is input to the controller 510 via a bus driver 503 for adjusting a signal level and performing waveform shaping. Controller 510 is RAM502
Is used as a buffer, the input data is temporarily stored in the RAM 502, print information is generated from the data stored in the RAM 502, and the generated print information is temporarily stored in the RAM 502. Therefore, inside the controller 510, an IF control unit 5101 related to interface status control, a bus arbiter 5102 related to print control, data development, MPU, RAM and ROM,
A head control unit 5104 that controls the print head mechanism 51 and a buffer development control unit 5103 that generates data for driving the print head are provided.

The printer system is controlled by a ROM 501.
Is performed by the MPU 500 based on the control program stored in the MPU and the program unique to the system.

In a peripheral device such as a printer, received processing data is temporarily stored in a reception buffer. At that time, in order to release the host computer from the printing processing in a short time, the processing data is continuously received up to the allowable range of the receiving buffer. In the case of print processing, received process data includes data of various attributes such as commands, image data, and character codes. These data are analyzed, and the print data is expanded in a print buffer according to the analysis result. .

The process of generating print data from the processing data of the reception buffer and developing the print data in the print buffer is more efficient if performed by DMA without the intervention of the MPU 500. In particular, for data such as bitmap data in which image data is continuous, it is possible to improve the throughput of the entire apparatus by continuously developing print data in a print buffer.

FIG. 2 is a diagram showing an example of transferring data obtained by dividing LW into byte units. In the figure, case_1 is a case where LW transfer is possible. As shown in the figure, if the data bus width is 32 bits, the current address of both the source side address and the destination side address is a base value of 32 bits,
That is, the lower two bits are '00' at little endian
If this is the case, you can read / write the entire bus width as it is.

However, when the transfer start position on the destination side is not the base value address as shown by case_2 in the figure, the address is transferred in byte units because the relative position (current byte) between the source and destination is different. Need to shift. In such a case, it is necessary to perform the DMA transfer in byte units, not in LW units, and it is required to perform the DMA transfer in byte units until the set number of transfers is completed. Of course, even when the data on the source side starts with a fractional byte, the address is shifted in byte units, and a DMA transfer in byte units is required.

If the rate of performing such byte-by-byte data transfer is high, even in a system having a wide angle and a wide bus width, the processing efficiency is reduced, and an improvement in throughput cannot be expected. In order to reduce the processing in units of bytes, there is a method of inserting a barrel shifter for each minimum processing unit (here, in units of bytes) between the data buffer on the source side and the data buffer on the destination side.

FIG. 3 is a diagram for explaining the barrel shift in byte units. Reference numeral 401 denotes a barrel shifter in byte units (hereinafter, simply referred to as "barrel shifter"). Barrel shifter 401
Is an input port for inputting a required shift amount, an input port for inputting 32-bit data to be shifted, and
An input port is provided for inputting carry data that is complemented during the shift (held during the shift). Then, the barrel shifter 401 arranges the carry data at the base position of the address, and then outputs from the output port 32-bit barrel-out data in which valid data (3 bytes) obtained by shifting the input 32-bit data is arranged. In this barrel out, the output pending data (1 byte) is separated and output from the carry out data output port for the next barrel out.

In FIG. 3, the current data is such that the data string on the source side is [data_e, data_f, data_g, data_h], and when this is shifted by 1 byte, the data string on the destination side is [data_d, data_e, data_f, data_g]. ] Is obtained. The carry-out data at this time is [data_h]. The carry-out output of barrel shifter 401 is 3
It becomes ['00', '00', data_h] of byte width. If the shift amount is 2, the carry-out output is ['00', data
_g, data_h], [data_f, data_g, d when the shift amount is 3
ata_h].

FIG. 4 is a diagram showing an example of a data array in the buffer. Source buffer data string [data_e, data_
f, data_g, data_h] are barrel-shifted to [data_d, d
ata_e, data_f, data_g] in the destination buffer.

If the shift amount between the source buffer and the destination buffer in LW units, (the lower 2 bits of the destination address) − (the lower 2 bits of the source address) is greater than zero, the read LW unit By barrel-shifting the data according to the shift amount, it is possible to obtain desired data in LW units. However,
Bytes that are fractions of LW at the write start position on the destination side, [data_a, data_b, data_
Regarding c], it is required to read and shift the data on the source side in byte units, and write the data on the destination side in byte units.

As described above, transfer between arbitrary memory areas in an information processing apparatus having a large data bus width, in particular,
In the control for increasing the bus utilization efficiency such as DMA, when the data transfer unit is smaller than the data bus width, and when the data array on the source side and the data array on the destination side are , The data transfer with the data bus width is impossible.

In the above description, the unit of data handled by the information processing apparatus is 8 bits (1 byte) and the bus width is 32 bits. In this example, using a barrel shifter, if the shift amount between the source side and the destination side is (lower 2 bits of the address on the destination side) − (lower 2 bits of the address on the source side), the shift amount is greater than 0. Holds, the transfer access with the data bus width becomes possible. This condition restricts the relative positional relationship between the source side and the destination side with respect to the start position of one band. In other words, the barrel shifter is not practical in a system in which the data storage position cannot be restricted.

[0026]

First Embodiment Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

[Structure] In this embodiment, by controlling the data transfer with the structure as shown in FIG. 5, the above-mentioned restriction is solved, and the data stored at an arbitrary position can be changed.
Transfer using the full width of the data bus.

The configuration shown in FIG. 5 includes a control information register 101,
State control unit 102, address storage unit 103, address calculation unit 10
4. There are a subtractor 105, a barrel shifter 106, a data latch 107, a data latch 108, and a data latch 109. That is, the two-stage latch using the data latch 107 and the data latch 109 for performing data transfer (or data expansion) between two points in the memory area, and the barrel shifter 106 including the carry data latch are controlled by the state control unit. 1
02 performs the effective bus width control, and maximizes the state in which the effective bus width is equal to the actual bus width. This control is realized by returning the output of the subtractor 105 to the state control unit 102.

Here, the function of each configuration in FIG. 5 will be briefly described. The control information register 101 holds a set value of a source address and a destination address set in a microprocessor (MPU) not shown,
For example, it is used to hold the amount of data to be expanded when executing DMA and the set value of the expansion prohibited section of the data area. Further, when a function for a special use is realized, the control information register 101 holds information on the mode changeover switch. In addition, the function of the special use is, for example,
In addition to normal data transfer between two points, there is a mode in which compressed data on the source side is written to the destination side while being expanded.

The state control unit 10 controls the circuit state by referring to the information set in the control register 101 by the MPU.
2 The state control unit 102 has a function of generating a control state timing. In the present embodiment, the status (MPU_STATUS), which is control information written into the control information register 101 by the MPU, is used as a start trigger, and a start trigger (START_TRIGGER) indicating the timing is transmitted to the state control unit 102. Upon receiving this start trigger, the state control unit 102 sends a status (MEMORY_STSTUS) to a memory unit (not shown), or sends a request (D
ATA_REQUEST). When receiving a data (request) acknowledgment (DATA_ACKNOWLEDGE) from a source buffer (not shown), the state control unit 102 receives data from the source buffer.

Data (SOURCE_DTAT_IN) is a data latch
Via (latched) 107, the data is input as the data to be shifted (BARREL_IN) to the barrel shifter 106 which transfers the data in the byte unit which is the minimum unit of the data. The barrel shifter 106 carries carry information (CARR) according to the shift amount (SHIFT).
Although the complement of Y) is required, the carry data is held by the data latch 108. In the barrel shifter 106 having a 32-bit width, the shift amount is 3, that is, the shift of 3 bytes is the maximum, and the maximum data size of CARRY_OUT is 24 bits. In accordance with this, the data size of the data latch 108 is also set to 24 bits.

The shift amount is calculated from the initial address set value. The source address and the initial value of the destination address are input to the subtractor 105. However, the shift amount is the lower 2 bits of the destination address.
Since only the lower 2 bits of the source address are subtracted from the bits, only the initial values of the lower 2 bits need to be input. For the same reason, when data writing to the destination side is started, if the positional relationship between the source side and the destination side that requires carry data is used, the shift amount becomes a negative number, and the hardware uses a subtractor. The output of 105 must consist of 3 bits.
The calculated shift amount is output as a shift amount to the barrel shifter 106, and is fed back to the state control unit 102 as address control information.

Also, a data acknowledge (DATA_ACKNOWL)
Upon receiving EDGE: (hereinafter abbreviated as “Ack”), the state control unit 102 confirming that the source data (SOURCE_DATA_IN) has been latched by the data latch 107 holds the data to be transferred to the destination in the data latch 109, Performs memory access to the destination area.

The address storage unit 103 outputs the addresses on the source side and the destination side by switching at the time of access. However, there is no problem even if the configuration is such that the addresses on the source side and the destination side are output independently. The address calculation unit 104 includes an address storage unit 103
When outputting the current address (CURRENT_ADDRESS) input from the memory to the memory, the next address (NEXT_ADDRESS) is calculated (the address value is updated) and returned to the address storage unit 103. If LW access and byte access in the present embodiment are taken as an example, "1" is used for byte access.
And "4"('100') in the LW access.

[Operation] Next, the operation of the data transfer control unit shown in FIG. 5 will be described with reference to the flowchart shown in FIG. In the following description, as an example, assume that the width of the system bus is 32 bits and the minimum data width is 8 bits. As a system configuration, it is assumed that read access is performed with a fixed LW length to a buffer on the source side, and write access is performed with a LW width and a byte width on a buffer on the destination side.

FIG. 6 is a flowchart showing DMA in the case where the LW width is fixed and the source side is read-accessed.

The address storage unit 103 has a control register 101
, The initial values of the source and destination addresses are set by the MPU (step S601). By determining the lower 2 bits of each address,
The shift amount is calculated by the subtractor 105 (step S60)
2). First, since the source data is read only with a fixed LW width, an LW read request is transmitted to the memory (or another intervening block) regardless of the shift amount (step S603). Waiting for the reception of Ack indicating the determination of the data read (step S604), when the Ack is received, the LW data is stored in the data latch 107 (step SS605).

It should be noted that in the description of FIG.
The control signals output from the control unit are omitted except for the signals characteristic of the present invention which are output to the external block. In practice, a control signal is output to each block that requires control. That is, the timing at which each data latch latches data is controlled by the control signal output from the state control unit 102, and the source data is latched in steps S603 to S605.

The data of the LW width is read regardless of the shift amount on the destination side.
The determination is made based on two bits (step S606). That is,
If the lower 2 bits are '00', write access is possible at once with the LW width, and if it is a fraction of '01''10' or '11', first the corresponding byte is written in byte width. Write access is required.

In the burst transfer mode in which the amount of one transfer is large, a maximum of 3 bytes at the beginning and end (total of 6 bytes)
Write access is required for byte (byte) width, and all write access can be performed for LW width thereafter. For write access of LW width, set the source address to "+4"
('100') (step S607), and if the shift amount is not "0", barrel shift is performed by the barrel shifter 106 (step S608). Of course, if the shift amount is “0”, BARREL_in_data = BARREL_out_data in FIG. Step SS
As a result of the determination in 606, if it is byte processing, the source address is incremented by "1" (step S610), and byte data for transfer is set (step S611).

Data sent to the destination side is stored in the data latch 109. The data read in the LW width is held in the data latch 109 via the barrel shifter 106 even in the case of a byte-width write access. However, even if an output path for data to be sent from the data latch 107 to the destination side is provided or a new byte access latch is provided, the characteristics of the present invention are not affected at all. That is, the feature of the present invention lies in the address operation.

The output of the subtractor 105 is input to the barrel shifter 106 as a shift amount and is returned to the state control unit 102. In the state where the shift amount is greater than 0, there are cases where the update address output from the address calculation unit 104 cannot be stored in the address storage unit 103 as the next address. When reading source data, the lower 2 bits of the current address are set to '00' 01 '10' 11 '
, The current address of the read must indicate '00' (base value).

Therefore, in the present embodiment, first, at the time of read access of the LW width, the lower 2 bits of the current address at the start are stored in the address storage unit 103, and the subtracter 10
A signal (IGNORE) for invalidating the value of the lower 2 bits of the address read from the address storage unit 103 from 5 is output. Thereafter, the lower two bits output from the address operation unit 104 become “00”. At the end of the data transfer, the state control is performed such that the lower two bits of the address at the start of the read access of the LW width are output from the address storage unit 103 to the byte position at which the transfer (expansion) has actually been completed. The signal (UPDATE) is output from the unit 102.

When valid data is read from the source, the current address is output to the destination, a write request is transmitted to the destination buffer (step S609), and the reception of an Ack from the destination is waited. (Step S612). When the Ack is received, it is determined in step S613 whether or not byte processing is to be performed. This processing also indicates address update processing as in the case of the source side. Whether to perform byte processing or LW processing in actual destination buffer access is determined by LW if the lower 2 bits of the current address pointer on the destination side are '00' or the remaining transfer data amount is 4 bytes or more. Processing.

In the LW process, the destination address is incremented by "4" (step S614), and the amount of data transferred (developed) is counted as 4 bytes (or the remaining data amount is "-4") (step S614). Step S615). In the case of byte processing, the destination address is incremented by "+1" (step S616), and the data transfer (development) amount is counted as one byte (or the remaining data amount is "-1") (step S617). The data transfer (development) amount or the remaining data amount is used for determining the end of the data transfer in step S618. If the DMA transfer of the set amount of data has been performed, the DMA has been completed.
Return to step 3.

In the processing for performing read access of the LW width on the source side and write access of the destination side in the byte width in the present embodiment, if only the target byte data is written in the LW width read data, the remaining 3 bytes Data is discarded, and data with the same LW width is newly read.

[0047]

[Second Embodiment] In a second embodiment according to the present invention, a method for suppressing a change in the shift amount during the LW process in only the negative direction will be described. The configuration of the device is the same as that of the first embodiment, and the control flow will be described with reference to FIGS. 7 and 8.

The initial value of the address is set (step S70)
1) The shift amount is calculated (step S702), and then the current byte position on the destination side is detected.
If the current byte on the destination side is the base position (the lower 2 bits are '00'), the process branches to read access processing of the LW width of the source data; otherwise, it branches to read access processing of the byte width of the source data ( Steps
S703).

In the present embodiment, the current byte position on the destination side is moved to the base position, and the difference from the read address on the source side at that time is calculated.
(Lower 2 bits of destination address)
The shift amount represented by (lower 2 bits of source address) must be negative (or zero).

In the byte processing on the source side, a byte read request is output (step S704), and the process waits until an Ack is received (step S705). When the Ack is received and the source data is determined, the source data is latched by the data latch 107. And the source address is incremented by 1 (step S7).
06). Then, the source data is set as the destination data in the data latch 109 (step S70).
7), a byte write request is output to the destination side (step S708), and the destination side
Wait for Ack to be received (step S709). When the Ack is received, the current address of the destination is incremented by "1" (step S710), and the data transfer (development) amount is set to 1
Count as bytes (or
1 ") (step S711). DMA of set data amount
If the transfer (deployment) has been completed, the DMA has been completed, and if there is any remaining, the process returns to step S702 (step S725).

Returning to step S702, recalculation of the shift amount is performed. As described above, byte processing is performed until the lower two bits of the destination become "00". When the shift amount becomes negative (or zero), the process proceeds to the LW process (step S703).

In the LW processing, both the read access of the source data and the data write access to the destination are performed.
Perform with LW width. First, a read request for the source data is output (step S712), and an Ack is received (step S713). When the Ack is received, the source data is latched in the data latch 107, the address on the source side is incremented by "+4" (step S714), and the source data is barrel-shifted by the previously calculated shift amount (step S71).
Five). Thereafter, the data of the barrel-shifted LW width is latched by the data latch 109 as data to be sent to the destination, and the carry-out data is latched by the data latch 108 (step S716).

Next, in step S717, the lower two bits of the source address are examined to determine whether or not it is at the base position. As described above, the shift amount in the barrel shift is negative or zero. If the shift is in the negative direction, no carry data is prepared at the beginning of the LW process. Therefore, if the shift amount is negative in step S717, that is, if the source address is not at the base position, LW data is read-accessed by performing the processing of steps S712 to S716 in step S726, and the previous carry-out data is replaced with the current carry-out data. Turn to data. If the shift amount is zero, that is, if the source address is at the base position, step S726 is not executed because carry data is unnecessary.

Subsequently, the L latched by the data latch 109
Make the W-width data ready for output as destination data (step S718) and go to the destination
An LW width write request is transmitted (step S719), and Ac
Wait for k to be received (step S720). After confirming that the Ack has been received and that the data write has been completed normally, the destination side address is incremented by "+4" (step S7).
21), the data transfer (development) amount is set to “+4” (or the remaining data amount is set to “−4”) (step S722).

If the set amount of data is DMA-transferred (developed), the DMA is terminated (step S723). If not, the LW process is repeated until the remaining transfer data becomes less than 4 bytes in step S726. Return to (Step S7
twenty four). In the LW processing thereafter, the previous carry data is filled.

When the remaining transfer data is less than 4 bytes (step S724), byte processing is required again. At this time, since the source address is overrun by the amount packed in the carry in the LW process, it is necessary to control the return of the address corresponding to the overrun. This control is preferably executed in step S704. That is,

The current address before receiving and storing the operation result is stored.

At the end of the LW process, the address operation unit 10
Ignore the operation result of 4 and adopt the saved address. Then, by returning the lower 2 bits of the address to the initial setting value, it is possible to indicate the next access address.

As described above, in an information processing apparatus having a large data bus width, in a control for increasing the use efficiency of a bus such as a DMA for transferring data between arbitrary memory areas, for example, a data unit is a data unit. If the data width is small with respect to the bus width, or if the data array on the source side is shifted and sent to the destination side, data transfer with the data bus width is impossible. On the contrary,
According to each of the above-described embodiments, it is possible to perform data transfer at an arbitrary data storage position by making full use of the data bus width.

The feature of each embodiment is that, in data transfer between two points on a memory area, state control of a two-stage latch including a data latch 107 and a data latch 109 and a barrel shifter 106 including a carry data latch 108 are performed. What the part 102 does is to maximize the period during which the data width is equal to the data bus width while controlling the data width of the transfer data. This control is realized when the output of the subtractor 105 is fed back to the state control unit 102.

[0061]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

Further, an object of the present invention is to provide a storage medium storing program codes of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or a CPU or M
Needless to say, this can also be achieved by the PU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also the OS running on the computer based on the instructions of the program code.
It goes without saying that an (operating system) performs a part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into the memory provided in the function expansion card inserted into the computer or the function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that the CPU included in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0064]

As described above, according to the present invention,
An information processing apparatus and a method for controlling the width of data to be transferred can be provided.For example, in order to improve the throughput of the entire apparatus, byte access, LW
The access can be clearly separated, and in particular, the ratio of LW access to the entire memory access can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a printer controller.

FIG. 2 is a diagram illustrating an example of transferring data obtained by dividing a long word into bytes.

FIG. 3 is a diagram illustrating barrel shift in byte units;

FIG. 4 is a diagram showing an example of a data array in a buffer.

FIG. 5 is a diagram showing a configuration example of a data transfer control unit according to the present invention;

[Fig. 6] DM by read access with longword fixed width
Flowchart showing an example of A,

FIG. 7 is a flowchart showing an example of DMA with dummy read access;

FIG. 8 is a flowchart illustrating an example of DMA with dummy read access.

Claims (11)

[Claims] 1. A storage unit in which control information for data transfer is set, a control unit for controlling data transfer based on the held control information, a storage unit for storing read and write addresses of transfer data, Address processing means for calculating a next address for continuous transfer, and an information processing device for transferring data between any two points in the address space, wherein the minimum unit related to the width of the data transfer bus A shift unit for shifting data to be transferred, a latch unit for latching each of data input and output to and from the shift unit, and a read and write address of the transfer data divided into the minimum units. Computing means for computing the shift amount of the shifting means, wherein the control means comprises: the latch means and the shift means. Controls data transfer via the means, based on the calculated shift amount and the write address of the transfer data by the calculating means, the information processing apparatus characterized by controlling the width of data to be data transferred. 2. The information processing apparatus according to claim 1, wherein the data transfer is performed by the control unit in a maximum width of the data transfer bus or in the minimum unit. 3. The minimum unit is a minimum data unit effective for processing of the device, and sets a width of the data transfer bus.
3. The information processing apparatus according to claim 1, wherein when W is the minimum unit, the remainder of W / U is a positive integer value of zero. 4. The apparatus according to claim 1, wherein the shift amount of the shift means is variable, and the transfer data and the carry for the shift are input, and the shifted data and the carry are output. An information processing device according to any one of the above. 5. The control means reads the transfer data with a width equal to the width of the data transfer bus, and writes the transfer data by switching the data width to the width of the data transfer bus or the minimum unit. Claim 1 characterized by the following:
The information processing device according to any one of claims 1 to 4. 6. The method according to claim 5, wherein when the write access using the minimum unit data width is performed a plurality of times, the same address on the transfer data supply side is read-accessed by the number of write accesses. Information processing device. 7. The shift amount is a difference between predetermined lower-order bits in a read address and a write address of the transfer data, which can determine a position for storing the minimum unit of data within a width of the data transfer bus. When the calculated shift amount is not zero, the control means performs the transfer from the second read access after performing one read access of the transfer data by the width of the data transfer bus. 5. The information processing apparatus according to claim 1, wherein write access to data is started. 8. The control means decodes the contents of the read transfer data as a command, expands the transfer data to a transfer destination based on an instruction indicated by the command, and, if the command indicates a predetermined instruction, 5. The information processing apparatus according to claim 1, wherein the data on the specified supply side is repeatedly developed to the transfer destination. 9. The control means decodes the content of the read transfer data as a command, and expands the read information compressed data and expands the data to a transfer destination based on an instruction indicated by the command. Claims characterized by the following:
5. The information processing device according to claim 1, wherein: 10. A storage unit in which control information for data transfer is set, a control unit for controlling data transfer based on the stored control information, a storage unit for storing read and write addresses of transfer data, Address processing means for calculating a next address for continuous transfer, and a method for controlling an information processing device for performing data transfer between any two points in an address space, wherein the transfer data is latched, The shift amount is calculated from predetermined lower bits of read and write addresses of transfer data divided into minimum units related to the width of the bus for use, and the transfer data latched in the minimum unit is calculated based on the calculated shift amount. The transfer data is shifted, the shifted transfer data is latched, and the shift data is calculated based on the calculated shift amount and the write address of the transfer data. The control method characterized by controlling the width of data to be data transferred. 11. A storage unit for setting data transfer control information, a control unit for controlling data transfer based on the held control information, a storage unit for storing read and write addresses of transfer data, Address calculation means for calculating a next address for continuous transfer, wherein a program code for a control method of an information processing apparatus for performing data transfer between any two points in an address space is recorded. A code of a step of latching the transfer data, and a code of a step of calculating the shift amount from predetermined lower bits of the read and write addresses of the transfer data divided into the minimum units related to the width of the data transfer bus. Code of the step of shifting the latched transfer data in the minimum unit based on the shift amount And a code of a step of latching the shifted transfer data; and a code of a step of controlling the width of data to be transferred based on a calculated shift amount and a write address of the transfer data. Recording medium.