JPH11183661A - Mobile communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reconfigure a time base after a pause interval with a simple layout by reloading a value arriving from a low-accuracy clock source that continues to operate to a high-accuracy counter when power is turned on after the pause period. SOLUTION: A high-frequency and high-accuracy main oscillator 20 is frequency-divided by a divider 21 and is supplied to the main clock of a high- accuracy counter 22. During the initialization of a system, a CPU 12 reads a count value from the counter 22 at a proper point of a GSM period to prepare for the succeeding, first pause period. The number of pulses from the divider 21 is counted during approximately 0.5-1 second being synchronized by a sub clock from a low-frequency and low-cost sub oscillator 25, the sub clock is calibrated by a main clock, and the frequency ratio of the main oscillator 20 to the sub oscillator 25 is obtained. During operation, counters 27 and 28 alternately perform loading and measurement by the sub clock. Power is turned on after the pause period, is stabilized during two to three periods of the sub clock, and a change value that is calculated by the CPU 12 is loaded into a register 24 before that.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a mobile communication device, and more particularly to a mobile communication device having a highly accurate clock recovery function.

[0002]

2. Description of the Related Art A time division multiple access system (TDMA: Ti
GSM (Global System for Mobile communica) that allows one base station to communicate with many mobile devices at the same time using me Divisional Multiple Access (ME).
) and other digital communication systems, it is very important to accurately synchronize the mobile device with the base station transmission. To that end, each mobile device is equipped with a stable and accurate high-frequency clock oscillator, which is used to accurately measure time intervals.

However, since various components used in a high-frequency clock oscillator and a high-precision timing chain consume considerable power, a mobile communication device periodically switches the high-frequency clock oscillator and other components of the timing chain. It is common to periodically disconnect to save battery power. It has already been proposed to attach to the mobile device a second clock oscillator operating at a low frequency and used to measure the time interval when the high-precision timing chain is off (hereinafter referred to as the "pause" interval). Have been.

In the prior art, the following operation is performed.
Just prior to the beginning of the pause interval, the high-precision count value is read from the register by the edge of the output of the second oscillator. Next, the high frequency clock oscillator is turned off during the predetermined number of low frequency clock "ticks" to place the device in a low power mode, ie, a "pause" mode. After this period, the high-frequency clock oscillator is started again. When the high-frequency clock oscillator is started and stabilized, the high-precision count register is reloaded with a reconstructed value which is a value considered to have been reached when the high-frequency clock oscillator was assumed to have been operating continuously. This reconstructed value is calculated using the following equation.

New value = Old value + (TICK_SPEED_RATIO × POWER_DOWN_PERIO
D) where TICK_SPEED_RATIO is the frequency ratio of the two clock oscillators and POWER_DOWN_PERIOD is the period of the pause interval measured by the ticking frequency of the low frequency clock oscillator.

[0006]

The prior art described above raises many problems. First, the edges of the high frequency clock pulse and the low frequency clock pulse are not synchronized.
Further, the clock frequency ratio cannot be accurately represented in a binary system. In addition, jitter at the edges of the low frequency clock oscillator and variations in clock speed must be considered. Together, these factors can cause errors in the reloading of the high-precision count register, and after a long period of time the errors accumulate, causing loss of accuracy and no longer maintaining proper operation of the mobile device. Disappears.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and provides a mobile communication device with a simple arrangement for time-based reconstruction after a pause interval. With the goal.

[0008]

SUMMARY OF THE INVENTION In its broadest aspect, the present invention provides a mobile communication having a high precision counter which reloads a value coming from a continuously running low precision clock source upon power-up after an idle period. Including equipment.

According to the present invention, a high-frequency high-precision main clock oscillator, a high-precision counter for counting clock pulses from the main oscillator for controlling the timing of a communication operation, and a power holding device are provided. A low-frequency sub-clock oscillator for timing a pause interval when the main oscillator is turned off, and means for periodically switching the main oscillator on and off during a time interval determined by the sub-clock. Loading the high-accuracy counter at the start of the on-period of each cycle with a restart value in a previous cycle by the cycle of the sub-clock and a restart value determined according to a total time elapsed since the previous restart. And a means for performing the above. With this arrangement, there is no error in repeatedly calculating and accumulating restart values at the start of a continuous cycle, and the high-precision counter can be maintained in accurate synchronization with the signal received from the current base station. .

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a mobile communication device according to the present invention. FIG. 2 is a block diagram showing a configuration of a clock device for performing a highly accurate clock recovery operation in the embodiment. It is.

The embodiment shown in FIG. 1 includes an RF stage 10, a digital signal processor (DSP) 11, and a central processing unit (CPU) 12. DSP 11 receives input from RF stage 10 in the form of analog samples, processes and stores it for use by CPU 12. The DSP 11 controls an audio stage 13, which receives an input to a microphone 14 and outputs an audio signal obtained from an RF signal to a speaker (earphone) 15. The CPU 12 determines the associated R
AM16 and ROM17, and the CPU 1
There is also a known subscriber identification module 18 connected to 2.

FIG. 2 is a block diagram showing a configuration of a circuit for supplying a clock in this embodiment. As shown in FIG. 2, this device has two system clock pulse generators. One of the main oscillators 20 is a high-frequency and high-precision oscillator operating at a frequency of 13 MHz. The output of the main oscillator 20 is divided by a frequency divider 21 by a value of 6 to obtain a frequency of 2.1666.
Clock, and the divided clock is GS
It is eight times the bit rate used in the M system, and is used for the clock of the high-precision counter 22 (hereinafter, referred to as a count value HI_RES_TIMER held in the counter 22).

The counter 22 can be formed of a 32-bit counter that counts down a value that is reset each time the count value returns to zero.

The reset value is determined by the value HI_RES_MODULO set in the register 23 by the CPU 12. This set value HI_RES_MODULO is, for example, 2
The value of the bit period required for the GSM multiplex frame of 6 frames, that is, 8 times 260000 can be used. Further, as described below, preparations are made for setting the value HI_RES_RELOAD set in the register 24 by the CPU 12 in the counter 22.

The system of the present embodiment also includes a low frequency, low cost secondary oscillator 25 used to control the length of the idle period of the main oscillator, and associated components for power savings.

When the device is in the standby mode,
The device needs to periodically receive a signal from the currently logged base station and check for signal paging. The signal occurs at precisely defined time intervals in the GSM cycle, during which time the RF stage 10, master oscillator 20, CPU 12, and other options of the device need not be active. . The function of the sub-oscillator 25 is such that by taking the timing of the on-period and the off-period, the counter 22 can be loaded with a value considered to be held by the counter 22 when the counting is not stopped during the pause period. To provide a means to The power supply to the main oscillator 20 and other parts of the device is stopped by turning off the main power supply device 26.

Sub oscillator 2 operating at a frequency of about 32 KHz
5 drives the clocks of the two counters 27 and 28. The counter 27 is a power stop counter. The counting operation of the counter 27 starts with a value determined by the value POWER_DOWN_PERIOD set in the register 29 at the start of the pause interval, and counts until it becomes zero, which is a value for switching on the main power supply 26.
The counter 28 is a power-on counter. Counter 28
Starts at the value POWER_UP_PERIOD set by the CPU 12 in the register 30 when the count of the counter 27 reaches zero. By changing the count value held in the counter 28 by the CPU 12, the period can be shortened or extended during the power-on period. It does so by loading a positive or negative POWER_UP_CHANGE value in register 31. When the count value decreases (ie, 32 KHz
On the next active edge of the clock signal), POWER_UP_C
By adding the HANGE value to the count value of the counter 28,
Increase or decrease the time to completion while maintaining synchronization.

In use, during system initialization, G
At an appropriate point in the SM cycle, the CPU 12 reads the count value from the counter 22 and prepares for a first pause period thereafter. The timing is set by the sub clock 25.
By counting the number of pulses obtained by the frequency divider 21 for 5 to 1 second, the sub clock 25
Calibrated to zero. According to the obtained value, TICK_SPE
ED_RATIO value can be calculated. Performing this calibration operation periodically during use cancels the frequency shift.

In operation, counters 27 and 28 alternately load and measure with a sub-clock. At the end of the sleep period, the power supply is turned on, stabilizing the high-frequency system by further passing two or three cycles of the subclock, but loading the HI_RES_RELOAD value previously calculated by the CPU 12 into the register 24. .

Time since last reload ELAPSED_TIME
Is calculated from the values loaded into the registers 29, 30 in the previous cycle to take into account the additional sub-clock ticks assigned during the power-on phase for changes and stabilization during the cycle.

The value HI_RES_RELOAD (i) (ie, the value for the i-th cycle) is calculated as follows.

(HI_RES_RELOAD (i-1) + TICK_SPEED_RATIO
× POWER_DOWN_PERIOD (i-1)) mod HI_RES_MODULO The CPU 12 performs further calculations and maintains a count of the number of multiplexed frames that have passed.

Any calculations performed are HI at initialization.
It should be noted that, except for the purpose of obtaining a certain initial value of _RES_RELOAD (0) and for the case of periodic calibration of the secondary clock, it does not rely on the counting of high-precision clock pulses during operation. Calibration is performed over a long time interval to obtain the ratio with the required level of accuracy. If there is a slight error in the reload value at each reload, the error is random and not cumulative.

[0025]

Since the present invention is configured as described above, there is an effect that time-based reconstruction after a pause interval can be performed with a simple arrangement.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a mobile communication device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a clock device that performs a highly accurate clock recovery operation in the embodiment shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 RF stage 11 Digital signal processor 12 CPU 13 Audio stage 14 Microphone 15 Speaker 16 RAM 17 ROM 18 Subscriber identification module 20 Main oscillator 21 Divider 22, 27, 28 Counter 23, 24, 30, 31 Register 25 Secondary oscillator 26 Main power supply

Claims (6)

[Claims] 1. A mobile communication device having a high-precision counter for reloading a value coming from a continuously operating low-precision clock source when the power is turned on after a pause. 2. A high-frequency high-precision main clock oscillator; a high-precision counter for counting clock pulses from the main oscillator for controlling a timing of a communication operation; and the main oscillator for power retention. A low-frequency sub-clock oscillator for taking a pause interval timing when turning off, a means for periodically switching the main oscillator on and off during a time interval determined by the sub-clock, Means for loading, at the start of the on-period, the high-accuracy counter with a restart value in a previous cycle according to the cycle of the sub-clock and a restart value determined according to a total time elapsed since the previous restart. A mobile communication device having: 3. The mobile communication device according to claim 2, wherein the high-precision counter is periodically reset to a modulo value considered in calculating the restart value. 4. The mobile communication device according to claim 2, wherein said means for periodically turning on / off the main oscillator is provided with a count value representing a period required for an on-period and an off-period. A first counter and a second counter, which are sequentially loaded, wherein the first counter turns off the main oscillator at the end of counting, starts a second counter, and the second counter starts at the end of counting. A mobile communication device that turns on a main oscillator and starts a first counter. 5. The mobile communication device according to claim 4, wherein a value of an on-period and a value of an off-period are loaded by the central processing unit, and the first and second counters respectively load the first and second counters. A mobile communication device to which a second register is attached. 6. The mobile communication device according to claim 5, further comprising a register which is loaded with a change value by the central processing unit when the length of the on-time is requested to be changed during the on-time. A mobile communication device in which when the power is turned on after a pause period, the changed value is added to a current count value of a high-precision counter that is reloaded with a value from a continuously operating low-precision clock source.