JPH11183530A - Circuit and method for detecting high voltage level - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit which converts a high-voltage signal of approximately -200 to -50 V into a low-voltage logic signal of 3 to 5 V or 0 V. SOLUTION: The circuit is equipped with a 1st power source VDD, a 2nd power source VSS, and a 3rd power source GND and consists of a differential circuit DEF consisting of a 1st transistor TR1 and a 2nd transistor TR2 operating with the 1st power source VDD and 2nd power source VSS, a current mirror circuit CM as the load on the differential circuit DEF, a reference voltage Vref applied to one input of the differential circuit DEF and a high-voltage input signal Vin applied to the other input of the differential circuit DEF, an inverter circuit INV which operates with the 1st power source VDD and 3rd power source GND, and a level shift circuit SH provided between the current mirror circuit CM and inverter circuit INV.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage level detection circuit suitable for converting a high voltage signal to a low voltage logic signal and a method thereof.

[0002]

2. Description of the Related Art A circuit for converting a high-voltage signal of about -200 to -50 V into a low-voltage logic signal of 3 to 5 V or 0 V has not been provided.

[0003]

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to convert a high voltage signal of about -200 to -50 V into a low voltage logic signal of 3 to 5 V or 0 V. Such a circuit and its method are provided.

[0004]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of the high-voltage level detection circuit according to the present invention includes a first power supply, a second power supply, and a third power supply, and includes the first power supply and the second power supply. A differential circuit including a first transistor and a second transistor serving as a power supply; a current mirror circuit serving as a load of the differential circuit; a reference voltage applied to one input of the differential circuit; A high-voltage input signal applied to the other input of the driving circuit, an inverter circuit using the first power supply and the third power supply as power supplies, and a level provided between the current mirror circuit and the inverter circuit. In a second aspect, the level shift circuit includes a resistor provided at an input of the first power supply and the input of the inverter circuit, and an anode configured to include the anode. Connect to the input of the inverter circuit A first diode, a second diode having an anode connected to the third power supply and a cathode connected to the cathode of the first diode, a cathode of the first diode, and the second power supply. And a third transistor provided between the third transistor and a third transistor. In a third aspect, a Zener diode is provided between a gate and a drain of the third transistor. In a fourth aspect, a fifth transistor is provided between a first transistor to which a high voltage of the differential circuit is input and a fourth transistor which is a load of the transistor. A transistor is provided, and the gate of the fifth transistor is fixed to a predetermined voltage. In a fifth aspect, the voltage of the first power supply is a positive voltage, The voltage of the second power supply is a negative voltage, and the voltage of the third power supply is a ground potential. In a sixth aspect, at least the differential circuit, the current mirror circuit, The inverter circuit and the level shift circuit are formed on one main surface of a semiconductor substrate.

A first aspect of the method for detecting a high voltage level according to the present invention is a method for converting a high voltage signal into a low voltage logic signal, comprising a first power supply and a second power supply. And a third power supply, wherein the high-voltage signal is input to a differential circuit provided between the first power supply and the second power supply,
The differential circuit compares the high voltage signal with a reference voltage,
The comparison result is sent to the first power supply and the third power supply via the level shift circuit.
And a low-voltage logic signal is obtained by leading to an inverter circuit provided between the first power supply and the second power supply.
5V, and the voltage of the second power supply is -200V to -50V.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A high-voltage level detection circuit according to the present invention includes a first power supply, a second power supply, and a third power supply, and the first power supply, the second power supply, and the like. The first power source
Circuit, a current mirror circuit which is a load of the differential circuit, a reference voltage applied to one input of the differential circuit, and a differential circuit of the other of the differential circuit. A high voltage input signal applied to the input, an inverter circuit using the first power supply and the third power supply as power supplies, and a level shift circuit provided between the current mirror circuit and the inverter circuit Therefore, a high-voltage signal of about -200 to -50 V can be converted into a low-voltage logic signal of 3 to 5 V or 0 V with a simple circuit and reliably.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing the structure of a specific example of a high-voltage level detection circuit according to the present invention. FIG. 1 shows a first power supply VDD, a second power supply VSS, and a third power supply GND. And a differential circuit DEF including a first transistor TR1 and a second transistor TR2, which are powered by the first power supply VDD and the second power supply VSS.
A current mirror circuit C which is a load of the differential circuit DEF
M, a reference voltage Vref applied to one input of the differential circuit DEF, a high-voltage input signal Vin applied to the other input of the differential circuit DEF, the first power supply VDD and the third A high voltage level detection circuit including an inverter circuit INV using a power supply GND as a power supply and a level shift circuit SH provided between the current mirror circuit CM and the inverter circuit INV is shown.
The level shift circuit SH is connected to the first power supply VD.
D, a resistance element R1 provided at the input of the inverter circuit INV, a first diode D1 having an anode connected to the input of the inverter circuit INV, an anode connected to the third power supply GND, and a cathode connected to the third power supply GND. A second diode D2 connected to the cathode of the first diode D1, and a third transistor TR10 provided between the cathode of the first diode D1 and the second power supply VSS. A voltage level detection circuit is shown, and a high voltage level detection circuit in which a Zener diode ZD1 is provided between the gate and the drain of the third transistor TR10 is shown.
A fifth transistor TR11 is provided between a first transistor TR1 to which the high voltage of the differential circuit DEF is input and a fourth transistor TR6 which is a load of this transistor.
And a detection circuit of a high voltage level in which the gate of the fifth transistor TR11 is fixed to a predetermined voltage is shown, and the voltage VDD of the first power supply is a positive voltage (+5
V), and the voltage of the second power supply VSS is a negative voltage (−
150 V), and the voltage of the third power supply GND is the ground potential (0 V).

Next, the present invention will be described in more detail. FIG.
FIG. 2 is a circuit diagram showing a first specific example of the present invention, and FIG.
Is a diagram for explaining the operation. First, the configuration of the present invention will be described. The sources of Pch field effect transistors (hereinafter, referred to as FETs) TR1 and TR2 forming a differential circuit DFF are connected to the drain of a Pch FET TR3 forming a constant current circuit. , FETTR3 has a source of the first
Is connected to a 5V power supply. And FET
The gate of TR3 is a diode-connected Pch TR4 of Pch.
It is kept at a constant voltage by a constant voltage circuit composed of TR5.

The reference voltage Vref is applied to the gate of the FET TR2 of the differential circuit DFF,
A high-voltage signal Vin is applied to one gate, and the differential circuit compares the high-voltage signal Vin with a reference voltage Vref. The drains of FETTR1 and FETTR2 of the differential circuit are connected to N-channel FETTR6 and FETTR7, respectively.
A current mirror circuit comprising
6. The drains of FETTR7 are FETTR1 and FE, respectively.
FETTR6, FETTR to the drain of TTR2
7 is connected to a second power supply, a -150V power supply VSS.

A Pch FET T is connected between the 5V power supply VSS and the ground (potential 0 V) which is the third power supply GND.
Inverter circuit I composed of R8 and N-channel FET TR9
NV is provided, the source of the FET TR8 is connected to the first power supply, the source of the FET TR9 is connected to the ground GND, the gate of the FET TR8 is connected to the gate of the FET TR9, and the drain of the FET TR8 is connected to the FE.
The drain of TTR9 is connected, and FETTR8 (F
The logic output is obtained at the drain of the ETTR 9).

A level shift circuit S provided between the current mirror circuit CM and the inverter circuit INV.
H is provided. The level shift circuit SH includes a resistance element R1 provided at the input of the 5V power supply VDD and the inverter circuit INV, and a first diode D1 having an anode connected to the input of the inverter circuit INV.
A second diode D2 having an anode connected to the ground GND and a cathode connected to the cathode of the first diode D1, and a drain connected to the cathode of the first diode D1 (second diode D2) FETTR whose source is connected to the second power supply VSS
10 and a Zener diode ZD1 (Zener voltage 15 V) provided between the gate and source of the FET TR10.

The FETTR1 constituting each of the above circuits
TR10, diodes D1, D2, resistance element R1, and zener diode ZD1 are integrally formed on a semiconductor substrate. In the high voltage level detection circuit of the present invention configured as described above, the voltage of the input signal Vin is equal to the reference voltage V.
If it is greater than ref, FETTR1 turns off and FETTR10 also turns off, thus turning on FETTR9 due to Zener diode ZD1;
An L level is output.

In this case, the gate potential of the FET TR10 is -150V via the FET TR6. On the other hand, when the voltage of the input signal Vin is smaller than the reference voltage Vref, the FET TR1 is turned ON, and therefore, the potential of the node B becomes -135 V, thereby the FET TR1
0 turns ON.

At this time, since the diodes D1 and D2 are turned on and the constant of each element is set so that the potential of the gate of the inverter circuit INV becomes 0 V by the action of the diodes D1 and D2, the FET TR8 is turned on. In this case, the H level is output. FIG. 2 shows this state. FIG. 3 is a circuit diagram showing a second specific example of the present invention.

In this circuit, an Nch FET TR11 is provided between the FET TR1 and the FET TR6 without using the Zener diode ZD1 of FIG. 1, and the source of the FET TR11 is connected to the drain of the FET TR6, and the drain of the FET TR11 is connected to the drain of the FET TR1. The gate is fixed at a predetermined voltage by a Zener diode ZD2.

For this reason, the anode of the Zener diode ZD2 is connected to the third power supply VSS, and the Zener diode ZD2
Is connected to the gate of the FET TR11, and a predetermined current flows through the Zener diode ZD2 via the resistance element R2. In this case, if the Zener voltage of the Zener diode ZD2 is set to the gate-source voltage of the FET TR10 + the gate-source voltage of the FET TR11 + α (a voltage that can cover the variation), the voltage of the node B can be kept constant. I can do it.

In this circuit, the Zener diode ZD1
Can eliminate the effect of the junction capacitance of
When the ETTR 10 turns from ON to OFF, it turns OFF with a small delay time. Therefore, the delay time (level detection time) of the rise of the output signal is smaller than that of the circuit of FIG. 1, and high-speed operation is possible. FIG. 4 is a graph comparing the delay times of the circuit of FIG. 3 and the circuit of FIG.
5V, VSS = -150V, ZD2 = 23V, ZD1 =
15V, input signal amplitude 150V, period 8μs
Square wave of c, rise and fall time of square wave is 0.5
It shows a simulation result in the case of μsec. When the REF voltage is in the range of −120 to −50 V, the delay time is small in 0 to 30 nsec in the rise determination and 10 nsec in the fall determination.

This is because ZD is applied between the gate and source of TR10.
This is because, since there is no 1, the charge accumulation time in the junction capacitance of ZD1 is eliminated, and the delay time is reduced. FIG. 5 shows that resistors R1 and R2 are used instead of using the Zener diode ZD2.
Is used to maintain the gate voltage of the FET TR11 at a predetermined voltage. Since this circuit does not use a Zener diode, the variation in the manufacturing process is smaller than that in FIG. 3 and the manufacturing is easy.

Although the Zener diode ZD1 is used in the circuit of FIG. 1, the circuit may be constructed without using the Zener diode ZD1. Also, in the above description,
The voltage of the first power supply is 5V, and the voltage of the second power supply is -150.
Although described as V, the effect of the present invention can be achieved even when the voltage of the first power supply is set to 3 to 5 V and the voltage of the second power supply is set to a range of -200 to -50 V.

[0020]

Since the high voltage level detection circuit according to the present invention is constructed as described above, a high voltage signal of about -140 to -50 V can be easily converted into a low voltage logic signal of 5 V or 0 V. In addition, the conversion can be performed reliably. The circuit of the present invention is suitable for a case where a high-voltage power supply is mounted on a device for adjusting the image quality, such as a PDP (plasma display panel), for each panel.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first specific example of the present invention.

FIG. 2 is a diagram illustrating the operation of FIG.

FIG. 3 is a circuit diagram of a second specific example of the present invention.

FIG. 4 is a graph showing delay characteristics of the present invention.

FIG. 5 is a circuit diagram of a third specific example of the present invention.

[Explanation of symbols]

 TR1 to TR11 Transistors ZD1, ZD2 Zener diodes D1, D2 Diodes R1 to R3 Resistance VDD First power supply VSS Second power supply GND Third power supply DEF Differential circuit CM Current mirror circuit SH Level shift circuit INV Inverter circuit Vin High voltage Signal Vref reference voltage

Claims (8)

[Claims] A first power supply, a second power supply, and a third power supply. The first and second transistors are powered by the first power supply and the second power supply. A current mirror circuit which is a load of the differential circuit, a reference voltage applied to one input of the differential circuit, and a high voltage input applied to the other input of the differential circuit. And a level shift circuit provided between the current mirror circuit and the inverter circuit, wherein the high voltage includes a signal, an inverter circuit using the first power source and the third power source as power sources. Level detection circuit. 2. The level shift circuit includes: a first power supply, a resistance element provided at an input of the inverter circuit, a first diode having an anode connected to the input of the inverter circuit, and a third diode. A second diode having an anode connected to the power supply and a cathode connected to the cathode of the first diode; and a third transistor provided between the cathode of the first diode and the second power supply. 2. The high voltage level detection circuit according to claim 1, wherein: 3. The high voltage level detection circuit according to claim 2, wherein a Zener diode is provided between a gate and a drain of said third transistor. 4. A first circuit to which a high voltage of the differential circuit is inputted.
3. A transistor according to claim 1, wherein a fifth transistor is provided between said transistor and a fourth transistor which is a load of said transistor, and a gate of said fifth transistor is fixed at a predetermined voltage. High voltage level detection circuit. 5. The voltage of the first power supply is a positive voltage,
The voltage of the second power supply is a negative voltage, and the voltage of the third power supply is a ground potential.
5. The high voltage level detection circuit according to any one of claims 1 to 4. 6. The device according to claim 1, wherein at least the differential circuit, the current mirror circuit, the inverter circuit, and the level shift circuit are formed on one main surface of a semiconductor substrate. Voltage level detection circuit. 7. A method for converting a high voltage signal to a low voltage logic signal, comprising: a first power supply; a second power supply;
A third power supply, wherein the high-voltage signal is input to a differential circuit provided between the first power supply and the second power supply, and the differential circuit converts the high-voltage signal to a reference voltage. Wherein the comparison result is led to an inverter circuit provided between the first power supply and the third power supply via a level shift circuit to obtain a low-voltage logic signal. Voltage level detection method. 8. The method for detecting a high voltage level according to claim 7, wherein the voltage of the first power supply is 3 to 5 V, and the voltage of the second power supply is -200 V to -50 V.