JPH11177403A - Reset signal detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a reset voltage without consuming current from a power supply in a standby state. SOLUTION: A charge storage means 1 stores charges fed from a main body circuit via a charge storage switch means 2 in the operating mode, and the reset signal detection circuit consumes the charges stored in the main body circuit, since the charge storage switch means 2 becomes open in the standby mode so as to electrically isolate the main body circuit from the reset signal detection circuit. Furthermore, the charges stored in the charge storage means 1 are discharged via a stored charge discharge means 3' then it is detected that a voltage applied to a first input terminal IN1 has reached the level lower than a prescribed voltage. Thus, the voltage for resetting the main body circuit is surely detected, without consuming the charges stored in the main body circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal detection circuit, and more particularly, to a reset signal detection circuit suitable for use in a slave unit of a data carrier system for transmitting operating power of a slave unit from a master unit.

[0002]

2. Description of the Related Art Recently, in a data carrier system, a slave unit does not have an operating power source, and a high frequency signal supplied from a master unit is received and rectified by a built-in antenna to generate operating power. I have.

[0003] Therefore, when a high-frequency signal is constantly transmitted from the master unit, power during operation can always be generated, so that there is no inconvenience of insufficient operating power. However, depending on the signal modulation method or the procedure for transmitting the signal, a non-power supply period during which no signal is transmitted from the parent device to the child device may be set.

[0004] When the non-power supply period is set, no operating power can be generated during that period, so that in the slave unit, the power supply is cut off and the circuit may run away. In order to prevent such a problem, a standby mode is provided in which a data holding capacitor is provided in the slave unit and data is held by the electric charge stored in the data holding capacitor.

In the standby mode,
In the slave unit, the power consumption is minimized by stopping the operation during the non-power supply period, and the data of the state immediately before the stop of the operation is held by the charge of the internal holding capacitor.

By the way, in a use environment of a data carrier, a slave starts operating when approached to a master,
A predetermined operation set in advance is performed by communicating with the master unit. However, after the operation of the slave unit is started and before a series of data transfer and processing is completed, the slave unit is taken out of the communicable area of the master unit or remains in the communicable area. Due to the change in the orientation of the slave, the signal may not be transmitted from the master to the slave.

Since the data carrier system is constructed in consideration of such a case as well, a response such as an instruction to bring the slave unit closer to the master unit again or no display indicating the completion of processing is issued from the master unit. It has become.

Therefore, even if the communication is suddenly interrupted during the processing, the slave does not run away. When the communication is interrupted, the operation is stopped and the mode shifts to the standby mode, and the charge of the data holding capacitor in the slave is reduced. As long as it remains, the state immediately before the operation is maintained.

Since it is difficult to increase the amount of charge that can be stored in the data holding capacitor, there is a predetermined limit to the time during which data can be held. Therefore, when the standby time becomes long and it becomes difficult to hold the data, the state of the slave unit is reset to the initial state. In order to perform this reset reliably, it is necessary to reliably detect the reset voltage. Conventionally, a reset signal detection circuit is provided in the slave unit to detect the reset voltage.

FIG. 3 shows an example of a conventional reset signal detection circuit. This reset signal detection circuit includes N-type MOS transistors Q21 and Q22, and applies the power supply voltage V _DD of the main circuit to the sources of these transistors Q21 and Q22. Then, the N-type MOS transistor Q2
The reference voltage from the reference power supply 20 is applied to the gate of the transistor 1, and the same power supply voltage V _DD as the source is applied to the gate of the N-type MOS transistor Q22.

The N-type MOS transistor Q2
P-type MOS transistors Q2
3, 24 sources are connected and these MOs
The gates of the S transistors Q23 and Q24 are commonly connected to the drain of the MOS transistor Q24, and the drain of the MOS transistor Q23 is connected to the output terminal OUT.

Further, the N-type MOS transistor Q2
N-type MOS transistors Q2
The sources of the transistors 5 and 26 are connected to each other, and the gates of the N-type MOS transistors Q25 and Q26 are connected to the bias circuit 27. The drains of the N-type MOS transistors Q25 and Q26 are connected to the ground potential.

[0013]

[SUMMARY OF THE INVENTION When a conventional reset signal detection circuit configured as described above, compares the reference voltage 20 and the power supply voltage V _DD, when the power supply voltage V _DD falls below the set value It operates so as to output a reset signal from the output terminal OUT.

Therefore, according to the conventional reset signal detection circuit shown in FIG. 3, it is possible to detect satisfactorily that it becomes difficult to hold data in the main circuit. However, there is a problem that the reference power supply 20 in the reset signal detection circuit consumes power and also consumes power during the operation of comparing voltages.

Therefore, in the standby mode, the reference voltage is switched to the holding voltage by the capacitor, and the intermittent operation is performed in order to suppress the current consumption in the comparison circuit. Therefore, there is a problem that current consumption cannot be eliminated.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to make it possible to detect a reset voltage without consuming current of a main circuit during standby.

[0017]

According to the present invention, there is provided a reset signal detecting circuit comprising: a first input terminal to which an operating voltage of a main circuit is applied; and a second input terminal for inputting a mode switching signal sent from the main circuit. An input terminal, an electric charge accumulating means for accumulating electric charge input from the main circuit via the first input terminal, and an on-operation when the mode switching signal is in an operation mode, the first input terminal And the charge storage means are connected to a closed circuit, and charges from the main circuit are stored in the charge storage means. When the mode switching signal is in a standby mode, the charge storage means and the main circuit are turned off. A charge storage switch for electrically disconnecting the charge storage device from the first input terminal; and turning off the charge storage device when the voltage applied to the first input terminal is higher than a predetermined voltage value. The charge means is held in a charge storage state, and when the voltage applied to the first input terminal is lower than a predetermined voltage value, an ON operation is performed to discharge the charge stored in the charge storage means. Based on the discharged charge of the charge storage means discharged through the stored charge discharge means,
A detection circuit for detecting that the voltage applied to the input terminal of the first circuit becomes lower than a predetermined voltage value, and a reset signal output terminal for outputting the detection result of the detection circuit to the outside as a reset signal. It is characterized by.

Another feature of the present invention is that
The operating voltage of the main circuit applied to the first input terminal is a power supply voltage of the main circuit.

According to another feature of the present invention, the detection circuit accumulates the discharge charge of the charge storage means discharged through the storage charge discharge means, and stores a voltage corresponding to the amount of the stored charge. Characterized in that it has a capacitor for accumulating discharge charges that generates

Another feature of the present invention is that the reset signal output terminal is connected to a gate terminal of a MOS transistor. Another feature of the present invention is that a first input terminal to which an operating voltage supplied to the main body circuit is applied and a second input terminal for inputting a mode switching signal sent from the main body circuit. An input terminal, a charge storage capacitor for storing charge input from the main circuit through the first input terminal, a source connected to the first input terminal, and a drain connected to the charge storage capacitor. And the gate is connected to the second input terminal, and when the mode switching signal is in the operation mode, it is turned on to close the first input terminal and the charge storage capacitor. To store the charge in the charge storage capacitor, and when the mode switching signal is in the standby mode, turn off to operate the charge storage capacitor. A MOS transistor switch for the capacitors and the body circuit to electrically disconnect, with the source to the drain and the charge storage capacitor of the MOS transistor for the switch is connected,
When the gate is connected to the first input terminal and the voltage applied to the first input terminal is higher than a predetermined voltage value, the gate is turned off, and the gate is connected to the first input terminal. When the applied voltage is lower than a predetermined voltage value, a discharging MOS transistor that is turned on to discharge the charge stored in the charge storage capacitor, and a charge storage transistor that is discharged through the discharge MOS transistor. A capacitor for accumulating discharge charge of the capacitor and generating a voltage corresponding to the amount of accumulated charge, and a capacitor for discharge charge accumulation, which is connected in parallel with the capacitor for discharge charge accumulation,
A bypass MOS transistor for preventing the discharge charge storage capacitor from being charged by a leakage current when the discharge MOS transistor is off;
A reset signal output terminal for outputting a voltage generated by the discharge charge storage capacitor as a reset signal to the outside, and a gate connected to the second input terminal while being connected in parallel with the discharge charge storage capacitor When the mode switching signal is in the operation mode, the operation is turned on to hold the discharge charge storage capacitor in a discharging state, and when the mode switching signal is in the standby mode, the operation is turned off to charge the discharge charge storage capacitor. It is characterized by comprising a storage control MOS transistor for setting a storage state, and a polarity inversion circuit interposed between the gate of the storage control MOS transistor and the reset signal output terminal.

Another feature of the present invention is that the reset signal output terminal is connected to a gate terminal of a MOS transistor.

Another feature of the present invention is that the switching MOS transistor is a P-type MOS transistor.
A transistor, and an N-type MOS transistor is connected in parallel with the P-type MOS transistor as a second switching MOS transistor, and the output of the polarity inversion circuit is supplied to the gate of the second switching MOS transistor. It is characterized by doing.

[0023]

Since the present invention has the above technical means, the electric charge supplied from the main circuit through the electric charge accumulation switch means is accumulated in the electric charge accumulation means in the operation mode, and the electric charge accumulation switch means is turned off in the standby mode. By doing so, the main body circuit and the reset signal detection circuit are electrically insulated, so that the charge stored in the main body circuit is not consumed by the reset signal detection circuit in the standby mode.

In the standby mode, the charge stored in the charge storage means is discharged through the stored charge discharging means, and the first input terminal is connected to the first input terminal based on the discharge charge of the charge storage means. It is detected that the applied voltage is lower than a predetermined voltage value.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a reset signal detection circuit according to the present invention will be described with reference to the drawings. FIG.
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG.
As shown in the figure, the reset signal detection circuit of the present embodiment has a first input terminal IN1, a second input terminal IN2, and an output terminal OUT.

The first input terminal IN1 is connected to the first switch means SW ₁ constituting the charge storage switch means 2.
One end is connected to the first gate of the MOS transistor Q ₁ is connected. Further, the first source of the MOS transistor Q ₁ is connected to the said first end of the switch means SW _1.

[0027] That is, the first source of the MOS transistor Q ₁ is connected to the first input terminal IN1 through the first switch means SW _1. Further, in the first end of the switch means SW _1, the first capacitor C ₁ is connected. The first capacitor C ₁ is a capacitor constituting the charge storage means 1.

[0028] MOS transistors to Q ₁ the first is a transistor constituting the accumulated charge-discharge unit 3, its drain connected to the source of the second MOS transistor Q _2. Further, the second MOS transistor Q ₂
The sources, a second MOS transistor Q ₂ of the gate, the second end of the capacitor C _2, the second switch means SW ₂ at one end, and the output terminal OUT are connected. The detection circuit 4 is constituted by the second MOS transistor Q ₂ and the second capacitor C ₂ .

Further, the second MOS transistor Q ₂
, The first and second capacitors C ₁ , C _1
2 of the other end, and a second end of the switch means SW ₂ is connected to a reference potential (ground potential). In the present embodiment, the said second switch means SW ₂ is composed of N-type MOS transistor Q _4.

The reset signal detection circuit of the present embodiment configured as described above detects whether the main circuit (not shown) is in the standby mode and is connected to the first input terminal IN1. Potential point, for example, the power supply voltage V _DD
And are connected.

Further, in the second switch means SW ₂ have been made as a switching signal in the standby mode is entered, when the main body circuit (not shown) is in operation, the first switch means SW ₁ and the 2 switch means SW
₂ are controlled to be turned on together. Further, when the main body circuit (not shown) is in standby mode, the first switch means SW ₁ and the second switch means SW ₂ is controlled to be turned off together.

In the example of FIG. 1, the P-type MOS transistor Q
₃ constitutes the first switch means SW ₁ , and the N-type M
The second switching means SW by the OS transistor Q _4
2 are configured. Therefore, in order to realize the control as described above, the second signal input to the input terminal IN2 is supplied directly to the gate of the P-type MOS transistor Q _3, the via the polarity inversion circuit INV N It is to be supplied to the gate of the type MOS transistor Q _4.

Further, the second capacitor is connected to the first capacitor C ₁ .
Of the capacitor C ₂ is set to about 1/3 to 1/30, and the second MOS transistor Q ₂ is
It is set to several times the area - the area of the MOS transistor the same extent as the Q ₁ of. Further, an external circuit connected to the output terminal OUT includes a gate of a MOS transistor, for example,
It is limited to a simple CMOS inverter gate.

Next, the operation of the reset signal detection circuit of the present embodiment having the above-described configuration will be described. When the main body circuit (not shown) is in operation, since the first switch means SW ₁ is turned on, the voltage applied to the first MOS transistor the gate and the source of Q ₁ is both a first input terminal This is the voltage applied to IN1. Therefore, in this case, the power supply voltage V
_DD .

[0035] In this case, since the potential of the gate and the source are equal, the first MOS transistor Q ₁ is turned off, the operating current does not flow. Further, since the first switch means SW ₁ is turned on, the first capacitor C ₁ is the power supply voltage V
It is charged to the potential of _DD . Also, the second switch means S
Since W ₂ is also turned on, the output terminal OUT will be connected to a reference potential, the logic level of the output terminal OUT is in the "L" level.

When the main circuit shifts to the standby mode, the first switch means SW ₁ and the second switch means SW ₂ are turned off in response to the standby mode switching signal input to the second input terminal IN ₂ . . At this time, the power supply voltage V _DD of the unillustrated main body circuit is the same as that during operation, or slightly rises because the operating current has disappeared. In this state, the first MOS transistor Q ₁ is so turned off, the charge accumulated in the first capacitor C ₁ is not discharged. Therefore, the logic level of the output terminal OUT at this time remains at "L" level.

By the way, the first MOS transistor Q ₁
However, even when the transistor is turned off, a small leak current due to the reverse bias of the PN junction on the structure flows from the source to the drain. Therefore, in the present embodiment, the leakage current is compensated by flowing to the ground via the _second MOS transistor Q2 which is similarly turned off.

When the power supply voltage V _DD of the main circuit (not shown) drops due to the long standby time, the voltage applied to the gate drops, so that the first MOS transistor Q ₁ turns on. Thereby, the first capacitor C
_The charge that has been charged to 1 becomes the first MOS transistor Q
₁ moves the second to the capacitor C ₂ through, so that the terminal voltage rises, the potential of the output terminal OUT rises.

At this time, if the load connected to the output terminal OUT has a DC power path, the potential does not rise. However, as described above, only the gate of the MOS transistor is connected to the output terminal OUT. The potential of the terminal OUT rises without any problem.

Incidentally, since the main circuit (not shown) has a larger circuit scale, the leakage current is larger. For this reason, the first capacitor C of the reset signal detection circuit of the present embodiment is
_Although the capacity of ₁ is small, the power supply voltage V
_The potential can be held for a longer time than _DD .

Next, a second embodiment of the present invention will be described with reference to FIG. Example shown in FIG. 2, when the first control switching of the switch means SW _1, in particular, to ensure that the potential of the first capacitor C ₁ by a control signal that swings in the positive direction is not changed when turning off, the with a larger capacity, it is disposed an N-type MOS transistor Q ₅ of the fifth,
And to reduce the effect by applying a control signal of opposite phase to the MOS transistor Q ₅ of the fifth.

In the above-described embodiment, the charge stored in the first capacitor C ₁ is moved to the second capacitor C _2, and the reset signal is generated by increasing the terminal voltage of the second capacitor C _2. An example was shown.
In this way, since the electric charge discharged set aside in the second capacitor C _2, without being restricted by the detection timing, the first charge and discharge of the capacitor C ₁ can be accurately detected.

However, various methods can be used as a method of detecting the discharge of the first capacitor C ₁ and generating the reset signal. For example, to dispose the load resistor to the second place of the capacitor C _2, the charge and discharge of the first capacitor C ₁ may be to increase the terminal voltage of the load resistor.

[0044]

According to the present invention, as described above, according to the present invention, in the operation mode, the electric charge supplied from the main circuit through the electric charge accumulation switch means is accumulated in the electric charge accumulation means.
In the standby mode, by turning off the charge storage switch means, the main body circuit and the reset signal detection circuit are electrically insulated, and the charge stored in the charge storage means is discharged. Since the reset voltage indicating that the voltage of the main circuit applied to the first input terminal is lower than a predetermined voltage value is detected based on the charge, the voltage value of the main circuit is detected. The decrease can be reliably detected by a small-scale circuit, and the electric charge accumulated in the main circuit can be prevented from being consumed in the standby mode.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 charge storage means 2 charge storage switch means 3 stored charge discharge means 4 detection circuit IN1 First input terminal IN2 Second input terminal Q ₁ First MOS transistor Q ₂ Second MOS transistor Q ₃ Third MOS transistor Q ₄ Fourth MOS transistor SW ₁ First switch means SW ₂ Second switch means

Claims (7)

[Claims] A first input terminal to which an operating voltage of a main circuit is applied; a second input terminal for inputting a mode switching signal sent from the main circuit; and a first input terminal. Charge accumulation means for accumulating the electric charge inputted from the main body circuit, and turning on when the mode switching signal is in an operation mode to connect the first input terminal and the charge accumulation means to a closed circuit; Charge storage switch means for storing charge from the main body circuit in the charge storage means, and turning off when the mode switching signal is in a standby mode to electrically disconnect the charge storage means and the main body circuit; When the voltage applied to the first input terminal is higher than a predetermined voltage value, an off operation is performed to hold the charge storage means in a charge storage state, When the voltage applied to the first input terminal is lower than a predetermined voltage value, the stored charge discharging means turns on to discharge the charge stored in the charge storage means; A detection circuit for detecting that a voltage applied to the first input terminal is lower than a predetermined voltage value based on a discharge charge of the charge storage means discharged through the detection circuit; A reset signal output terminal for outputting a detection result of the above to the outside as a reset signal. 2. The reset signal detection circuit according to claim 1, wherein the operating voltage of the main circuit applied to the first input terminal is a power supply voltage of the main circuit. 3. The discharge circuit according to claim 2, wherein the detection circuit includes a discharge charge storage capacitor that stores the discharge charge of the charge storage means discharged through the storage charge discharge means and generates a voltage corresponding to the amount of the stored charge. The reset signal detection circuit according to claim 1 or 2, wherein: 4. The reset signal detection circuit according to claim 3, wherein said reset signal output terminal is connected to a gate terminal of a MOS transistor. 5. A first input terminal to which an operating voltage supplied to a main body circuit is applied; a second input terminal for inputting a mode switching signal sent from the main body circuit; A charge storage capacitor for storing charge input from the main body circuit via an input terminal; a source connected to the first input terminal; a drain connected to the charge storage capacitor; Is connected to the second input terminal, and is turned on when the mode switching signal is in the operation mode to connect the first input terminal and the charge storage capacitor to a closed circuit to connect the charge storage capacitor In addition to accumulating electric charge in the capacitor, the capacitor is turned off when the mode switching signal is in the standby mode, and the main circuit and the electric charge storage capacitor are electrically connected. A switching MOS transistor to be electrically disconnected, a source connected to the drain of the switching MOS transistor and the charge storage capacitor, and a gate connected to the first input terminal; When the voltage applied to the first input terminal is higher than a predetermined voltage value, the operation is turned off. When the voltage applied to the first input terminal is lower than the predetermined voltage value, the operation is turned on. A discharge MOS transistor for discharging the charge stored in the charge storage capacitor; and a discharge charge of the charge storage capacitor discharged through the discharge MOS transistor; and a voltage corresponding to the amount of stored charge. The discharge charge storage capacitor to be generated, and the discharge charge storage capacitor connected in parallel with the discharge charge storage capacitor. A bypass MOS transistor for preventing the discharge charge storage capacitor from being charged by a leak current when the use MOS transistor is off; and a voltage generated by the discharge charge storage capacitor as a reset signal to the outside. A reset signal output terminal to be output to the outside and the discharge charge storage capacitor are connected in parallel, and the gate is connected to the second input terminal. A storage control MOS transistor for holding the discharge charge storage capacitor in a discharge state and turning off the discharge charge storage capacitor when the mode switching signal is in a standby mode to place the discharge charge storage capacitor in a charge storage state; MOS transistor gate and reset signal Reset signal detection circuit, characterized by comprising a polarity inversion circuit which is interposed between the force terminal. 6. The reset signal detection circuit according to claim 5, wherein said reset signal output terminal is connected to a gate terminal of a MOS transistor of an external circuit. 7. The switching MOS transistor is P
And the P-type MOS transistor
7. An N-type MOS transistor is connected as a second switch MOS transistor in parallel with an OS transistor, and an output of the polarity inversion circuit is supplied to a gate of the second switch MOS transistor. 2. The reset signal detection circuit according to 1.