JPH11177056A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate need of conformal deposition of a capacitor insulating film, to avoid damage to the capacitor insulating film when an electrode film is deposited, and then, to form a capacitor through a simple process. SOLUTION: A method for manufacturing a semiconductor device includes a process of forming both electrodes 25 and 27 of a capacitor on the main surface side of a semiconductor substrate 11, and another process of forming a dielectric film 28 of the capacitor in contact with the side faces of the electrodes 25 and 27 of the capacitor. The capacitor is formed of the electrodes 25 and 27 and the dielectric film 28 formed between the electrodes 25 and 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a capacitor used in a memory device.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become more highly integrated, memory cells have been miniaturized along with miniaturization of minimum processing dimensions. However, even if the memory cell area is reduced, the capacitance of the capacitor (storage capacitance: Cs) cannot be reduced too much in terms of sense sensitivity and soft error. As a method of solving this, a method of forming a capacitor three-dimensionally and increasing the capacitor surface area with a small cell area as much as possible to increase the capacitor capacity has been studied.

However, with the generation of design rules of about 0.15 μm (corresponding to the 1 Gbit DRAM generation), it becomes increasingly difficult to process storage node electrodes (SN electrodes) having complicated three-dimensional shapes. ing. It has also become difficult to conformally deposit a capacitor insulating film on a fine and complicatedly processed SN electrode and a plate electrode (PL electrode) thereon.
In addition, when depositing the electrode film on the capacitor insulating film, there is a problem that the underlying capacitor insulating film is damaged. Further, there is a problem that the number of steps for processing these complicated electrodes and capacitor insulating films increases.

[0004]

As described above, in the above-described conventional capacitor structure, it is difficult to conformally deposit a capacitor insulating film on a fine and complicatedly processed electrode. There is also a problem that the underlying capacitor insulating film is damaged during the deposition, and that the number of steps is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is not necessary to conformally deposit a capacitor insulating film, and it is possible to avoid damage to the capacitor insulating film due to deposition of an electrode film. It is another object of the present invention to provide a semiconductor device capable of forming a capacitor by a simple process and a method for manufacturing the same.

[0006]

A method of manufacturing a semiconductor device according to the present invention (manufacturing method A) includes a step of forming one electrode and another electrode of a capacitor on a main surface side of a semiconductor substrate, and thereafter, Forming a dielectric film of the capacitor in contact with a side surface of one electrode and the other electrode of the capacitor, the dielectric film sandwiched between the one electrode and the other electrode of the capacitor and the side walls thereof; A capacitor is formed by the method.

The one electrode is, for example, an SN electrode, and the other electrode is, for example, a PL electrode. As a constituent material of these electrodes, for example, a metal such as Ru whose oxide has conductivity can be used. It is preferable to use a high dielectric film such as a (Ba, Sr) TiO ₃ film as the dielectric film, but it is also possible to use a silicon oxide film or a silicon nitride film.

According to the invention, since the capacitor dielectric film is formed in the region sandwiched between the one electrode and the other electrode, there is no need to conformally deposit the capacitor insulating film. Further, since the capacitor dielectric film is formed after forming one electrode and the other electrode, damage to the capacitor insulating film due to deposition of the electrode film can be avoided. Further, since it is not necessary to perform complicated electrode processing or the like, the number of steps for manufacturing a capacitor can be reduced. Furthermore, since a capacitor dielectric film is formed in a region sandwiched between the side walls of one electrode and the other electrode, increasing the thickness of the electrode (the thickness in the direction perpendicular to the substrate surface) increases The capacity can be increased.

As a production method based on the production method A,
The following production methods B and C can be given. The manufacturing method B includes a step of forming one electrode of the capacitor on the main surface side of the semiconductor substrate, a step of forming a dummy film on a side wall of the one electrode of the capacitor, and a step of filling the gap between the dummy films. Forming the other electrode of
Removing the dummy film, and forming a dielectric film of the capacitor in a region where the dummy film has been removed, the capacitor being sandwiched between one electrode and the other electrode of the capacitor and their side walls. A capacitor is formed with the dielectric film.

According to the manufacturing method B, since the capacitor dielectric film is formed in the region where the dummy film formed on the side wall of the one electrode is removed, the capacitor dielectric film has the thickness of the dummy film on the side wall portion. Thickness is decided. Therefore, a capacitor dielectric film having a small thickness can be obtained, and the capacitance of the capacitor can be increased.

In the manufacturing method C, one electrode and the other electrode of the capacitor are simultaneously formed on the main surface side of the semiconductor substrate, and the capacitor in contact with the side surface of the one electrode and the other electrode of the capacitor formed at the same time. Forming a dielectric film, wherein one electrode and the other electrode of the capacitor and the dielectric film sandwiched between these side walls form a capacitor.

According to the manufacturing method C, since the one electrode and the other electrode of the capacitor are formed simultaneously, the number of steps for manufacturing the capacitor can be further reduced.

In the manufacturing method C, the step of simultaneously forming one electrode and the other electrode of the capacitor includes the step of forming a conductor film to be one electrode and the other electrode of the capacitor, Forming a first mask film on the body film, forming a second mask film on a side wall of the first mask film, and using the first and second mask films as a mask to form the conductor It is effective to include a step of removing the film.

According to this method, since the second mask film is formed on the side wall of the first mask film, the size of the second mask film formed on the side wall of the first mask film is smaller than the dimension determined by lithography. The gap between one electrode and the other electrode can be reduced by twice the film thickness. Therefore, it is possible to form a capacitor dielectric film having a small thickness, and it is possible to increase the capacitance of the capacitor.

Further, in the above-mentioned manufacturing methods A to C, a plurality of one electrodes of the capacitor may be formed apart from each other, and the other electrode of the capacitor may be formed so as to surround the plurality of one electrodes. preferable.

According to this structure, since the capacitor dielectric film is sandwiched between one electrode and the other electrode surrounding the periphery of the side wall, the area of the capacitor can be increased, and the capacitance of the capacitor can be increased. Can be.

The shape of one of the electrodes may be a polygonal prism such as a quadrangular prism, or the like. Deterioration of the withstand voltage of the capacitor insulating film due to concentration can be prevented.

According to the semiconductor device of the present invention, one electrode and the other electrode of a capacitor formed on the main surface side of the semiconductor substrate with substantially uniform thickness, and one electrode and the other electrode of the capacitor are provided. It has a dielectric film of a capacitor in contact with a side surface, and the capacitor is constituted by one electrode and the other electrode of the capacitor and the dielectric film sandwiched between these side walls.

According to the invention, since the useless unevenness is not formed on one electrode and the other electrode of the capacitor, the area of the electrode can be reduced as compared with the case where the unevenness is formed, and The area of the entire chip of the device can be reduced.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B are diagrams showing a schematic configuration of a memory cell of a DRAM according to an embodiment of the present invention. FIG. 1A is a plan view thereof, and FIG.
It is A 'sectional drawing. FIG. 2 is a plan view showing a schematic configuration when a plurality of memory cells shown in FIG. 1 are arranged (here, arranged for 4 bits).

In FIG. 1, a trench-type element isolation 12 is formed on a p-type silicon substrate 11 (or an n-type silicon substrate), and a gate insulating film 13 and a gate electrode (for example, a word line) are formed. , Poly-Si film 14 and W
A MOS transistor is formed by the polycide structure composed of the Si ₂ film 15, the gate cap film 16, the gate side wall film 17 composed of the silicon nitride film, and the source / drain diffusion layers. Further, interlayer insulating films 19, 21,
An n ⁺ polycrystalline silicon film 20 and a tungsten film (W film) 23 connected to the source / drain diffusion layers 18 are formed in openings formed in the stopper film 22 and the etching stopper film 24.

A storage node electrode (SN electrode) 25 serving as one electrode of a capacitor is formed on the tungsten film 23.
(For example, a ruthenium film (Ru film) is connected), and a plate electrode (PL electrode) 27 (for example, a ruthenium film (Ru film) is used), which is the other electrode of the capacitor, is formed so as to surround the SN electrode 25. And SN
A capacitor insulating film 28 (for example, using a (Ba, Sr) TiO ₃ film) is formed on a region sandwiched between the side walls of the electrode 25 and the PL electrode 27, and on the SN electrode 25 and the PL electrode 27 (FIG. 1). (A), for convenience, the SN electrode 2
Only the region between the side walls of the fifth and PL electrodes 27 is hatched in the capacitor insulating film 28. ). Note that the capacitor insulating film 28 only needs to be formed in a region sandwiched between the sidewalls of the SN electrode 25 and the PL electrode 27, and does not necessarily need to be formed on the SN electrode 25 and the PL electrode 27. A capacitor which is a component of a DRAM memory cell includes an SN electrode 25, a PL electrode 27, and a capacitor insulating film 28 formed in a region sandwiched between these side walls.
Will be composed by

Next, a first example of a manufacturing method for manufacturing the semiconductor device shown in FIGS. 1 and 2 will be described. First, as shown in FIG. 3A, the impurity concentration is 5 × 10 ¹⁵ c
On the (100) plane of the p-type silicon substrate 11 (or n-type silicon substrate) of about m ⁻³ , a p-well (n is
(Well) (not shown). Subsequently, the Si substrate 11 is formed using, for example, a reactive ion etching (RIE) method.
A so-called trench type element isolation 12 (trench depth of about 0.2 μm) is formed by burying an insulating film in this groove.

Next, a gate insulating film 13 having a thickness of about 6 nm
Is formed, and a gate electrode (word line) is formed on the gate insulating film. In this example, to reduce the resistance,
A so-called polycide structure (for example, each having a film thickness of 50 n
m of a poly-Si film 14 and a WSi ₂ film 15). First, the poly-Si film 14 and the WS
After the i ₂ film 15 is formed, a gate cap film 16 made of a silicon nitride film (Si ₃ N ₄ film) is formed on the WSi ₂ film 15 as an etching stopper for a gate electrode in a later self-alignment process. I do. Thereafter, a resist pattern (not shown) is formed on the gate cap film 16, the gate cap film 16 is processed using the resist pattern as a mask, and the processed gate cap film 16 is used as a mask. Poly Si film 14 and WS
The gate electrode is formed by processing the i ₂ film 15. Thereafter, the gate electrode and the low concentration impurity diffusion layer 18 are formed.
(Formed in a later step) to improve the breakdown voltage in an oxygen atmosphere at 1050 ° C. for about 100 seconds, for example.
Thermal oxidation by TO is performed to form a so-called post-oxide film (not shown).

Next, in order to form an LDD structure, after forming a silicon nitride film (for example, a film thickness of about 10 nm), a gate side wall film 17 is formed by a side wall leaving method by etching the entire surface using RIE. . Subsequently, using a resist pattern (not shown), the gate cap film 16 and the gate side wall film 17 as a mask, an n ⁻ diffusion layer 18 serving as a source / drain is formed in the surface region of the Si substrate 11 by ion implantation.

Next, a BPSG film, for example, having a thickness of about 500 nm is deposited as an interlayer insulating film 19 on the entire surface by a CVD method, and the surface thereof is subjected to an interlayer insulating film on the gate cap film 16 by, for example, a CMP (chemical mechanical polishing) method. Membrane 1
9 is polished and flattened to a thickness of about 100 nm.

Next, a contact hole for making contact between the n ⁻ -type impurity diffusion layer 18 and the bit line and the SN electrode portion is opened in the interlayer insulating film 19, and an n ⁺ -type poly-Si film 20 is formed on the contact hole. Embed completely in the hall. For this embedding, for example, a CMP method is used. The contact hole is etched by a high selectivity RIE method (etching of the BPSG film) such that the etching rate differs between the BPSG film used as the interlayer insulating film 19 and the silicon nitride film of the gate cap film 16 by 10 or more. Rate is Si
₍ 10 times or more faster than ₃ N ₄ film). By doing so, it is possible to prevent a short circuit between the n ⁺ -type poly-Si film at the gate electrode and the bit line contact portion, and to improve the product yield.

Next, an interlayer insulating film 21 is formed on the entire surface by, for example, CV.
A bit line contact (not shown) is formed so as to reach the poly-Si film by a method D, and a bit line (for example, using a tungsten film, not shown) electrically connected to the poly-Si film is formed between the layers. A buried formation is performed via the insulating film 21 (a so-called dual damascene process using a CMP method). After that, an interlayer insulating film 22 is formed on the entire surface to planarize the surface, and further, as an etching stopper film required when forming a capacitor,
A silicon nitride film 24 is deposited.

Next, the silicon nitride film 24 and the interlayer insulating film 2
2 and 21 are sequentially etched using a method such as the RIE method, and a contact hole reaching the poly-Si film 20 is opened. Subsequently, after a tungsten film 23 is deposited on the entire surface, the tungsten film on the silicon nitride film 24 is removed by a CPM method or the like, and the tungsten film 23 is buried only in the contact hole. Although a tungsten film is used here, poly Si can be used.

Next, as shown in FIG. 3B, for example, a Ru film 25 is formed as an SN electrode on the entire surface by, for example, a sputtering method. Next, as shown in FIG.
Is etched using a method such as the RIE method to form an SN electrode.

Thereafter, as shown in FIG.
A dummy insulating film 26 such as an S film is deposited on the entire surface. next,
As shown in FIG. 4E, the dummy insulating film 26 is etched using a method such as the RIE method, and Ru serving as an SN electrode is formed.
It is left only on the side wall of the film 25.

Next, as shown in FIG. 4F, for example, a Ru film 27 is deposited on the entire surface as a PL electrode by, for example, a sputtering method. Thereafter, as shown in FIG. 5G, the Ru films 25 and 27 and the dummy insulating film 26 are etched back using a method such as a CMP method to planarize the Ru films. Thereby, S
A PL electrode 27 is formed around the N electrode 25 with a dummy insulating film 26 interposed therebetween. Note that a CVD method may be used instead of the sputtering method for forming the films to be the SN electrode and the PL electrode.

Next, as shown in FIG.
The dummy insulating film 26 such as a film is selectively removed using an etching solution such as an NH ₄ F solution. At this time, the silicon nitride film 24 functions as an etching stopper. Note that the dummy insulating film 26 may be selectively removed using an RIE method or the like.

Next, as shown in FIG. 5I, for example, a (Ba, Sr) TiO ₃ film is deposited on the entire surface as a capacitor insulating film 28 by using, for example, a CVD method. (Ba,
The Sr) TiO ₃ film 28 includes the SN electrode 25 and the PL electrode 2
7 and on the SN electrode 25 and PL
It will be formed on the electrode 27. Note that (Ba, S
r) The TiO ₃ film 28 may be deposited by a sputtering method instead of the CVD method. After this, (Ba, Sr) T
The iO ₃ film 28 may be etched back using, for example, a CMP method to flatten it.

As described above, a capacitor of the DRAM is formed by the SN electrode 25, the PL electrode 27, and the capacitor insulating film 28 formed in the region sandwiched between these side walls.

FIG. 2 is a plan view showing a schematic configuration when a plurality of memory cells manufactured by the above-described manufacturing method are arranged (the SN electrode 25, the PL electrode 27, and the capacitor insulating film). Only the capacitor insulating film 28 is shown. In the capacitor insulating film 28, only the region sandwiched between the side walls of the SN electrode 25 and the PL electrode 27 is hatched.), And the PL electrode 27 becomes a common electrode of all capacitors on the wafer. .

In the above manufacturing method, the dummy insulating film 26
Although a TEOS film was used as an etching stopper film, the etching stopper film 24 (in this example, a silicon nitride film) and SN
Other materials may be used as long as they can be selectively etched away from the electrode 25 (Ru film in this example) and the PL electrode 27 (Ru film in this example). For example, BP
An SG film, an SOG film, or the like can be used.

As described above, according to the above manufacturing method, after the formation of the SN electrode and the PL electrode, the capacitor insulating film is formed in the region sandwiched between the side walls of these electrodes.
Therefore, a capacitor can be formed without performing complicated and difficult processing of an SN electrode or depositing a capacitor insulating film on an SN electrode having a complicated structure, and the number of steps can be reduced. is there. Further, since the area of the capacitor is determined by the film thickness of the SN electrode, the PL electrode, and the capacitor insulating film, the area can be increased by increasing the film thickness in the vertical direction of the silicon wafer.

Next, a second example of a manufacturing method for manufacturing the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIG. Note that the formation of the MOS transistor, the interlayer insulating film, and the like is the same as the step (a) of the first manufacturing method example, and thus these steps will be described with reference to FIG. Here, detailed description is omitted.

After the step of FIG. 3A is completed, FIG.
As shown in (a), a Ru film 31 is deposited on the entire surface as an SN electrode and a PL electrode of a capacitor. Then, FIG.
As shown in (b), for example, using a resist (not shown) patterned by lithography as a mask, the Ru film 31 is etched by RIE or the like, and an SN electrode 31a and a PL electrode 31b are simultaneously formed in the same step. I do.

Next, as shown in FIG. 6C, a (Ba, Sr) TiO ₃ film 32 is formed as a capacitor insulating film by CVD.
It deposits using the method or the sputtering method. (Ba, Sr)
The TiO ₃ film 32 includes an SN electrode 31a and a PL electrode 31b.
Sandwiched between the side walls and on the SN electrode 31a and PL
It will be formed on the electrode 31b. After this,
The (Ba, Sr) TiO ₃ film 32 may be etched and flattened using, for example, a CMP method.

As described above, the SN electrodes 31a, PL
The capacitor of the DRAM is formed by the electrode 31b and the capacitor insulating film 32 formed in the region sandwiched between these side walls.

In this manufacturing method example, the same effect as in the first manufacturing method example can be obtained, and the number of steps can be reduced as compared with the first manufacturing method example. Next, a third example of a manufacturing method for manufacturing the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIGS.

This example is a modification of the second example of the manufacturing method shown in FIG. 6, and particularly relates to the step (b) of the second example of the manufacturing method. Therefore, the other steps are referred to the example of the second manufacturing method shown in FIG. 6, and the detailed description is omitted.

After a Ru film 31 serving as an SN electrode and a PL electrode is deposited on the entire surface in the step of FIG. 6A, an insulating film is formed on the Ru film 31 as a first mask as shown in FIG. 3
3 (for example, a SiO ₂ film) is deposited, and the insulating film 33 is etched using lithography and RIE.

Next, as shown in FIG. 7B, an insulating film 34 (for example, SiO ₂ film) is
After the entire surface is deposited by using the VD method, it is left only on the side wall of the insulating film 34 serving as a first mask by using the RIE method.

Next, as shown in FIG. 7C, RIE is performed using the first mask 33 and the second mask 34 as masks.
The Ru film 31 is etched using a method or the like to form an SN electrode 31a and a PL electrode 31b. Then the first
Then, the mask 33 and the second mask 34 are removed, and then the formation of the capacitor insulating film 32 and the like may be performed as shown in FIG.

According to this manufacturing method, the gap between the SN electrode and the PL electrode can be narrowed, that is, the thickness of the capacitor insulating film sandwiched between the SN electrode and the PL electrode can be reduced. Can be increased. That is, the distance between the first masks 33 (the distance a) is the limit width of the etching determined by the limit of the lithography.
3 (the thickness of the second mask 34 at the side wall of the first mask 33 is assumed to be b), the second etching width a is smaller than the etching limit width a determined by the lithography method.
Only twice the film thickness b of the mask 34 (that is, a-2b
And the gap between the SN electrode and the PL electrode can be narrowed.

In the embodiment described above, the shape of the SN electrode is a square pole, but as shown in FIG.
The shape of the electrode may be cylindrical or elliptical. This eliminates a corner where an electric field is concentrated on the surface where the SN electrode 25 and the PL electrode 27 and the capacitor insulating film 28 are in contact with each other, so that deterioration of the withstand voltage of the capacitor insulating film due to the electric field concentration can be prevented. .

As shown in FIG. 9, even if the corner of the SN electrode is rounded, the corner where the electric field is concentrated on the surface where the SN electrode 25 and the PL electrode 27 are in contact with the capacitor insulating film 28 is formed. Can be eliminated. In this case, as shown in FIG.
When the major axis is b and the roundness of the corner is represented by the radius of curvature r, r is “a / 4 ≦ r ≦ 3” for the condition “b ≧ a”.
It is preferable to be within the range of a / 4 ".

As the capacitor insulating film, (B
a, Sr) In addition to a TiO ₃ film, a high dielectric film such as a Ta ₂ O ₅ film, a ferroelectric film such as a (Pb, Zn) TiO ₃ film,
Further, an oxide or nitride of Si may be used.

In addition to the Ru film, the SN electrode and the PL electrode include a Pt film, a Re film, an Ir film, an Os film, a Pd film, and a R film.
It is possible to use a noble metal conductive film such as an h film, an Au film, or an oxide conductor thereof (for example, a RuO ₂ film obtained by oxidizing a Ru film is conductive), for example, RuO ₂
It is also possible to use a laminated structure such as a film / Ru film. Further, different materials can be used for the SN electrode and the PL electrode.

Further, the above-described embodiment is an example in which the present invention is applied to a DRAM. However, the present invention is applied to a semiconductor memory element which accumulates and stores electric charges, for example, an FRAM or the like, like the DRAM. It is also possible. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[0054]

According to the present invention, since a capacitor dielectric film is formed in a region sandwiched between a side wall of one electrode and the other electrode, there is no need to conformally deposit a capacitor insulating film. Further, since the capacitor dielectric film is formed after forming one electrode and the other electrode, damage to the capacitor insulating film due to deposition of the electrode film can be avoided. Further, since it is not necessary to perform complicated electrode processing or the like, the number of steps for manufacturing a capacitor can be reduced. Further, since the capacitor dielectric film is formed in a region sandwiched between the one electrode and the other electrode, the capacitance of the capacitor can be increased by increasing the thickness of the electrode.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a schematic configuration of a memory cell of a DRAM according to an embodiment of the present invention, FIG.
3A is a cross-sectional view taken along line AA ′ of FIG.

FIG. 2 is a plan view showing a schematic configuration when a plurality of memory cells shown in FIG. 1 are arranged.

FIG. 3 is a process cross-sectional view showing a part of a first example of a manufacturing method for manufacturing the semiconductor device shown in FIGS. 1 and 2;

FIG. 4 is a process cross-sectional view showing a part of a first example of a manufacturing method for manufacturing the semiconductor device shown in FIGS. 1 and 2;

FIG. 5 is a process cross-sectional view showing a part of a first example of a manufacturing method for manufacturing the semiconductor device shown in FIGS. 1 and 2;

FIG. 6 is a process sectional view showing main processes in a second example of the manufacturing method for manufacturing the semiconductor device shown in FIGS. 1 and 2;

FIG. 7 is a process cross-sectional view showing main processes in a third manufacturing method example for manufacturing the semiconductor device shown in FIGS. 1 and 2;

FIG. 8 is a view showing an example of another shape of the SN electrode according to the embodiment of the present invention.

FIG. 9 is a diagram showing an example of another shape of the SN electrode according to the embodiment of the present invention.

[Description of Signs] 11 silicon substrate 12 element isolation region 13 gate insulating film 14 poly Si film (gate electrode) 15 WSi ₂ film (gate electrode) 16 gate cap film 17 gate side wall film 18 source Drain diffusion layers 19, 21, 22 ... interlayer insulating film 20 ... n ⁺ polycrystalline silicon film 23 ... tungsten film 24 ... stopper film for etching 25 ... SN electrode 26 ... dummy insulating film 27 ... PL electrode 28 ... capacitor insulating film 31a ... SN electrode 31b ... PL electrode 32 ... Capacitor insulating film 33 ... First mask 34 ... Second mask

Claims (6)

[Claims] 1. A step of forming one electrode and the other electrode of a capacitor on a main surface side of a semiconductor substrate, and thereafter, forming a dielectric film of the capacitor in contact with a side surface of the one electrode and the other electrode of the capacitor. And forming a capacitor by using one electrode and the other electrode of the capacitor and the dielectric film sandwiched between these side walls. A step of forming one electrode of the capacitor on the main surface side of the semiconductor substrate, a step of forming a dummy film on a side wall of the one electrode of the capacitor, and a step of filling the gap between the dummy films. Forming the other electrode of the capacitor, removing the dummy film, and forming a dielectric film of the capacitor in a region where the dummy film has been removed. Forming a capacitor with the electrodes and the dielectric film sandwiched between these side walls. 3. The step of simultaneously forming one electrode and the other electrode of the capacitor on the main surface side of the semiconductor substrate, and the step of forming the dielectric of the capacitor in contact with the side surfaces of the one electrode and the other electrode of the simultaneously formed capacitor. Forming a capacitor, wherein the capacitor is formed by one electrode and the other electrode of the capacitor and the dielectric film sandwiched between these side walls. 4. The step of simultaneously forming one electrode and the other electrode of the capacitor includes forming a conductor film to be one electrode and the other electrode of the capacitor, and forming a first film on the conductor film. Forming a mask film, forming a second mask film on a side wall of the first mask film, and removing the conductive film using the first and second mask films as a mask. 4. The method for manufacturing a semiconductor device according to claim 3, comprising: 5. The method according to claim 1, wherein a plurality of one electrodes of the capacitor are formed apart from each other, and the other electrode of the capacitor is formed so as to surround the plurality of one electrodes. The method for manufacturing a semiconductor device according to any one of the above. 6. One electrode and the other electrode of a capacitor formed on the main surface side of the semiconductor substrate with a substantially uniform thickness;
A capacitor dielectric film that is in contact with the side surfaces of the one electrode and the other electrode of the capacitor; and the capacitor is formed by the one electrode and the other electrode of the capacitor and the dielectric film sandwiched between these side walls. A semiconductor device characterized by being constituted.