JPH11176171A - Method for initializing electrically rewritable non-volatile semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for initializing a non-volatile semiconductor storage that can be rewritten electrically to reduce the fluctuation of a threshold voltage, and at the same time to prevent abnormal operation, problems regarding reliability, and the increase in erasure time. SOLUTION: A method includes process 101 for repeating erasure operation and erasure verification and performing excessive erasure until a lower value as compared with a desired threshold voltage is reached, writing back process 102 for repeating verification for checking writing back operation and the lower limit of the threshold voltage and executing the threshold voltage until a desired value is reached, and verification process 103 for verifying that the upper limit of the threshold voltage at that time is equal to or smaller than a value. In the method, the processes 101, 102, and 103 are performed in this order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of initializing an electrically rewritable nonvolatile semiconductor memory device, and more particularly, to a method of initializing an electrically rewritable nonvolatile semiconductor memory device before programming data or at the time of shipment from a factory. About.

[0002]

2. Description of the Related Art In recent years, as the capacity of semiconductor memory devices has increased, there has been a possibility of opening new application fields. One of them is an electrically rewritable nonvolatile semiconductor memory device. In particular, a flash memory is in the spotlight.

The flash memory is expected to have a large market application in the future because it can store data without backing up a battery and can easily have a large capacity like a DRAM.

On the other hand, this flash memory has some problems to be overcome. For example, there are long erasing and writing times, two power supplies are required at present, and it is more difficult to handle low voltages than other devices.

Among them, the threshold voltage of the memory cell at the time of erasing is not so low as to be lower than the word line voltage at the time of selection and to such an extent that no leak current is generated in the type having one memory transistor per cell. There is also a problem that it must be controlled.

That is, it is necessary to suppress the variation of the cell threshold voltage at the time of erasing within a certain range. In particular, in order to realize low-voltage reading, it is very important to reduce variation in threshold voltage.

Further, various measures have been proposed and attempted to date to reduce the variation in the threshold voltage of the memory cell when erasing the flash memory, which is the most important factor for improving the yield of the flash memory. ing. Variations in the threshold voltage cause the thickness and film quality of the transistor,
Because of process-related factors such as the profile of a semiconductor substrate, the main one is an approach for realizing a memory cell having essentially small variation through process improvement.

However, in this measure, if the content of the improvement (for example, the optimal setting of the process conditions) shifts or includes variations, the improvement effect changes accordingly (in most cases, the effect decreases). I cannot exclude instability.

That is, if the process measures themselves deviate, the effect is sharply reduced, and in any case, it cannot be a fundamental measure to suppress the variation of the threshold voltage to a certain fixed value or less. It is. In this case, the erasing flow to be performed must be the same as the conventional one. Based on this flow, a memory cell having a variation in the threshold voltage of the memory cell equal to or less than a certain value is determined as a non-defective product. Inadequate measures will reduce the number of good products.

FIG. 2 shows an erasing flow of a conventional erasing method for a flash memory.

Conventionally, in order to narrow the threshold voltage distribution at the time of erasing, a pre-writing routine (20) in which all memory cells included in a range (block) to be erased are written in advance.
1) had been adopted. After that, an erase routine for erasing by repeatedly applying a relatively short pulse is executed (202). In the erase verify, it is determined whether or not the upper limit of the threshold voltage distribution of the memory cell becomes a certain value VEV (for example, 3 V), and the erase is repeated until the upper limit is passed.

At the time when the erasing routine 202 is completed, the entire erasing may be completed. In some cases, the lower limit of the threshold voltage distribution of the memory cell may have a value VDV (for example, 0.5).
V) A threshold voltage lower limit value check routine 203 for checking whether or not the value is equal to or lower than the threshold value may be added.

If the lower limit value is lower than a certain value VDV, a leak current is generated even in a non-selected state of the cell. Therefore, at the time of reading, the data of all the bit lines connected to the cell become "1" (ON). At the time of writing, there is a possibility that inconvenience such that writing cannot be performed on the bit line due to the leak. Since this check is for a problem that occurs in the unit of a bit line as described above, it is performed in the unit of a bit line (it is not necessary to perform the check in a unit of a cell).

The change in the threshold voltage distribution is shown in FIG.
(A).

Referring to FIG. 3 showing a block diagram of a flash memory, in this flash memory, memory cells M00 to Mnm included in cell array 1 have control gates commonly connected by word lines X0 to Xn and drains to bit lines. In this configuration, they are commonly connected and enter the column selection transistor group 2. In the transistor group 2, a bit line is selected by the column selection transistors TY0 to TYm. The source of the memory cell transistor is one block (1
Erasing unit), and the erasing voltage is supplied from the erasing circuit 5 (in other cases, ground).
Word lines X0 to Xn and column select transistors TY0 to TYm
Are supplied from the row decoder 3, for example, the decoder 4.

Further, an input / output bus line BSk grouped for each input / output by the column selection transistor group 2 is input to the sense amplifier 6 and receives data from the memory cell through an input / output buffer 8 to a data input / output terminal. I /
This is a configuration for outputting to O.

On the other hand, write data is transmitted to the data input / output terminal I.
/ O is input through the input / output buffer 8 and an appropriate write voltage is applied to the drain of the memory cell selected by the write circuit 7.

In order to perform the entire erase routine shown in FIG. 2, a write / erase sequence control circuit and a voltage supply circuit 9 supply various signals and voltages to the respective circuits. In a flash memory, an operation instruction is performed in a command format. Therefore, the command control circuit 10 receives the command, and the write / erase sequence control circuit 10 receives the command, and instructs the write / erase sequence control circuit (9) about the operation.

FIGS. 4 to 8 show a row decoder 3, a column decoder 4, an erase circuit 5, a sense amplifier 6, and a write circuit 7, respectively.
1 shows an example of the circuit.

A write / erase sequence control circuit and a voltage supply circuit 9 receive signals and voltages supplied to each circuit, and perform predetermined operations in a predetermined routine. In particular, in the threshold voltage lower limit check routine 203 shown in FIG. 2, the voltage applied to the word line (corresponding to the threshold voltage VDV of the memory cell of about 0.5 V) is input from the VSX terminal and the NA
By controlling the input of the ND circuit 401, all selections are made (Tn2 becomes conductive in all the row decoders), and at the same time, the Vsx voltage is applied to all the word lines. As a result, a check can be performed in units of bit lines. Also, by changing the current value of the variable constant current source 705 in the sense amplifier of FIG.
Level), erase verify (threshold voltage upper limit value VEV is 3
V) and threshold voltage lower limit check (threshold voltage lower limit value VDV is approximately 0.5 V).

In recent years, several attempts have been made to reduce the variation of the threshold voltage after erasing systematically, that is, by adding an internal operation.

The first prior art is "A SELF-C".
ONVERENCE ERASING SCHEME
FOR A SIMPLE STACKED GAT
EFLASH EEPROM ”(1991)
Year, IEDM Technical Digest,
S. Yamada, et. , PP. 307-310).

This is due to the injection of avalanche hot carriers induced by channel (hot) electrons by applying a high voltage to the drain or source of the memory cell after erasing and grounding the other (the control electrode is also grounded). And converge to a certain threshold voltage.

A second prior art is “A Novel”.
Erasing Technology for
3.3V Flash Memory with 64
MbCapacity and Beyond "(1992, IEDM Technical D
egest, K.C. Oyama et. , PP. 607-
610).

This technique utilizes the fact that the barrier height variation in FN tunneling is smaller when moving electrons from the substrate to the floating gate than when moving electrons from the floating gate to the substrate. Variation is reduced by applying a voltage.

As a third prior art, Japanese Patent Laid-Open No.
No. 130995.

This includes a method of performing write-back after erasing by using a small electric field in a direction opposite to the erasing.

[0028]

The erasing of the conventional nonvolatile semiconductor memory device described above has the following problems.

First, if no system countermeasures shown in FIG. 2 are taken, a certain degree of variation in threshold voltage due to process fluctuations must be anticipated. There were problems such as difficulty in reading.

In the flow shown in FIG. 2, the pre-write flow 201 is indispensable for securing a certain amount of variation, and it cannot be saved. Therefore, there is a problem that the erasing time is significantly increased.

Next, as for the system measures, as described in the above-mentioned literatures and publications, since a verify operation is not assumed, a normal effect can be obtained by setting the applied pulse width incorrectly. In order to avoid this, there is a problem that it is necessary to give a margin to the setting, which causes an increase in the total erasing time.

Further, in the first prior art in which a systematic measure is taken, hot holes are injected into cells having a threshold voltage higher than the convergence value of the threshold voltage, which is reliable. It has a serious problem in terms of sex. Therefore, it is necessary to ensure that the distribution of the threshold voltages after erasure is all lower than the convergence value.

[0033]

According to the present invention, there is provided a method for initializing an electrically rewritable nonvolatile semiconductor memory device, wherein an erasing operation for one erasing unit is included in the one erasing unit following the erasing operation. And a first verify operation for verifying that the threshold voltage of all the memory cells to be applied is lower than or equal to the first memory cell threshold voltage upper limit value. Repeating the steps until the first memory cell threshold voltage becomes equal to or lower than the upper limit value; and performing a write-back operation on the one erase unit and all the memory cells included in the one erase unit following the write-back operation. And a second verify operation for verifying that the threshold voltage is equal to or higher than the lower limit value of the threshold voltage of the first memory cell. A write-back process repeated until the threshold voltage becomes equal to or higher than the lower limit voltage, and the threshold voltage of all the memory cells included in the one erase unit is equal to or lower than the second memory cell threshold voltage upper limit. And a third verify step for verifying that the first memory cell threshold voltage upper limit is greater than the second memory cell threshold voltage upper limit. Features.

Further, the method for initializing an electrically rewritable nonvolatile semiconductor memory device according to the present invention includes a step of performing an erasing operation for a predetermined time determined for one erasing unit, and a write-back operation for the one erasing unit. And verifying that the threshold voltage of all of the memory cells included in the one erase unit following the write-back operation is equal to or higher than the first memory cell threshold voltage lower limit value. A write-back step of repeating the verify operation of Step 2 until all the threshold voltages of the memory cells become equal to or higher than the lower limit value of the threshold voltage of the first memory cell. And a third verifying step for verifying that the threshold voltage of all the memory cells is equal to or lower than the upper limit value of the threshold voltage of the second memory cell.

Further, the method for initializing an electrically rewritable nonvolatile semiconductor memory device according to the present invention may have a configuration in which the third verifying step is omitted.

Still further, in the initialization method of the electrically rewritable nonvolatile semiconductor memory device according to the present invention, the pre-writing operation for the one erasing unit and the pre-writing operation following the pre-writing operation immediately before the erasing step are performed. And performing a fourth verify operation for verifying that the threshold voltage of all the memory cells included in one erase unit is equal to or higher than the second memory cell threshold voltage lower limit value. May be added to repeat the pre-writing process until all the threshold voltages of the second memory cell become the second memory cell threshold voltage lower limit value or more.

Still further, in the method for initializing an electrically rewritable nonvolatile semiconductor memory device according to the present invention, the write-back operation is performed by applying a constant voltage to a source or a drain of the memory cell and grounding the other. It is also possible to adopt a configuration in which the execution is performed simultaneously on all the memory cells included in the erase unit.

Further, in the initialization method of the electrically rewritable nonvolatile semiconductor memory device according to the present invention, the write-back operation is included in the one erase unit by applying a constant voltage to a control gate of a memory cell. It is also possible to adopt a configuration in which the operation is performed simultaneously on all the memory cells.

[0039]

According to the method for initializing an electrically rewritable nonvolatile semiconductor memory device of the present invention, the upper limit of the threshold voltage of the memory cell is lower than the first constant value (VEEV) (the desired threshold voltage). → Over-erase) A routine that repeatedly performs erasure and verify check until it becomes less than or equal to, and applies a high voltage to the control gate of the memory cell, or a write-back by applying a high voltage to the source or drain and grounding the other. And a routine that repeats until the lower limit of the threshold voltage of the memory cell reaches or exceeds the second constant value (VDV), and finally, the upper limit of the threshold voltage of the memory cell becomes the third constant value (VEV) A routine for verifying that the threshold voltage is equal to or less than the second constant value VDV and equal to or less than the third constant value VEV is configured (each voltage is shown in FIG. 11).
(B)), thereby not increasing the operation or erasing time as long as it is caused by performing erasing or rewriting by a predetermined pulse without verifying without reliability. This has the effect of narrowing the threshold voltage distribution.

[0040]

Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a flow chart of a method for initializing an electrically rewritable nonvolatile semiconductor memory device according to a first embodiment of the present invention. In this case, the pre-writing routine (step 201 in FIG. 2) which has been conventionally performed is omitted.

First, verification is performed while repeatedly applying a pulse relatively longer than in the conventional example, and the upper limit of the threshold voltage distribution of the memory cell is set to a desired value (meaning after the end of the erase operation) (VEV). Lower than (VEEV) → that is, execute (over) erase (step 10)
1). FIG. 11B shows the relationship between the threshold voltage distributions.
Shown in

Thereafter, the write-back operation is performed by repeating the application of a relatively long pulse, and the write-back operation is performed based on the result of verifying whether the lower limit of the threshold voltage distribution of the memory cell is equal to or higher than a predetermined value (VDV). Is stopped (step 102).

Finally, as a confirmation, it is checked that the upper limit of the threshold voltage is equal to or lower than the desired value (VEV) (step 103), and the operation is completed.

Performing the (over) erase routine (101) once has the following remarkable points.

First, due to the characteristics of the memory cell, when the threshold voltage becomes negative, the electric field becomes small and erasing becomes difficult. This means that the lower limit of the threshold voltage is saturated at a certain negative value, which leads to a reduction in distribution.

Second, in the write-back method in which a high voltage is applied to the source or drain and the other is grounded, the injection of hot holes is a problem in reliability as described above. Over-erasure is necessary to guarantee injection.

Third, in the write-back method in which a high voltage is applied to the control gate, there is an effect of reducing variation but no self-convergence effect.

From the first viewpoint of this reason, it is considered that there is not much trouble even in (over) erasure by the verification.

Further, if the threshold voltage variation can be reliably reduced by rewriting, the threshold voltage upper limit value check 103, which is the final routine shown in FIGS. 1 and 9, can be omitted.

These routines can be realized by the conventional circuit shown in FIG.

That is, it can be realized only by changing the contents and order of the signals output from the write / erase sequence control circuit 9 to each circuit.

Next, the specific operation of the write-back routine (102) will be described.

First, in a system in which a high voltage is applied to the source or drain and the other is grounded, a voltage is applied from the erasing circuit 5 or the column selection transistor TY0 to TYm is controlled by controlling the column decoder 4. All are conducted, and a voltage is applied from the write circuit 7.

Next, in the method of applying a high voltage to the control gate, the row decoder 3 is controlled to control all the word lines X0 to X0.
Xn is selected and brought to a high potential.

Next, an initialization method of the electrically rewritable nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described.

Referring to FIG. 10 showing an erasing flow of the initialization method according to the second embodiment of the present invention, the initialization method according to this embodiment is different from the initialization method according to the first embodiment in the flow chart of FIG.
The (over) erase routine 101 has the same steps as the initialization method of the first embodiment except that the same pre-writing flow as the pre-writing routine 201 of the conventional initialization method is added before the erasure routine 101. Therefore, a detailed description of the operation is omitted.

As a result, the threshold voltage distribution is further reduced, and the narrower the threshold voltage distribution before erasing is, the narrower the distribution obtained as a result of subsequent operations is realized. There are effects that can be done. In addition, since there is no need to perform over-erasing too much, there is an effect that the total erasing time does not increase.

[0059]

As described above, the present invention relates to a method for erasing (initializing) a flash memory, in which once over-erasing is performed, simultaneous rewriting is performed in units of erasing, and the lower limit of the memory cell threshold voltage is reduced. The method of executing while checking until a certain value or more is adopted, so that the operation and the erasing time are not increased more than caused by not performing the verification, and the threshold voltage distribution is set to the initial value of the conventional example. This has the effect that it can be reduced to about 1/2 to 3/4 as compared with the conversion method.

[Brief description of the drawings]

FIG. 1 is a diagram showing an erase (initialization) flow of an initialization method for an electrically rewritable nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an erasing (initializing) flow in a conventional technique.

FIG. 3 is a block diagram of a flash memory.

FIG. 4 is a circuit diagram of a row decoder of the flash memory shown in FIG. 3;

FIG. 5 is a circuit diagram of a column decoder of the flash memory shown in FIG. 3;

6 is a circuit diagram of an erase circuit of the flash memory shown in FIG.

FIG. 7 is a circuit diagram of a sense amplifier of the flash memory shown in FIG. 3;

FIG. 8 is a circuit diagram of a sense amplifier of the flash memory shown in FIG. 3;

FIG. 9 is a diagram showing a flow of erasing (initializing) a modification of the initialization method according to the first embodiment of the present invention.

FIG. 10 shows erasing (initialization) of an initialization method for an electrically rewritable nonvolatile semiconductor memory device according to a second embodiment of the present invention;
It is a figure showing a flow.

11A is a diagram showing a distribution of memory cell threshold voltages, FIG. 11A is a diagram showing a memory cell threshold voltage distribution in a conventional example, and FIG. 11B is a diagram showing a memory cell threshold voltage in the present invention; It is a figure showing distribution.

[Explanation of symbols]

 Reference Signs List 1 memory cell array 2 column selection transistor group 3 row decoder 4 column decoder 5 erase circuit 6 sense amplifier 7 write circuit 8 input / output buffer 9 write / erase sequence control circuit + voltage supply circuit 10 command control circuit Y0 to Ym column decoder output X0 to Ym word line TY0 to TYm column selection transistor M00 to Mnm memory cell transistor S memory cell source BS0 to BSk bus line CTR control terminal I / O data input / output terminal ADD address terminal 101 (over) erase routine 102 write-back routine 103 threshold Value voltage upper limit check routine 201 Pre-write routine 202 Erase routine 203 Threshold voltage lower limit check routine AXY address AY Column address EPC Allowable limit of erase count DPC Allowable limit of writeback count Permissible limit value of PPC pre-write count 401, 501, 601, 801 NAND circuit 602, 701 to 704 Inverter Tn1 to Tn17 n-channel transistor TP1 to TP13 P-channel transistor VPX row system power supply voltage VCC power supply voltage VSX threshold voltage lower limit value Check voltage VPY Column system power supply voltage VPP Write power supply voltage ER Erase control signal ABK Block address select signal 705 Variable constant current source VPG Write circuit voltage DATA Input data signal PG write control signal VPV Write threshold voltage lower limit value VEV Erase Threshold voltage upper limit value at the time of erasing VDV threshold voltage lower limit at the time of erasing VEEEV threshold voltage at the time of overerasing

Claims (7)

[Claims] 1. A method for initializing an electrically rewritable nonvolatile semiconductor memory device having one erase unit including a plurality of nonvolatile memory cells, the method comprising: A first step of performing an erasing operation to lower the threshold voltage of these memory cells to a first voltage or less, and performing a writing operation on the memory cells included in the one erasing unit to perform a erasing operation on these memory cells. A second step of setting a threshold voltage to be equal to or higher than a second voltage, and that a threshold voltage of the memory cell included in the one erase unit is equal to or lower than a third voltage higher than the first voltage. Confirming that the threshold voltages of these memory cells have converged to the second voltage or more and the third voltage or less by confirming the electrically rewritable nonvolatile semiconductor memory. Initial equipment Method. 2. The erasing threshold voltage lower limit, the third voltage is an erasing threshold voltage upper limit, and the first voltage is the erasing threshold. An over-erase threshold voltage upper limit lower than a value voltage upper limit, and the first step is to change the threshold voltage of the memory cell included in the one erase unit to the over-erase threshold voltage. 2. An over-erasing process for reducing the temperature to an upper limit or less.
An initialization method for the electrically rewritable nonvolatile semiconductor memory device described in the above. 3. An erase unit including a plurality of nonvolatile memory cells, wherein threshold voltages of all memory cells included in the one erase unit are equal to or less than an upper threshold voltage during erase. A first step of performing an over-erasing operation on all the memory cells included in the one erasing unit; A second step of performing a write-back operation on the memory cells included in the unit. A method for initializing an electrically rewritable nonvolatile semiconductor memory device, comprising: 4. The method according to claim 1, wherein the threshold voltages of all the memory cells included in the one erase unit are equal to or lower than an over-erase threshold voltage upper limit lower than the erase threshold voltage upper limit. The step of confirming is performed subsequent to the first step, and the step of confirming that the threshold voltages of all memory cells included in the one erase unit are equal to or higher than the lower threshold voltage at the time of erase 4. The method according to claim 3, wherein the step (c) is performed subsequent to the second step. 5. The method according to claim 3, further comprising, prior to the first step, a step of pre-writing all memory cells included in the one erase unit. A method for initializing a rewritable nonvolatile semiconductor memory device. 6. A method for initializing a threshold voltage of a plurality of nonvolatile memory cells to be equal to or lower than an upper threshold voltage during erasing and equal to or higher than a lower threshold value during erasing. Over-erasing operation without performing pre-programming on the memory cells, and setting the threshold voltages of these memory cells to be equal to or less than the over-erasing threshold voltage upper limit lower than the erasing threshold voltage upper limit. A first step and a second step performed after the first step, wherein a write-back operation is performed on the memory cells and the threshold voltages of these memory cells are changed to the threshold voltage at the time of erasing. The second to be more than the lower limit
The method for initializing the electrically rewritable nonvolatile semiconductor memory device, comprising the steps of: 7. A third step performed after the second step, wherein the third step of confirming that the threshold voltage of the memory cell is equal to or lower than the upper limit value of the threshold voltage during erasing. 7. The method for initializing an electrically rewritable nonvolatile semiconductor memory device according to claim 6, further comprising a step.